urjtag/jtag/doc/doc-layout.txt

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<!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.5//EN"
         "http://www.oasis-open.org/docbook/xml/4.5/docbookx.dtd" [
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<book>
<title>UrJTAG</title>
<toc/>

<chapter><title>General</title>

  <section><title>The name "UrJTAG"</title> <para/></section>
  <section><title>Authors, contributors, ... thanks</title><para/></section>
  <section><title>Copyright/Licensing</title> <para/> <para/></section>
  <section><title>UrJTAG/openwince history</title> <para/> <para/></section>
  <section><title>Installation </title><para/></section>
  <section><title>from binary tarball </title><para/></section>
  <section><title>from source tarball </title><para/></section>
  <section><title>from svn </title><para/></section>
  <section><title>Cygwin/MinGW specifics </title><para/></section>
  <section><title>Getting updates </title><para/></section>
  <section><title>Further info / support</title><para/></section>
</chapter>

<chapter><title>Usage</title>

  <section><title> Quick start: flash example </title><para/></section>
  <section><title> Configuration, cable setup </title><para/></section>
  <section><title> Chain setup </title><para/></section>
  <section><title> Part setup </title><para/></section>
  <section><title> Doing things with parts </title><para/></section>
  <section><title> Pin I/O </title><para/></section>
  <section><title> Memory I/O </title><para/></section>
  <section><title> FPGA configuration </title><para/></section>
  <section><title> Flash programming </title><para/></section>
  <section><title> ...  </title><para/></section>
  <section><title> SVF Player </title><para/></section>
  <section><title> bsdl2jtag, data files </title><para/></section>
  <section><title> target specific documentation</title><para/></section>
  <section><title> EJTAG support </title><para/></section> 
  <section><title> Blackfin support (when available) </title><para/></section> 
</chapter>

<chapter><title> Internals </title>

<section><title> How to</title>
  <para>
      .. add a part
      .. add a command
      .. add a bus driver
      .. add a cable driver
      ,,
     .. create a patch and upload to SF
  </para>
  <para/></section>
  <section><title> Directory structure</title>
  <para>
    data/
    ./include/
    ../include/
    libbrux/
      cmd/ flash/
    src/
      bus/ cmd/ lib/ tap/ svf/
  </para>
  <para/></section>
  <section><title> Cable driver interface</title>
  <para>
      parport
      cable
      chain
  </para>
  <para/></section> 
  <section><title> Bus driver interface </title><para/></section>
  <section><title> target specific internals  </title><para/></section><section><title>
  </title><para/></section>
</chapter>

<chapter><title> Frequently asked questions </title>

  <section><title> Cygwin/MinGW </title><para/></section>
  <section><title> Compilation problems </title><para/></section>
</chapter>

<chapter><title>Future plans</title>

    <section><title> API and library package
    </title><para/></section><section><title> Bindings for Python, Perl, ...
    </title><para/></section><section><title> TCP/IP access
    </title><para/></section><section><title> New cable drivers
    </title><para/></section><section><title> ...
    </title><para/></section>
</chapter>

<appendix><title> UrJTAG quick reference</title><para/> </appendix>

<appendix><title> Exkurs: JTAG </title><para/></appendix>

<appendix><title>UrJTAG Revision information</title><para/> </appendix>

<appendix><title>UrJTAG Licenses</title><para/> </appendix>

</book>