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@ -23,6 +23,7 @@
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#include <stdlib.h>
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#include <string.h>
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#include <time.h>
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#include <unistd.h>
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#include <urjtag/chain.h>
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#include <urjtag/tap_state.h>
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@ -1537,13 +1538,33 @@ chain_system_reset (urj_chain_t *chain)
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p0 = part_get_p0 (chain, chain->main_part);
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r0 = part_get_r0 (chain, chain->main_part);
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/*
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* Flush all system events like cache line fills. Otherwise,
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* when we reset the system side, any events that the core was
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* waiting on no longer exist, and the core hangs.
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*/
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part_emuir_set (chain, chain->main_part, INSN_SSYNC, URJ_CHAIN_EXITMODE_IDLE);
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/* Write 0x7 to SWRST to start system reset. */
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part_set_p0 (chain, chain->main_part, SWRST);
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part_set_r0 (chain, chain->main_part, 0x7);
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part_emuir_set (chain, chain->main_part, gen_store16_offset (REG_P0, 0, REG_R0), URJ_CHAIN_EXITMODE_IDLE);
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part_emuir_set (chain, chain->main_part, INSN_SSYNC, URJ_CHAIN_EXITMODE_IDLE);
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/*
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* Delay at least 10 SCLKs instead of doing an SSYNC insn.
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* Since the system is being reset, the sync signal might
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* not be asserted, and so the core hangs waiting for it.
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* The magic "10" number was given to us by ADI designers
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* who looked at the schematic and ran some simulations.
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*/
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usleep (100);
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/* Write 0x0 to SWRST to stop system reset. */
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part_set_r0 (chain, chain->main_part, 0);
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part_emuir_set (chain, chain->main_part, gen_store16_offset (REG_P0, 0, REG_R0), URJ_CHAIN_EXITMODE_IDLE);
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part_emuir_set (chain, chain->main_part, INSN_SSYNC, URJ_CHAIN_EXITMODE_IDLE);
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/* Delay at least 1 SCLK; see comment above for more info. */
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usleep (100);
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part_set_p0 (chain, chain->main_part, p0);
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part_set_r0 (chain, chain->main_part, r0);
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