diff --git a/include/ChangeLog b/include/ChangeLog index 4bd9d7ae..d9f7c2f7 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,12 @@ +2005-05-31 Branislav Petrovsky + + * h8/h8s2357/bus.h: New file. + * h8/h8s2357/dmac.h: Ditto. + * h8/h8s2357/ic.h: Ditto. + * h8/h8s2357/ppg.h: Ditto. + * h8/h8s2357/wdt.h: Ditto. + * Makefile.am (nobase_openwinceinc_HEADERS): Added new files. + 2005-05-27 Branislav Petrovsky * h8/h8s2357/ports.h: New file. diff --git a/include/Makefile.am b/include/Makefile.am index 0f6986f4..b0d61586 100644 --- a/include/Makefile.am +++ b/include/Makefile.am @@ -87,12 +87,17 @@ nobase_openwinceinc_HEADERS = \ device/other/hd64461/stbsys.h \ device/other/hd64461/timer.h \ h8/h8s2357/adc.h \ + h8/h8s2357/bus.h \ h8/h8s2357/dac.h \ + h8/h8s2357/dmac.h \ h8/h8s2357/flash.h \ + h8/h8s2357/ic.h \ h8/h8s2357/ports.h \ + h8/h8s2357/ppg.h \ h8/h8s2357/sci.h \ h8/h8s2357/timer.h \ h8/h8s2357/tpu.h \ + h8/h8s2357/wdt.h \ sh/sh7750/ccn.h \ std/mic.h diff --git a/include/h8/h8s2357/bus.h b/include/h8/h8s2357/bus.h new file mode 100644 index 00000000..83099af2 --- /dev/null +++ b/include/h8/h8s2357/bus.h @@ -0,0 +1,191 @@ +/* + * $Id$ + * + * H8S/2357 BUS Controller Registers + * Copyright (C) 2005 Elcom s.r.o. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Written by Branislav Petrovsky , 2005. + * + * Documentation: + * [1] Renesas Technology Corp., "Hitachi 16-Bit Single-chip Microcomputer + * H8S/2357 Series, H8S/2357F-ZTAT, H8S/2398F-ZTAT Hardware Manual", + * Rev. 5.0, 11/22/02, Order Number: ADE-602-146D + * + */ + +#ifndef H8S2357_BUS_H +#define H8S2357_BUS_H + +#include + +#if LANGUAGE == C +#include +#endif + +/* BUS registers */ + +#define BUS_BASE 0xfffffed0 + +#if LANGUAGE == C +typedef struct BUS_registers { + uint8_t abwcr; + uint8_t astcr; + uint8_t wcrh; + uint8_t wcrl; + uint8_t bcrh; + uint8_t bcrl; + uint8_t mcr; + uint8_t dramcr; + uint8_t rtcnt; + uint8_t rtcor; + uint8_t __reserved; + uint8_t ramer; +} BUS_registers_t; + +#define BUS_pointer ((BUS_registers_t*) BUS_BASE) + +#define ABWCR BUS_pointer->abwcr +#define ASTCR BUS_pointer->astcr +#define WCRH BUS_pointer->wcrh +#define WCRL BUS_pointer->wcrl +#define BCRH BUS_pointer->bcrh +#define BCRL BUS_pointer->bcrl +#define MCR BUS_pointer->mcr +#define DRAMCR BUS_pointer->dramcr +#define RTCNT BUS_pointer->rtcnt +#define RTCOR BUS_pointer->rtcor +#define RAMER BUS_pointer->ramer +#endif /* LANGUAGE == C */ + +#define ABWCR_OFFSET 0x00 +#define ASTCR_OFFSET 0x01 +#define WCRH_OFFSET 0x02 +#define WCRL_OFFSET 0x03 +#define BCRH_OFFSET 0x04 +#define BCRL_OFFSET 0x05 +#define MCR_OFFSET 0x06 +#define DRAMCR_OFFSET 0x07 +#define RTCNT_OFFSET 0x08 +#define RTCOR_OFFSET 0x09 +#define RAMER_OFFSET 0x0b + +/* ABWCR bits */ +#define ABWCR_ABW7 bit(7) +#define ABWCR_ABW6 bit(6) +#define ABWCR_ABW5 bit(5) +#define ABWCR_ABW4 bit(4) +#define ABWCR_ABW3 bit(3) +#define ABWCR_ABW2 bit(2) +#define ABWCR_ABW1 bit(1) +#define ABWCR_ABW0 bit(0) + +/* ASTCR bits */ +#define ASTCR_AST7 bit(7) +#define ASTCR_AST6 bit(6) +#define ASTCR_AST5 bit(5) +#define ASTCR_AST4 bit(4) +#define ASTCR_AST3 bit(3) +#define ASTCR_AST2 bit(2) +#define ASTCR_AST1 bit(1) +#define ASTCR_AST0 bit(0) + +/* WCRH bits */ +#define WCRH_W7_MASK bits(7,6) +#define WCRH_W7(x) bits_val(7,6,x) +#define get_WCRH_W7(x) bits_get(7,6,x) +#define WCRH_W6_MASK bits(5,4) +#define WCRH_W6(x) bits_val(5,4,x) +#define get_WCRH_W6(x) bits_get(5,4,x) +#define WCRH_W5_MASK bits(3,2) +#define WCRH_W5(x) bits_val(3,2,x) +#define get_WCRH_W5(x) bits_get(3,2,x) +#define WCRH_W4_MASK bits(1,0) +#define WCRH_W4(x) bits_val(1,0,x) +#define get_WCRH_W4(x) bits_get(1,0,x) + +/* WCRL bits */ +#define WCRL_W3_MASK bits(7,6) +#define WCRL_W3(x) bits_val(7,6,x) +#define get_WCRL_W3(x) bits_get(7,6,x) +#define WCRL_W2_MASK bits(5,4) +#define WCRL_W2(x) bits_val(5,4,x) +#define get_WCRL_W2(x) bits_get(5,4,x) +#define WCRL_W1_MASK bits(3,2) +#define WCRL_W1(x) bits_val(3,2,x) +#define get_WCRL_W1(x) bits_get(3,2,x) +#define WCRL_W0_MASK bits(1,0) +#define WCRL_W0(x) bits_val(1,0,x) +#define get_WCRL_W0(x) bits_get(1,0,x) + +/* BCRH bits */ +#define BCRH_ICIS1 bit(7) +#define BCRH_ICIS0 bit(6) +#define BCRH_BRSTRM bit(5) +#define BCRH_BRSTS1 bit(4) +#define BCRH_BRSTS0 bit(3) +#define BCRH_RMTS_MASK bits(2,0) +#define BCRH_RMTS(x) bits_val(2,0,x) +#define get_BCRH_RMTS(x) bits_get(2,0,x) + +/* BCRL bits */ +#define BCRL_BRLE bit(7) +#define BCRL_BREQOE bit(6) +#define BCRL_EAE bit(5) +#define BCRL_LCASS bit(4) +#define BCRL_DDS bit(3) +#define BCRL_WDBE bit(1) +#define BCRL_WAITE bit(0) + +/* MCR bits */ +#define MCR_TPC bit(7) +#define MCR_BE bit(6) +#define MCR_RCDM bit(5) +#define MCR_CW2 bit(4) +#define MCR_MXC_MASK bits(3,2) +#define MCR_MXC(x) bits_val(3,2,x) +#define get_MCR_MXC(x) bits_get(3,2,x) +#define MCR_RLW_MASK bits(1,0) +#define MCR_RLW(x) bits_val(1,0,x) +#define get_MCR_RLW(x) bits_get(1,0,x) + +/* DRAMCR bits */ +#define DRAMCR_RFSHE bit(7) +#define DRAMCR_RCW bit(6) +#define DRAMCR_RMODE bit(5) +#define DRAMCR_CMF bit(4) +#define DRAMCR_CMIE bit(3) +#define DRAMCR_CKS_MASK bits(2,0) +#define DRAMCR_CKS(x) bits_val(2,0,x) +#define get_DRAMCR_CKS(x) bits_get(2,0,x) + +/* RAMER bits */ +#define RAMER_RAMS bit(3) +#define RAMER_RAM_MASK bits(2,0) +#define RAMER_RAM(x) bits_val(2,0,x) +#define get_RAMER_RAM(x) bits_get(2,0,x) + +#endif /* H8S2357_BUS_H */ diff --git a/include/h8/h8s2357/dmac.h b/include/h8/h8s2357/dmac.h new file mode 100644 index 00000000..3f81376b --- /dev/null +++ b/include/h8/h8s2357/dmac.h @@ -0,0 +1,184 @@ +/* + * $Id$ + * + * H8S/2357 DMAC Registers + * Copyright (C) 2005 Elcom s.r.o. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Written by Branislav Petrovsky , 2005. + * + * Documentation: + * [1] Renesas Technology Corp., "Hitachi 16-Bit Single-chip Microcomputer + * H8S/2357 Series, H8S/2357F-ZTAT, H8S/2398F-ZTAT Hardware Manual", + * Rev. 5.0, 11/22/02, Order Number: ADE-602-146D + * + */ + +#ifndef H8S2357_DMAC_H +#define H8S2357_DMAC_H + +#include + +#if LANGUAGE == C +#include +#endif + +/* DMAC registers */ + +#define DMAC_BASE 0xfffffee0 + +#if LANGUAGE == C +typedef struct DMAC_registers { + uint32_t mar0a; + uint16_t ioar0a; + uint16_t etcr0a; + uint32_t mar0b; + uint16_t ioar0b; + uint16_t etcr0b; + uint32_t mar1a; + uint16_t ioar1a; + uint16_t etcr1a; + uint32_t mar1b; + uint16_t ioar1b; + uint16_t etcr1b; + uint8_t dmawer; + uint8_t dmatcr; + uint8_t dmacr0a; + uint8_t dmacr0b; + uint8_t dmacr1a; + uint8_t dmacr1b; + uint8_t dmabcr; +} DMAC_registers_t; + +#define DMAC_pointer ((DMAC_registers_t*) DMAC_BASE) + +#define MAR0A DMAC_pointer->mar0a +#define IOAR0A DMAC_pointer->ioar0a +#define ETCR0A DMAC_pointer->etcr0a +#define MAR0B DMAC_pointer->mar0b +#define IOAR0B DMAC_pointer->ioar0b +#define ETCR0B DMAC_pointer->etcr0b +#define MAR1A DMAC_pointer->mar1a +#define IOAR1A DMAC_pointer->ioar1a +#define ETCR1A DMAC_pointer->etcr1a +#define MAR1B DMAC_pointer->mar1b +#define IOAR1B DMAC_pointer->ioar1b +#define ETCR1B DMAC_pointer->etcr1b +#define DMAWER DMAC_pointer->dmawer +#define DMATCR DMAC_pointer->dmatcr +#define DMACR0A DMAC_pointer->dmacr0a +#define DMACR0B DMAC_pointer->dmacr0b +#define DMACR1A DMAC_pointer->dmacr1a +#define DMACR1B DMAC_pointer->dmacr1b +#define DMABCR DMAC_pointer->dmabcr +#endif /* LANGUAGE == C */ + +#define MAR0A_OFFSET 0x00 +#define IOAR0A_OFFSET 0x04 +#define ETCR0A_OFFSET 0x06 +#define MAR0B_OFFSET 0x08 +#define IOAR0B_OFFSET 0x0c +#define ETCR0B_OFFSET 0x0e +#define MAR1A_OFFSET 0x10 +#define IOAR1A_OFFSET 0x14 +#define ETCR1A_OFFSET 0x16 +#define MAR1B_OFFSET 0x18 +#define IOAR1B_OFFSET 0x1c +#define ETCR1B_OFFSET 0x1e +#define DMAWER_OFFSET 0x20 +#define DMATCR_OFFSET 0x21 +#define DMACR0A_OFFSET 0x22 +#define DMACR0B_OFFSET 0x23 +#define DMACR1A_OFFSET 0x24 +#define DMACR1B_OFFSET 0x25 +#define DMABCR_OFFSET 0x26 + +/* DMAWER bits */ +#define DMAWER_WE1B bit(3) +#define DMAWER_WE1A bit(2) +#define DMAWER_WE0B bit(1) +#define DMAWER_WE0A bit(0) + +/* DMATCR bits */ +#define DMATCR_TEE1 bit(5) +#define DMATCR_TEE0 bit(4) + +/* DMACR bits - short address mode */ +#define DMACR_DTSZ bit(7) +#define DMACR_DTID bit(6) +#define DMACR_RPE bit(5) +#define DMACR_DTDIR bit(4) +#define DMACR_DTF_MASK bits(3,0) +#define DMACR_DTF(x) bits_val(3,0,x) +#define get_DMACR_DTF(x) bits_get(3,0,x) + +/* DMACRA bits - full address mode */ +#define DMACRA_DTSZ bit(7) +#define DMACRA_SAID bit(6) +#define DMACRA_SAIDE bit(5) +#define DMACRA_BLKDIR bit(4) +#define DMACRA_BLKE bit(3) + +/* DMACRB bits - full address mode */ +#define DMACRB_DAID bit(6) +#define DMACRB_DAIDE bit(5) +#define DMACRB_DTF_MASK bits(3,0) +#define DMACRB_DTF(x) bits_val(3,0,x) +#define get_DMACRB_DTF(x) bits_get(3,0,x) + +/* DMABCR bits - short address mode */ +#define DMABCR_FAE1 bit(15) +#define DMABCR_FAE0 bit(14) +#define DMABCR_SAE1 bit(13) +#define DMABCR_SAE0 bit(12) +#define DMABCR_DTA1B bit(11) +#define DMABCR_DTA1A bit(10) +#define DMABCR_DTA0B bit(9) +#define DMABCR_DTA0A bit(8) +#define DMABCR_DTE1B bit(7) +#define DMABCR_DTE1A bit(6) +#define DMABCR_DTE0B bit(5) +#define DMABCR_DTE0A bit(4) +#define DMABCR_DTIE1B bit(3) +#define DMABCR_DTIE1A bit(2) +#define DMABCR_DTIE0B bit(1) +#define DMABCR_DTIE0A bit(0) + +/* DMABCR bits - full address mode */ +#define DMABCR_FAE1 bit(15) +#define DMABCR_FAE0 bit(14) +#define DMABCR_DTA1 bit(11) +#define DMABCR_DTA0 bit(9) +#define DMABCR_DTME1 bit(7) +#define DMABCR_DTE1 bit(6) +#define DMABCR_DTME0 bit(5) +#define DMABCR_DTE0 bit(4) +#define DMABCR_DTIE1B bit(3) +#define DMABCR_DTIE1A bit(2) +#define DMABCR_DTIE0B bit(1) +#define DMABCR_DTIE0A bit(0) + +#endif /* H8S2357_DMAC_H */ diff --git a/include/h8/h8s2357/ic.h b/include/h8/h8s2357/ic.h new file mode 100644 index 00000000..d9d714fd --- /dev/null +++ b/include/h8/h8s2357/ic.h @@ -0,0 +1,157 @@ +/* + * $Id$ + * + * H8S/2357 Interrupt Controller (IC) Registers + * Copyright (C) 2005 Elcom s.r.o. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Written by Branislav Petrovsky , 2005. + * + * Documentation: + * [1] Renesas Technology Corp., "Hitachi 16-Bit Single-chip Microcomputer + * H8S/2357 Series, H8S/2357F-ZTAT, H8S/2398F-ZTAT Hardware Manual", + * Rev. 5.0, 11/22/02, Order Number: ADE-602-146D + * + */ + +#ifndef H8S2357_IC_H +#define H8S2357_IC_H + +#include + +#if LANGUAGE == C +#include +#endif + +/* interrupt registers */ + +#define IPR_BASE 0xfffffec4 +#define IC_BASE 0xffffff2c + +#if LANGUAGE == C +typedef struct IPR_registers { + uint8_t ipra; + uint8_t iprb; + uint8_t iprc; + uint8_t iprd; + uint8_t ipre; + uint8_t iprf; + uint8_t iprg; + uint8_t iprh; + uint8_t ipri; + uint8_t iprj; + uint8_t iprk; +} IPR_registers_t; + +typedef struct IC_registers { + uint16_t iscr; + uint8_t ier; + uint8_t isr; +} IC_registers_t; + +#define IPR_pointer ((IPR_registers_t*) IPR_BASE) +#define IC_pointer ((IC_registers_t*) IC_BASE) + +#define IPRA IPR_pointer->ipra +#define IPRB IPR_pointer->iprb +#define IPRC IPR_pointer->iprc +#define IPRD IPR_pointer->iprd +#define IPRE IPR_pointer->ipre +#define IPRF IPR_pointer->iprf +#define IPRG IPR_pointer->iprg +#define IPRH IPR_pointer->iprh +#define IPRI IPR_pointer->ipri +#define IPRJ IPR_pointer->iprj +#define IPRK IPR_pointer->iprk + +#define ISCR IC_pointer->iscr +#define IER IC_pointer->ier +#define ISR IC_pointer->isr +#endif /* LANGUAGE == C */ + +#define IPRA_OFFSET 0x00 +#define IPRB_OFFSET 0x01 +#define IPRC_OFFSET 0x02 +#define IPRD_OFFSET 0x03 +#define IPRE_OFFSET 0x04 +#define IPRF_OFFSET 0x05 +#define IPRG_OFFSET 0x06 +#define IPRH_OFFSET 0x07 +#define IPRI_OFFSET 0x08 +#define IPRJ_OFFSET 0x09 +#define IPRK_OFFSET 0x0a + +#define ISCR_OFFSET 0x00 +#define IER_OFFSET 0x02 +#define ISR_OFFSET 0x03 + +/* IPR bits */ +#define IPR_IPR6 bit(6) +#define IPR_IPR5 bit(5) +#define IPR_IPR4 bit(4) +#define IPR_IPR2 bit(2) +#define IPR_IPR1 bit(1) +#define IPR_IPR0 bit(0) + +/* ISCR bits */ +#define ISCR_IRQ7SCB bit(15) +#define ISCR_IRQ7SCA bit(14) +#define ISCR_IRQ6SCB bit(13) +#define ISCR_IRQ6SCA bit(12) +#define ISCR_IRQ5SCB bit(11) +#define ISCR_IRQ5SCA bit(10) +#define ISCR_IRQ4SCB bit(9) +#define ISCR_IRQ4SCA bit(8) +#define ISCR_IRQ3SCB bit(7) +#define ISCR_IRQ3SCA bit(6) +#define ISCR_IRQ2SCB bit(5) +#define ISCR_IRQ2SCA bit(4) +#define ISCR_IRQ1SCB bit(3) +#define ISCR_IRQ1SCA bit(2) +#define ISCR_IRQ0SCB bit(1) +#define ISCR_IRQ0SCA bit(0) + +/* IER bits */ +#define IER_IRQ7E bit(7) +#define IER_IRQ6E bit(6) +#define IER_IRQ5E bit(5) +#define IER_IRQ4E bit(4) +#define IER_IRQ3E bit(3) +#define IER_IRQ2E bit(2) +#define IER_IRQ1E bit(1) +#define IER_IRQ0E bit(0) + +/* ISR bits */ +#define ISR_IRQ7F bit(7) +#define ISR_IRQ6F bit(6) +#define ISR_IRQ5F bit(5) +#define ISR_IRQ4F bit(4) +#define ISR_IRQ3F bit(3) +#define ISR_IRQ2F bit(2) +#define ISR_IRQ1F bit(1) +#define ISR_IRQ0F bit(0) + +#endif /* H8S2357_IC_H */ diff --git a/include/h8/h8s2357/ppg.h b/include/h8/h8s2357/ppg.h new file mode 100644 index 00000000..b2c64e77 --- /dev/null +++ b/include/h8/h8s2357/ppg.h @@ -0,0 +1,176 @@ +/* + * $Id$ + * + * H8S/2357 PPG Registers + * Copyright (C) 2005 Elcom s.r.o. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Written by Branislav Petrovsky , 2005. + * + * Documentation: + * [1] Renesas Technology Corp., "Hitachi 16-Bit Single-chip Microcomputer + * H8S/2357 Series, H8S/2357F-ZTAT, H8S/2398F-ZTAT Hardware Manual", + * Rev. 5.0, 11/22/02, Order Number: ADE-602-146D + * + */ + +#ifndef H8S2357_PPG_H +#define H8S2357_PPG_H + +#include + +#if LANGUAGE == C +#include +#endif + +/* PPG registers */ + +#define PPG_BASE 0xffffff46 + +#if LANGUAGE == C +typedef struct PPG_registers { + uint8_t pcr; + uint8_t pmr; + uint8_t nderh; + uint8_t nedrl; + uint8_t podrh; + uint8_t podrl; + uint8_t ndrh; + uint8_t ndrl; + uint8_t ndrh_d; + uint8_t ndrl_d; +} PPG_registers_t; + +#define PPG_pointer ((PPG_registers_t*) PPG_BASE) + +#define PCR PPG_pointer->pcr +#define PMR PPG_pointer->pmr +#define NDERH PPG_pointer->nderh +#define NEDRL PPG_pointer->nedrl +#define PODRH PPG_pointer->podrh +#define PODRL PPG_pointer->podrl +#define NDRH PPG_pointer->ndrh +#define NDRL PPG_pointer->ndrl +#define NDRH_d PPG_pointer->ndrh_d +#define NDRL_d PPG_pointer->ndrl_d +#endif /* LANGUAGE == C */ + +#define PCR_OFFSET 0x00 +#define PMR_OFFSET 0x01 +#define NDERH_OFFSET 0x02 +#define NEDRL_OFFSET 0x03 +#define PODRH_OFFSET 0x04 +#define PODRL_OFFSET 0x05 +#define NDRH_OFFSET 0x06 +#define NDRL_OFFSET 0x07 +#define NDRH_OFFSET_d 0x08 +#define NDRL_OFFSET_d 0x09 + +/* PCR bits */ +#define PCR_G3CMS_MASK bits(7,6) +#define PCR_G3CMS(x) bits_val(7,6,x) +#define get_PCR_G3CMS(x) bits_get(7,6,x) +#define PCR_G2CMS_MASK bits(5,4) +#define PCR_G2CMS(x) bits_val(5,4,x) +#define get_PCR_G2CMS(x) bits_get(5,4,x) +#define PCR_G1CMS_MASK bits(3,2) +#define PCR_G1CMS(x) bits_val(3,2,x) +#define get_PCR_G1CMS(x) bits_get(3,2,x) +#define PCR_G0CMS_MASK bits(1,0) +#define PCR_G0CMS(x) bits_val(1,0,x) +#define get_PCR_G0CMS(x) bits_get(1,0,x) + +/* PMR bits */ +#define PMR_G3INV bit(7) +#define PMR_G2INV bit(6) +#define PMR_G1INV bit(5) +#define PMR_G0INV bit(4) +#define PMR_G3NOV bit(3) +#define PMR_G2NOV bit(2) +#define PMR_G1NOV bit(1) +#define PMR_G0NOV bit(0) + +/* NDERH bits */ +#define NDERH_NDER15 bit(7) +#define NDERH_NDER14 bit(6) +#define NDERH_NDER13 bit(5) +#define NDERH_NDER12 bit(4) +#define NDERH_NDER11 bit(3) +#define NDERH_NDER10 bit(2) +#define NDERH_NDER9 bit(1) +#define NDERH_NDER8 bit(0) + +/* NDERL bits */ +#define NDERL_NDER7 bit(7) +#define NDERL_NDER6 bit(6) +#define NDERL_NDER5 bit(5) +#define NDERL_NDER4 bit(4) +#define NDERL_NDER3 bit(3) +#define NDERL_NDER2 bit(2) +#define NDERL_NDER1 bit(1) +#define NDERL_NDER0 bit(0) + +/* PODRH bits */ +#define PODRH_POD15 bit(7) +#define PODRH_POD14 bit(6) +#define PODRH_POD13 bit(5) +#define PODRH_POD12 bit(4) +#define PODRH_POD11 bit(3) +#define PODRH_POD10 bit(2) +#define PODRH_POD9 bit(1) +#define PODRH_POD8 bit(0) + +/* PODRL bits */ +#define PODRL_POD7 bit(7) +#define PODRL_POD6 bit(6) +#define PODRL_POD5 bit(5) +#define PODRL_POD4 bit(4) +#define PODRL_POD3 bit(3) +#define PODRL_POD2 bit(2) +#define PODRL_POD1 bit(1) +#define PODRL_POD0 bit(0) + +/* NDRH bits */ +#define NDRH_NDR15 bit(7) +#define NDRH_NDR14 bit(6) +#define NDRH_NDR13 bit(5) +#define NDRH_NDR12 bit(4) +#define NDRH_NDR11 bit(3) +#define NDRH_NDR10 bit(2) +#define NDRH_NDR9 bit(1) +#define NDRH_NDR8 bit(0) + +/* NDRL bits */ +#define NDRL_NDR7 bit(7) +#define NDRL_NDR6 bit(6) +#define NDRL_NDR5 bit(5) +#define NDRL_NDR4 bit(4) +#define NDRL_NDR3 bit(3) +#define NDRL_NDR2 bit(2) +#define NDRL_NDR1 bit(1) +#define NDRL_NDR0 bit(0) + +#endif /* H8S2357_PPG_H */ diff --git a/include/h8/h8s2357/wdt.h b/include/h8/h8s2357/wdt.h new file mode 100644 index 00000000..669852c9 --- /dev/null +++ b/include/h8/h8s2357/wdt.h @@ -0,0 +1,105 @@ +/* + * $Id$ + * + * H8S/2357 WDT Registers + * Copyright (C) 2005 Elcom s.r.o. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Written by Branislav Petrovsky , 2005. + * + * Documentation: + * [1] Renesas Technology Corp., "Hitachi 16-Bit Single-chip Microcomputer + * H8S/2357 Series, H8S/2357F-ZTAT, H8S/2398F-ZTAT Hardware Manual", + * Rev. 5.0, 11/22/02, Order Number: ADE-602-146D + * + */ + +#ifndef H8S2357_WDT_H +#define H8S2357_WDT_H + +#include + +#if LANGUAGE == C +#include +#endif + +/* WDT registers */ + +#define WDT_BASE 0xffffffbc + +#if LANGUAGE == C +typedef struct WDT_registers { + union { + union { + uint16_t tcsr; + uint16_t tcnt; + } _write; + struct { + uint8_t tcsr; + uint8_t tcnt; + } _read; + } _timer; + union { + union { + uint16_t rstcsr; + } _write; + struct { + uint8_r __reserved; + uint8_t rstcsr; + } _read; + } _rstcsr; +} WDT_registers_t; + +#define WDT_pointer ((WDT_registers_t*) WDT_BASE) + +#define TCSR_r WDT_pointer->_timer._read.tcsr +#define TCNT_r WDT_pointer->_timer._read.tcnt +#define RSTCSR_r WDT_pointer->_rstcsr._read.rstcsr +#define TCSR_w WDT_pointer->_timer._write.tcsr +#define TCNT_w WDT_pointer->_timer._write.tcnt +#define RSTCSR_w WDT_pointer->_rstcsr._write.rstcsr +#endif /* LANGUAGE == C */ + +#define TCSR_OFFSET 0x00 +#define TCNT_OFFSET_w 0x00 +#define TCNT_OFFSET_r 0x01 +#define RSTCSR_OFFSET_w 0x02 +#define RSTCSR_OFFSET_r 0x03 + +/* TCSR bits */ +#define TCSR_OWF bit(7) +#define TCSR_WTIT bit(6) +#define TCSR_TME bit(5) +#define TCSR_CKS_MASK bits(2,0) +#define TCSR_CKS(x) bits_val(2,0,x) +#define get_TCSR_CKS(x) bits_get(2,0,x) + +/* RSTCSR bits */ +#define RSTCSR_WOVF bit(7) +#define RSTCSR_RSTE bit(6) +#define RSTCSR_RSTS bit(5) + +#endif /* H8S2357_WDT_H */