From 080f1377473ab90ecdbf2483f5fb73f38a71c3fb Mon Sep 17 00:00:00 2001 From: Marcel Telka Date: Tue, 2 Jul 2002 18:03:25 +0000 Subject: [PATCH] Added register offsets and bits. git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@42 b68d4a1b-bc3d-0410-92ed-d4ac073336b7 --- include/arm/sa11x0/gpclk.h | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/include/arm/sa11x0/gpclk.h b/include/arm/sa11x0/gpclk.h index 4d1552b0..4012daef 100644 --- a/include/arm/sa11x0/gpclk.h +++ b/include/arm/sa11x0/gpclk.h @@ -30,14 +30,13 @@ #ifndef SA11X0_GPCLK_H #define SA11X0_GPCLK_H -#ifndef uint32_t -typedef unsigned int uint32_t; -#endif +#include /* GPCLK Registers (Serial Port 1) */ #define GPCLK_BASE 0x80020060 +#if LANGUAGE == C typedef volatile struct GPCLK_registers { uint32_t gpclkr0; uint32_t gpclkr1; @@ -54,5 +53,21 @@ typedef volatile struct GPCLK_registers { #define GPCLKR1 GPCLK_pointer->gpclkr1 #define GPCLKR2 GPCLK_pointer->gpclkr2 #define GPCLKR3 GPCLK_pointer->gpclkr3 +#endif /* LANGUAGE == C */ + +#define GPCLKR0_OFFSET 0x00 +#define GPCLKR1_OFFSET 0x04 +#define GPCLKR2_OFFSET 0x0C +#define GPCLKR3_OFFSET 0x10 + +/* GPCLKR0 bits */ + +#define GPCLKR0_SCD bit(5) +#define GPCLKR0_SCE bit(4) +#define GPCLKR0_SUS bit(0) + +/* GPCLKR1 bits */ + +#define GPCLKR1_TXE bit(1) -#endif /* SA11X0_GPCLK_H */ +#endif /* SA11X0_GPCLK_H */