From 0b8605b6ee349295d48a8c3362e36eed4e889ff6 Mon Sep 17 00:00:00 2001 From: Branislav Petrovsk Date: Fri, 27 May 2005 09:04:54 +0000 Subject: [PATCH] 2005-05-27 Branislav Petrovsky * h8/h8s2357/adc.h: New file. * h8/h8s2357/sci.h: Ditto. * h8/h8s2357/tpu.h: Ditto. * Makefile.am (nobase_openwinceinc_HEADERS): Added new files. git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@629 b68d4a1b-bc3d-0410-92ed-d4ac073336b7 --- include/ChangeLog | 7 ++ include/Makefile.am | 3 + include/NEWS | 2 + include/h8/h8s2357/adc.h | 118 ++++++++++++++++++++ include/h8/h8s2357/sci.h | 142 ++++++++++++++++++++++++ include/h8/h8s2357/tpu.h | 234 +++++++++++++++++++++++++++++++++++++++ 6 files changed, 506 insertions(+) create mode 100644 include/h8/h8s2357/adc.h create mode 100644 include/h8/h8s2357/sci.h create mode 100644 include/h8/h8s2357/tpu.h diff --git a/include/ChangeLog b/include/ChangeLog index bec5d2b5..8f4d9f0a 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,10 @@ +2005-05-27 Branislav Petrovsky + + * h8/h8s2357/adc.h: New file. + * h8/h8s2357/sci.h: Ditto. + * h8/h8s2357/tpu.h: Ditto. + * Makefile.am (nobase_openwinceinc_HEADERS): Added new files. + 2004-12-20 Marcel Telka * device/other/hd64461/afe.h: New file. diff --git a/include/Makefile.am b/include/Makefile.am index 8481624b..ab44e052 100644 --- a/include/Makefile.am +++ b/include/Makefile.am @@ -86,6 +86,9 @@ nobase_openwinceinc_HEADERS = \ device/other/hd64461/pcc.h \ device/other/hd64461/stbsys.h \ device/other/hd64461/timer.h \ + h8/h8s2357/adc.h \ + h8/h8s2357/sci.h \ + h8/h8s2357/tpu.h \ sh/sh7750/ccn.h \ std/mic.h diff --git a/include/NEWS b/include/NEWS index 0c484e3e..b1a852f0 100644 --- a/include/NEWS +++ b/include/NEWS @@ -1,5 +1,7 @@ $Id$ + * Added Renesas H8S/2357 registers. + include-0.3.3: * Added Renesas SH7750 CCN registers. diff --git a/include/h8/h8s2357/adc.h b/include/h8/h8s2357/adc.h new file mode 100644 index 00000000..665faccf --- /dev/null +++ b/include/h8/h8s2357/adc.h @@ -0,0 +1,118 @@ +/* + * $Id$ + * + * H8S/2357 ADC Registers + * Copyright (C) 2005 Elcom s.r.o. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Written by Branislav Petrovsky , 2005. + * + * Documentation: + * [1] Renesas Technology Corp., "Hitachi 16-Bit Single-chip Microcomputer + * H8S/2357 Series, H8S/2357F-ZTAT, H8S/2398F-ZTAT Hardware Manual", + * Rev. 5.0, 11/22/02, Order Number: ADE-602-146D + * + */ + +#ifndef H8S2357_ADC_H +#define H8S2357_ADC_H + +#include + +#if LANGUAGE == C +#include +#endif + +/* ADC registers */ + +#define ADC_BASE 0xffffff90 + +#if LANGUAGE == C +typedef struct ADC_registers { + uint8_t addrah; + uint8_t addral; + uint8_t addrbh; + uint8_t addrbl; + uint8_t addrch; + uint8_t addrcl; + uint8_t addrdh; + uint8_t addrdl; + uint8_t adcsr; + uint8_t adcr; +} ADC_registers_t; + +#define ADC_pointer ((ADC_registers_t*) ADC_BASE) + +#define ADDRAH ADC_pointer->addrah +#define ADDRAL ADC_pointer->addral +#define ADDRBH ADC_pointer->addrbh +#define ADDRBL ADC_pointer->addrbl +#define ADDRCH ADC_pointer->addrch +#define ADDRCL ADC_pointer->addrcl +#define ADDRDH ADC_pointer->addrdh +#define ADDRDL ADC_pointer->addrdl +#define ADCSR ADC_pointer->adcsr +#define ADCR ADC_pointer->adcr +#endif /* LANGUAGE == C */ + +#define ADDRAH_OFFSET 0x00 +#define ADDRAL_OFFSET 0x01 +#define ADDRBH_OFFSET 0x02 +#define ADDRBL_OFFSET 0x03 +#define ADDRCH_OFFSET 0x04 +#define ADDRCL_OFFSET 0x05 +#define ADDRDH_OFFSET 0x06 +#define ADDRDL_OFFSET 0x07 +#define ADCSR_OFFSET 0x08 +#define ADCR_OFFSET 0x09 + +/* ADDR bits */ +#define ADDR_AD9 bit(7) +#define ADDR_AD8 bit(6) +#define ADDR_AD7 bit(5) +#define ADDR_AD6 bit(4) +#define ADDR_AD5 bit(3) +#define ADDR_AD4 bit(2) +#define ADDR_AD3 bit(1) +#define ADDR_AD2 bit(0) +#define ADDR_AD1 bit(7) +#define ADDR_AD0 bit(6) + +/* ADCSR bits */ +#define ADCSR_ADF bit(7) +#define ADCSR_ADIE bit(6) +#define ADCSR_ADST bit(5) +#define ADCSR_SCAN bit(4) +#define ADCSR_CKS bit(3) +#define ADCSR_CH_MASK bits(2,0) +#define ADCSR_CH(x) bits_val(2,0,x) +#define get_ADCSR_CH(x) bits_get(2,0,x) + +/* ADCR bits */ +#define ADCR_TRGS1 bit(7) +#define ADCR_TRGS0 bit(6) + +#endif /* H8S2357_ADC_H */ diff --git a/include/h8/h8s2357/sci.h b/include/h8/h8s2357/sci.h new file mode 100644 index 00000000..1e1f2fdb --- /dev/null +++ b/include/h8/h8s2357/sci.h @@ -0,0 +1,142 @@ +/* + * $Id$ + * + * H8S/2357 SCI Registers + * Copyright (C) 2005 Elcom s.r.o. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Written by Branislav Petrovsky , 2005. + * + * Documentation: + * [1] Renesas Technology Corp., "Hitachi 16-Bit Single-chip Microcomputer + * H8S/2357 Series, H8S/2357F-ZTAT, H8S/2398F-ZTAT Hardware Manual", + * Rev. 5.0, 11/22/02, Order Number: ADE-602-146D + * + */ + +#ifndef H8S2357_SCI_H +#define H8S2357_SCI_H + +#include + +#if LANGUAGE == C +#include +#endif + +/* SCI registers */ + +#define SCI0_BASE 0xffffff78 +#define SCI1_BASE 0xffffff80 +#define SCI2_BASE 0xffffff88 + +#if LANGUAGE == C +typedef struct SCI_registers { + uint8_t smr; + uint8_t brr; + uint8_t scr; + uint8_t tdr; + uint8_t ssr; + uint8_t rdr; + uint8_t scmr; +} SCI_registers_t; + +#define SCI0_pointer ((SCI_registers_t*) SCI0_BASE) +#define SCI1_pointer ((SCI_registers_t*) SCI1_BASE) +#define SCI2_pointer ((SCI_registers_t*) SCI2_BASE) + +#define SMR0 SCI0_pointer->smr +#define BRR0 SCI0_pointer->brr +#define SCR0 SCI0_pointer->scr +#define TDR0 SCI0_pointer->tdr +#define SSR0 SCI0_pointer->ssr +#define RDR0 SCI0_pointer->rdr +#define SCMR0 SCI0_pointer->scmr + +#define SMR1 SCI1_pointer->smr +#define BRR1 SCI1_pointer->brr +#define SCR1 SCI1_pointer->scr +#define TDR1 SCI1_pointer->tdr +#define SSR1 SCI1_pointer->ssr +#define RDR1 SCI1_pointer->rdr +#define SCMR1 SCI1_pointer->scmr + +#define SMR2 SCI2_pointer->smr +#define BRR2 SCI2_pointer->brr +#define SCR2 SCI2_pointer->scr +#define TDR2 SCI2_pointer->tdr +#define SSR2 SCI2_pointer->ssr +#define RDR2 SCI2_pointer->rdr +#define SCMR2 SCI2_pointer->scmr +#endif /* LANGUAGE == C */ + +#define SMR_OFFSET 0x00 +#define BRR_OFFSET 0x01 +#define SCR_OFFSET 0x02 +#define TDR_OFFSET 0x03 +#define SSR_OFFSET 0x04 +#define RDR_OFFSET 0x05 +#define SCMR_OFFSET 0x06 + +/* SMR bits */ +#define SMR_CA bit(7) +#define SMR_GM bit(7) +#define SMR_CHR bit(6) +#define SMR_PE bit(5) +#define SMR_OE bit(4) +#define SMR_STOP bit(3) +#define SMR_MP bit(2) +#define SMR_CKS_MASK bits(1,0) +#define SMR_CKS(x) bits_val(1,0,x) +#define get_SMR_CKS(x) bits_get(1,0,x) + +/* SCR bits */ +#define SCR_TIE bit(7) +#define SCR_RIE bit(6) +#define SCR_TE bit(5) +#define SCR_RE bit(4) +#define SCR_MPIE bit(3) +#define SCR_TEIE bit(2) +#define SCR_CKE_MASK bits(1,0) +#define SCR_CKE(x) bits_val(1,0,x) +#define get_SCR_CKE(x) bits_get(1,0,x) + +/* SSR bits */ +#define SSR_TDRE bit(7) +#define SSR_RDFR bit(6) +#define SSR_ORER bit(5) +#define SSR_FER bit(4) +#define SSR_ERS bit(4) +#define SSR_PER bit(3) +#define SSR_TEND bit(2) +#define SSR_MPB bit(1) +#define SSR_MPBT bit(0) + +/* SCMR bits */ +#define SCMR_SDIR bit(3) +#define SCMR_SINV bit(2) +#define SCMR_SMIF bit(0) + +#endif /* H8S2357_SCI_H */ diff --git a/include/h8/h8s2357/tpu.h b/include/h8/h8s2357/tpu.h new file mode 100644 index 00000000..500501a3 --- /dev/null +++ b/include/h8/h8s2357/tpu.h @@ -0,0 +1,234 @@ +/* + * $Id$ + * + * H8S/2357 TPU0 to TPU5 Registers + * Copyright (C) 2005 Elcom s.r.o. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holders nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Written by Branislav Petrovsky , 2005. + * + * Documentation: + * [1] Renesas Technology Corp., "Hitachi 16-Bit Single-chip Microcomputer + * H8S/2357 Series, H8S/2357F-ZTAT, H8S/2398F-ZTAT Hardware Manual", + * Rev. 5.0, 11/22/02, Order Number: ADE-602-146D + * + */ + +#ifndef H8S2357_TPU_H +#define H8S2357_TPU_H + +#include + +#if LANGUAGE == C +#include +#endif + +/* TPU registers */ + +#define TPU0_BASE 0xffffffd0 +#define TPU1_BASE 0xffffffe0 +#define TPU2_BASE 0xfffffff0 +#define TPU3_BASE 0xfffffe80 +#define TPU4_BASE 0xfffffe90 +#define TPU5_BASE 0xfffffea0 +#define TPU_COMMON_BASE 0xffffffc0 + +#if LANGUAGE == C +typedef struct TPU_registers { + uint8_t tcr; + uint8_t tmdr; + uint8_t tiorh; /* tior in TPU1, TPU2, TPU4, TPU5 */ + uint8_t tiorl; /* only for TPU0 and TPU3 */ + uint8_t tier; + uint8_t tsr; + uint16_t tcnt; + uint16_t tgra; + uint16_t tgrb; + uint16_t tgrc; /* only for TPU0 and TPU3 */ + uint16_t tgrd; /* only for TPU0 and TPU3 */ +} TPU_registers_t; + +typedef struct TPU_common_registers { + uint8_t tstr; + uint8_t tsyr; +} TPU_common_registers_t; + +#define TPU0_pointer ((TPU_registers_t*) TPU0_BASE) +#define TPU1_pointer ((TPU_registers_t*) TPU1_BASE) +#define TPU2_pointer ((TPU_registers_t*) TPU2_BASE) +#define TPU3_pointer ((TPU_registers_t*) TPU3_BASE) +#define TPU4_pointer ((TPU_registers_t*) TPU4_BASE) +#define TPU5_pointer ((TPU_registers_t*) TPU5_BASE) +#define TPU_COMMON_pointer ((TPU_common_registers_t*) TPU_COMMON_BASE) + +#define TCR0 TPU0_pointer->tcr +#define TMDR0 TPU0_pointer->tmdr +#define TIOR0H TPU0_pointer->tiorh +#define TIOR0L TPU0_pointer->tiorl +#define TIER0 TPU0_pointer->tier +#define TSR0 TPU0_pointer->tsr +#define TCNT0 TPU0_pointer->tcnt +#define TGR0A TPU0_pointer->tgra +#define TGR0B TPU0_pointer->tgrb +#define TGR0C TPU0_pointer->tgrc +#define TGR0D TPU0_pointer->tgrd + +#define TCR1 TPU1_pointer->tcr +#define TMDR1 TPU1_pointer->tmdr +#define TIOR1 TPU1_pointer->tiorh +#define TIER1 TPU1_pointer->tier +#define TSR1 TPU1_pointer->tsr +#define TCNT1 TPU1_pointer->tcnt +#define TGR1A TPU1_pointer->tgra +#define TGR1B TPU1_pointer->tgrb + +#define TCR2 TPU2_pointer->tcr +#define TMDR2 TPU2_pointer->tmdr +#define TIOR2 TPU2_pointer->tiorh +#define TIER2 TPU2_pointer->tier +#define TSR2 TPU2_pointer->tsr +#define TCNT2 TPU2_pointer->tcnt +#define TGR2A TPU2_pointer->tgra +#define TGR2B TPU2_pointer->tgrb + +#define TCR3 TPU3_pointer->tcr +#define TMDR3 TPU3_pointer->tmdr +#define TIOR3H TPU3_pointer->tiorh +#define TIOR3L TPU3_pointer->tiorl +#define TIER3 TPU3_pointer->tier +#define TSR3 TPU3_pointer->tsr +#define TCNT3 TPU3_pointer->tcnt +#define TGR3A TPU3_pointer->tgra +#define TGR3B TPU3_pointer->tgrb +#define TGR3C TPU3_pointer->tgrc +#define TGR3D TPU3_pointer->tgrd + +#define TCR4 TPU4_pointer->tcr +#define TMDR4 TPU4_pointer->tmdr +#define TIOR4 TPU4_pointer->tiorh +#define TIER4 TPU4_pointer->tier +#define TSR4 TPU4_pointer->tsr +#define TCNT4 TPU4_pointer->tcnt +#define TGR4A TPU4_pointer->tgra +#define TGR4B TPU4_pointer->tgrb + +#define TCR5 TPU5_pointer->tcr +#define TMDR5 TPU5_pointer->tmdr +#define TIOR5 TPU5_pointer->tiorh +#define TIER5 TPU5_pointer->tier +#define TSR5 TPU5_pointer->tsr +#define TCNT5 TPU5_pointer->tcnt +#define TGR5A TPU5_pointer->tgra +#define TGR5B TPU5_pointer->tgrb + +#define TSTR TPU_COMMON_pointer->tstr +#define TSYR TPU_COMMON_pointer->tsyr +#endif /* LANGUAGE == C */ + +#define TCR_OFFSET 0x00 +#define TMDR_OFFSET 0x01 +#define TIOR_OFFSET 0x02 /* TPU1, TPU2, TPU4, TPU5 */ +#define TIORH_OFFSET 0x02 /* TPU0, TPU3 */ +#define TIORL_OFFSET 0x03 /* TPU0, TPU3 */ +#define TIER_OFFSET 0x04 +#define TSR_OFFSET 0x05 +#define TCNT_OFFSET 0x06 +#define TGRA_OFFSET 0x08 +#define TGRB_OFFSET 0x0a +#define TGRC_OFFSET 0x0c /* TPU0, TPU3 */ +#define TGRD_OFFSET 0x0e /* TPU0, TPU3 */ + +#define TSTR_OFFSET 0x00 +#define TSYR_OFFSET 0x01 + +/* TCR bits */ +#define TCR_CCLR_MASK bits(7,5) /* bit 7 used only in TPU0 and TPU3 */ +#define TCR_CCLR(x) bits_val(7,5,x) +#define get_TCR_CCLR(x) bits_get(7,5,x) +#define TCR_CKEG_MASK bits(4,3) +#define TCR_CKEG(x) bits_val(4,3,x) +#define get_TCR_CKEG(x) bits_get(4,3,x) +#define TCR_TPSC_MASK bits(2,0) +#define TCR_TPSC(x) bits_val(2,0,x) +#define get_TCR_TPSC(x) bits_get(2,0,x) + +/* TMDR bits */ +#define TMDR_BFB bit(5) /* only for TPU0 and TPU3 */ +#define TMDR_BFA bit(4) /* only for TPU0 and TPU3 */ +#define TMDR_MD_MASK bits(3,0) +#define TMDR_MD(x) bits_val(3,0,x) +#define get_TMDR_MD(x) bits_get(3,0,x) + +/* TIOR bits (TPU1, TPU2, TPU4, TPU5) */ +#define TIOR_IOB_MASK bits(7,4) +#define TIOR_IOB(x) bits_val(7,4,x) +#define get_TIOR_IOB(x) bits_get(7,4,x) +#define TIOR_IOA_MASK bits(3,0) +#define TIOR_IOA(x) bits_val(3,0,x) +#define get_TIOR_IOA(x) bits_get(3,0,x) + +/* TIORH bits (TPU0, TPU3) */ +#define TIORH_IOB_MASK bits(7,4) +#define TIORH_IOB(x) bits_val(7,4,x) +#define get_TIORH_IOB(x) bits_get(7,4,x) +#define TIORH_IOA_MASK bits(3,0) +#define TIORH_IOA(x) bits_val(3,0,x) +#define get_TIORH_IOA(x) bits_get(3,0,x) + +/* TIORL bits (TPU0, TPU3) */ +#define TIORL_IOD_MASK bits(7,4) +#define TIORL_IOD(x) bits_val(7,4,x) +#define get_TIORL_IOD(x) bits_get(7,4,x) +#define TIORL_IOC_MASK bits(3,0) +#define TIORL_IOC(x) bits_val(3,0,x) +#define get_TIORL_IOC(x) bits_get(3,0,x) + +/* TSR bits */ +#define TSR_TCFD bit(7) /* only for TPU1, TPU2, TPU4, TPU5 */ +#define TSR_TCFU bit(5) /* only for TPU1, TPU2, TPU4, TPU5 */ +#define TSR_TCFV bit(4) +#define TSR_TGFD bit(3) /* only for TPU0 and TPU3 */ +#define TSR_TGFC bit(2) /* only for TPU0 and TPU3 */ +#define TSR_TGFB bit(1) +#define TSR_TGFA bit(0) + +/* TSTR bits */ +#define TSTR_CST5 bit(5) +#define TSTR_CST4 bit(4) +#define TSTR_CST3 bit(3) +#define TSTR_CST2 bit(2) +#define TSTR_CST1 bit(1) +#define TSTR_CST0 bit(0) + +/* TSYR bits */ +#define TSYR_SYNC5 bit(5) +#define TSYR_SYNC4 bit(4) +#define TSYR_SYNC3 bit(3) +#define TSYR_SYNC2 bit(2) +#define TSYR_SYNC1 bit(1) +#define TSYR_SYNC0 bit(0) + +#endif /* H8S2357_TPU_H */