Added file missing in previous commit for EJTAG_DMA driver
git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@1398 b68d4a1b-bc3d-0410-92ed-d4ac073336b7master
Kolja Waschk
16 years ago
parent
802df5f8f7
commit
11333c16e2
@ -0,0 +1,595 @@
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/*
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* $Id$
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*
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* EJTAG compatible bus driver via DMA
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* Copyright (C) 2008, Julien Aube
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* Credits goes to
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* - Marek Michalkiewicz (EJTAG Pracc driver),
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* - HairyDairyMaid for the HairyDairyMaid v48 utility,
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* - Florian Fanelli for the help on the flash interface infos,
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* - All others who contributed to the previous projetcs
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
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* 02111-1307, USA.
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*
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* Written by Marek Michalkiewicz <marekm@amelek.gda.pl>, 2005.
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*
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* Documentation:
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* [1] MIPS Licensees, "MIPS EJTAG Debug Solution", 980818 Rev. 2.0.0
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* [2] MIPS Technologies, Inc. "EJTAG Specification", 2001-02-15, Rev. 2.60
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*
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*
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*/
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//#define PRINT_DATA_DEBUG 1
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#include "sysdep.h"
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include "part.h"
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#include "bus.h"
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#include "chain.h"
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#include "bssignal.h"
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#include "jtag.h"
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#include "buses.h"
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#include "generic_bus.h"
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typedef struct {
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uint32_t impcode; /* EJTAG Implementation Register */
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} bus_params_t;
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#define BP ((bus_params_t *) bus->params)
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#define EJTAG_VER ((BP->impcode >> 29) & 7)
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#define EJTAG_20 0
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#define EJTAG_25 1
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#define EJTAG_26 2
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/* EJTAG control register bits */
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#define PerRst 20
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#define PRnW 19
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#define PrAcc 18
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#define PrRst 16
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#define ProbEn 15
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#define JtagBrk 12
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#define BrkSt 3
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#define Rocc 31
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#define ProbTrap 14
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/* DMA */
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#define DmaAcc 17
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#define DstRt 11
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#define DmaRwn 9
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#define Derr 10
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// default : DMA tranfser size BYTE
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#define DMA_HALFWORD 7
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#define DMA_WORD 8
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#define DMA_BYTE 0
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/**
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* bus->driver->(*new_bus)
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*
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*/
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static bus_t *
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ejtag_dma_bus_new( chain_t *chain, const bus_driver_t *driver, char *cmd_params[] )
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{
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bus_t *bus;
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bus = calloc( 1, sizeof (bus_t) );
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if (!bus)
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return NULL;
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bus->driver = driver;
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bus->params = calloc( 1, sizeof (bus_params_t) );
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if (!bus->params) {
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free( bus );
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return NULL;
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}
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CHAIN = chain;
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PART = chain->parts->parts[chain->active_part];
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return bus;
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}
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/**
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* bus->driver->(*printinfo)
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*
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*/
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static void
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ejtag_dma_bus_printinfo( bus_t *bus )
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{
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int i;
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for (i = 0; i < CHAIN->parts->len; i++)
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if (PART == CHAIN->parts->parts[i])
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break;
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printf( _("EJTAG compatible bus driver via DMA (JTAG part No. %d)\n"), i );
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}
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/**
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* helper function
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*
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*/
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static uint32_t
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reg_value( tap_register *reg )
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{
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uint32_t retval = 0;
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int i;
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for (i = 0; i < reg->len; i++) {
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if (reg->data[i])
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retval |= (1 << i);
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}
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return retval;
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}
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#ifdef PRINT_DATA_DEBUG
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/* Small debug helper */
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char siz_(int sz)
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{
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switch(sz) {
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case DMA_WORD: return 'w';
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case DMA_BYTE: return 'b';
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case DMA_HALFWORD: return 'h';
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default : return 'e';
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}
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return 'E';
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}
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#endif
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/**
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* low-level dma write
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*
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*/
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static void ejtag_dma_write(unsigned int addr, unsigned int data,int sz)
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{
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static data_register *ejctrl = NULL;
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static data_register *ejaddr = NULL;
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static data_register *ejdata = NULL;
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int i=0;
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int timeout=5;
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if (ejctrl == NULL)
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ejctrl = part_find_data_register( PART, "EJCONTROL" );
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if (ejaddr == NULL)
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ejaddr = part_find_data_register( PART, "EJADDRESS" );
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if (ejdata == NULL)
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ejdata = part_find_data_register( PART, "EJDATA" );
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switch (sz) { /* Fill the other bytes with copy of the current */
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case DMA_BYTE:
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data &= 0xff; data |= (data<<8) | (data << 16) | (data << 24);
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break;
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case DMA_HALFWORD:
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data &= 0xffff; data |= (data << 16);
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break;
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default: break;
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}
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part_set_instruction( PART, "EJTAG_ADDRESS" );
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chain_shift_instructions( CHAIN );
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for (i = 0; i < 32; i++)
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ejaddr->in->data[i] = (addr >> i) & 1;
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chain_shift_data_registers( CHAIN, 0 ); /* Push the address to write */
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#ifdef PRINT_DATA_DEBUG
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printf("Wrote to ejaddr->in =%s %08X\n",register_get_string( ejaddr->in),reg_value( ejaddr->in ) );
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#endif
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part_set_instruction( PART, "EJTAG_DATA" );
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chain_shift_instructions( CHAIN );
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for (i = 0; i < 32; i++)
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ejdata->in->data[i] = (data >> i) & 1;
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chain_shift_data_registers( CHAIN, 0 ); /* Push the data to write */
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#ifdef PRINT_DATA_DEBUG
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printf("Wrote to edata->in(%c) =%s %08X\n",siz_(sz),register_get_string( ejdata->in),reg_value( ejdata->in ) );
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#endif
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part_set_instruction( PART, "EJTAG_CONTROL" );
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chain_shift_instructions( CHAIN );
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register_fill( ejctrl->in, 0 );
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ejctrl->in->data[PrAcc] = 1; // Processor access
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ejctrl->in->data[ProbEn] = 1;
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ejctrl->in->data[DmaAcc] = 1; // DMA operation request */
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ejctrl->in->data[DstRt] = 1;
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if (sz)
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ejctrl->in->data[sz] = 1; // Size : can be WORD/HALFWORD or nothing for byte
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chain_shift_data_registers( CHAIN, 0 ); /* Do the operation */
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//printf("Wrote to ejctrl->in =%s %08X\n",register_get_string( ejctrl->in),reg_value( ejctrl->in ) );
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do {
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part_set_instruction( PART, "EJTAG_CONTROL" );
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chain_shift_instructions( CHAIN );
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register_fill( ejctrl->in, 0 );
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ejctrl->in->data[PrAcc] = 1;
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ejctrl->in->data[ProbEn] = 1;
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ejctrl->in->data[DmaAcc] = 1;
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chain_shift_data_registers( CHAIN, 1 );
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timeout--;
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if ( ! timeout)
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break;
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} while(ejctrl->out->data[DstRt] == 1); // This flag tell us the processor has completed the op
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part_set_instruction( PART, "EJTAG_CONTROL" );
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chain_shift_instructions( CHAIN );
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register_fill( ejctrl->in, 0 );
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ejctrl->in->data[PrAcc] = 1;
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ejctrl->in->data[ProbEn] = 1;
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chain_shift_data_registers( CHAIN, 1 ); // Disable DMA, reset state to previous one.
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if (ejctrl->out->data[Derr] == 1) { // Check for DMA error, i.e. incorrect address
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printf( _("%s(%d) Error on dma write (dma transaction failed)\n"),
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__FILE__, __LINE__ );
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}
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return ;
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}
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/**
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* low level dma read operation
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*
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*/
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static unsigned int ejtag_dma_read(unsigned int addr,int sz)
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{
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static data_register *ejctrl = NULL;
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static data_register *ejaddr = NULL;
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static data_register *ejdata = NULL;
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int i=0;
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int timeout=5;
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unsigned int ret;
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if (ejctrl == NULL)
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ejctrl = part_find_data_register( PART, "EJCONTROL" );
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if (ejaddr == NULL)
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ejaddr = part_find_data_register( PART, "EJADDRESS" );
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if (ejdata == NULL)
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ejdata = part_find_data_register( PART, "EJDATA" );
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part_set_instruction( PART, "EJTAG_ADDRESS" );
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chain_shift_instructions( CHAIN );
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for (i = 0; i < 32; i++)
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ejaddr->in->data[i] = (addr >> i) & 1;
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chain_shift_data_registers( CHAIN, 0 ); /* Push the address to read */
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#ifdef PRINT_DATA_DEBUG
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printf("Wrote to ejaddr->in =%s %08X\n",register_get_string( ejaddr->in),reg_value( ejaddr->in ) );
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#endif
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part_set_instruction( PART, "EJTAG_CONTROL" );
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chain_shift_instructions( CHAIN );
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register_fill( ejctrl->in, 0 );
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ejctrl->in->data[PrAcc] = 1; // Processor access
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ejctrl->in->data[ProbEn] = 1;
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ejctrl->in->data[DmaAcc] = 1; // DMA operation request */
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ejctrl->in->data[DstRt] = 1;
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if (sz)
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ejctrl->in->data[sz] = 1; // Size : can be WORD/HALFWORD or nothing for byte
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ejctrl->in->data[DmaRwn] = 1; // This is a read
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chain_shift_data_registers( CHAIN, 0 ); /* Do the operation */
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//printf("Wrote to ejctrl->in =%s %08X\n",register_get_string( ejctrl->in),reg_value( ejctrl->in ) );
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do {
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part_set_instruction( PART, "EJTAG_CONTROL" );
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chain_shift_instructions( CHAIN );
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register_fill( ejctrl->in, 0 );
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ejctrl->in->data[PrAcc] = 1;
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ejctrl->in->data[ProbEn] = 1;
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ejctrl->in->data[DmaAcc] = 1;
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chain_shift_data_registers( CHAIN, 1 );
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//printf("Wrote to ejctrl->in =%s %08X\n",register_get_string( ejctrl->in),reg_value( ejctrl->in ) );
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//printf("Read from ejctrl->out =%s %08X\n",register_get_string( ejctrl->out),reg_value( ejctrl->out ) );
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timeout--;
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if ( ! timeout)
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break;
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} while(ejctrl->out->data[DstRt] == 1); // This flag tell us the processor has completed the op
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part_set_instruction( PART, "EJTAG_DATA" );
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chain_shift_instructions( CHAIN );
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register_fill( ejdata->in,0);
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chain_shift_data_registers( CHAIN, 1 );
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ret = reg_value(ejdata->out);
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#ifdef PRINT_DATA_DEBUG
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printf("Read from ejdata->out(%c) =%s %08X\n",siz_(sz),register_get_string( ejdata->out),reg_value( ejdata->out ) );
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#endif
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part_set_instruction( PART, "EJTAG_CONTROL" );
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chain_shift_instructions( CHAIN );
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register_fill( ejctrl->in, 0 );
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ejctrl->in->data[PrAcc] = 1;
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ejctrl->in->data[ProbEn] = 1;
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chain_shift_data_registers( CHAIN, 1 ); // Disable DMA, reset state to previous one.
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// printf("Wrote to ejctrl->in =%s %08X\n",register_get_string( ejctrl->in),reg_value( ejctrl->in ) );
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// printf("Read from ejctrl->out =%s %08X\n",register_get_string( ejctrl->out),reg_value( ejctrl->out ) );
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if (ejctrl->out->data[Derr] == 1) { // Check for DMA error, i.e. incorrect address
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printf( _("%s(%d) Error on dma read (dma transaction failed)\n"),
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__FILE__, __LINE__ );
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}
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switch (sz) {
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case DMA_HALFWORD : ret &= ret & 0xffff; break;
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case DMA_BYTE : ret &= ret & 0xff; break;
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case DMA_WORD:
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default: break;
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}
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return ret;
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}
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/**
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* bus->driver->(*initbus)
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*
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*/
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int ejtag_dma_bus_init( bus_t *bus )
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{
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data_register *ejctrl=NULL, *ejimpl=NULL, *ejaddr=NULL, *ejdata=NULL;
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int timeout=100;
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ejctrl = part_find_data_register( PART, "EJCONTROL" );
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ejimpl = part_find_data_register( PART, "EJIMPCODE" );
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ejaddr = part_find_data_register( PART, "EJADDRESS" );
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ejdata = part_find_data_register( PART, "EJDATA" );
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if (!(ejctrl && ejimpl)) {
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printf( _("%s(%d) EJCONTROL or EJIMPCODE register not found\n"),
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__FILE__, __LINE__ );
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return URJTAG_STATUS_FAIL;
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}
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if (!(ejaddr && ejdata)) {
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printf( _("%s(%d) EJADDRESS of EJDATA register not found, DMA impossible\n"),
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__FILE__, __LINE__ );
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return URJTAG_STATUS_FAIL;
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}
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part_set_instruction( PART, "EJTAG_IMPCODE" );
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chain_shift_instructions( CHAIN );
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chain_shift_data_registers( CHAIN, 0 );
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chain_shift_data_registers( CHAIN, 1 );
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printf( "ImpCode=%s\n", register_get_string( ejimpl->out ) );
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BP->impcode = reg_value( ejimpl->out );
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switch (EJTAG_VER) {
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case EJTAG_20: printf( "EJTAG version: <= 2.0\n"); break;
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case EJTAG_25: printf( "EJTAG version: 2.5\n"); break;
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case EJTAG_26: printf( "EJTAG version: 2.6\n"); break;
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default:
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printf( "EJTAG version: unknown (%d)\n", EJTAG_VER );
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}
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printf( "EJTAG Implementation flags:%s%s%s%s%s%s%s\n",
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(BP->impcode & (1 << 28)) ? " R3k" : " R4k",
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(BP->impcode & (1 << 24)) ? " DINTsup" : "",
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(BP->impcode & (1 << 22)) ? " ASID_8" : "",
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(BP->impcode & (1 << 21)) ? " ASID_6" : "",
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(BP->impcode & (1 << 16)) ? " MIPS16" : "",
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(BP->impcode & (1 << 14)) ? " NoDMA" : " DMA",
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(BP->impcode & (1 )) ? " MIPS64" : " MIPS32" );
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if (BP->impcode & (1 << 14)) {
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printf( "Warning, plateform claim there are no DMA support\n");
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}
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if (EJTAG_VER != EJTAG_20) {
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printf( "Warning, plateform has a version which is not supposed to have DMA\n");
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}
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// The purpose of this is to make the processor break into debug mode on
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// reset rather than execute the reset vector
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part_set_instruction( PART, "EJTAGBOOT" );
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chain_shift_instructions( CHAIN );
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// Prepare for following instructions
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part_set_instruction( PART, "EJTAG_CONTROL" );
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chain_shift_instructions( CHAIN );
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register_fill( ejctrl->in, 0 );
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// Reset the processor
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ejctrl->in->data[PrRst] = 1;
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ejctrl->in->data[PerRst] = 1;
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chain_shift_data_registers( CHAIN, 0 );
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// Release reset
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ejctrl->in->data[PrRst] = 0;
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ejctrl->in->data[PerRst] = 0;
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chain_shift_data_registers( CHAIN, 0 );
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ejctrl->in->data[PrAcc] = 1;
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ejctrl->in->data[ProbEn] = 1;
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ejctrl->in->data[ProbTrap] = 1;
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ejctrl->in->data[JtagBrk] = 1;
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ejctrl->in->data[Rocc] = 1;
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chain_shift_data_registers( CHAIN, 0 );
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/* Wait until processor is in break */
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ejctrl->in->data[JtagBrk] = 0;
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do {
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chain_shift_data_registers( CHAIN, 1 );
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timeout--;
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if (!timeout) break;
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} while ( ejctrl->out->data[BrkSt] == 1 );
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if (timeout == 0)
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{
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printf( _("%s(%d) Failed to enter debug mode, ctrl=%s\n"),
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__FILE__, __LINE__,
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register_get_string( ejctrl->out ) );
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return URJTAG_STATUS_FAIL;
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}
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// Handle the reset bit clear, if any
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if (ejctrl->out->data[Rocc]) {
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ejctrl->in->data[Rocc] = 0;
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chain_shift_data_registers( CHAIN, 0 );
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ejctrl->in->data[Rocc] = 1;
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chain_shift_data_registers( CHAIN, 1 );
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}
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// Clear Memory Protection Bit in DCR
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printf( _("Clear memory protection bit in DCR\n"));
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unsigned int val = ejtag_dma_read(0xff300000,DMA_WORD);
|
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ejtag_dma_write(0xff300000, val & ~(1<<2), DMA_WORD );
|
||||
|
||||
// Clear watchdog, if any
|
||||
printf( _("Clear Watchdog\n"));
|
||||
ejtag_dma_write(0xb8000080,0,DMA_WORD);
|
||||
|
||||
printf( _("Potential flash base address: [0x%x], [0x%x]\n"),
|
||||
ejtag_dma_read(0xfffe2000,DMA_WORD), ejtag_dma_read(0xfffe1000,DMA_WORD));
|
||||
|
||||
printf( _("Processor successfully switched in debug mode.\n"));
|
||||
|
||||
INITIALIZED = 1;
|
||||
return URJTAG_STATUS_OK;
|
||||
}
|
||||
/**
|
||||
* bus->driver->(*prepare)
|
||||
*
|
||||
*/
|
||||
void
|
||||
ejtag_dma_bus_prepare( bus_t *bus )
|
||||
{
|
||||
if (!INITIALIZED)
|
||||
bus_init( bus );
|
||||
}
|
||||
|
||||
/**
|
||||
* bus->driver->(*area)
|
||||
*
|
||||
*/
|
||||
int
|
||||
ejtag_dma_bus_area( bus_t *bus, uint32_t adr, bus_area_t *area )
|
||||
{
|
||||
|
||||
/* from MIPS.org datasheets */
|
||||
if (adr < UINT32_C(0x1E000000)) {
|
||||
area->description = "USEG : User addresses";
|
||||
area->start = UINT32_C(0x00000000);
|
||||
area->length = UINT64_C(0x1E000000);
|
||||
area->width = 32;
|
||||
} else if (adr < UINT32_C(0x20000000)) {
|
||||
area->description = "FLASH : Addresses in flash (boot=0x1FC000000)";
|
||||
area->start = UINT32_C(0x1E000000);
|
||||
area->length = UINT64_C(0x2000000);
|
||||
area->width = 16;
|
||||
} else if (adr < UINT32_C(0x80000000)) {
|
||||
area->description = "USEG : User addresses";
|
||||
area->start = UINT32_C(0x20000000);
|
||||
area->length = UINT64_C(0x60000000);
|
||||
area->width = 32;
|
||||
} else if (adr < UINT32_C(0xA0000000)) {
|
||||
area->description = "KSEG0: Kernel Unmapped Cached";
|
||||
area->start = UINT32_C(0x80000000);
|
||||
area->length = UINT64_C(0x20000000);
|
||||
area->width = 32;
|
||||
} else if (adr < UINT32_C(0xC0000000)) {
|
||||
area->description = "KSEG1: Kernel Unmapped Uncached";
|
||||
area->start = UINT32_C(0xA0000000);
|
||||
area->length = UINT64_C(0x20000000);
|
||||
area->width = 32;
|
||||
} else if (adr < UINT32_C(0xE0000000)) {
|
||||
area->description = "SSEG : Supervisor Mapped";
|
||||
area->start = UINT32_C(0xC0000000);
|
||||
area->length = UINT64_C(0x20000000);
|
||||
area->width = 32;
|
||||
} else {
|
||||
area->description = "KSEG3: Kernel Mapped";
|
||||
area->start = UINT32_C(0xE0000000);
|
||||
area->length = UINT64_C(0x20000000);
|
||||
area->width = 32;
|
||||
}
|
||||
return URJTAG_STATUS_OK;
|
||||
}
|
||||
|
||||
int get_sz(uint32_t adr)
|
||||
{
|
||||
static bus_area_t area;
|
||||
static int initialized = 0;
|
||||
|
||||
if (! initialized) {
|
||||
ejtag_dma_bus_area(NULL,adr,&area);
|
||||
initialized = 1;
|
||||
}
|
||||
switch (area.width)
|
||||
{
|
||||
case 32: return DMA_WORD;
|
||||
case 16: return DMA_HALFWORD;
|
||||
default: break;
|
||||
}
|
||||
return DMA_BYTE;
|
||||
}
|
||||
/**
|
||||
* bus->driver->(*write)
|
||||
*
|
||||
*/
|
||||
void ejtag_dma_bus_write(bus_t *bus, uint32_t adr, uint32_t data)
|
||||
{
|
||||
//printf("%s:adr=0x%x,data=0x%x\n",__FUNCTION__,adr,data);
|
||||
ejtag_dma_write(adr,data, get_sz(adr));
|
||||
}
|
||||
/**
|
||||
* bus->driver->(*read)
|
||||
*
|
||||
*/
|
||||
unsigned int ejtag_dma_bus_read(bus_t *bus, uint32_t adr)
|
||||
{
|
||||
int data = ejtag_dma_read(adr, get_sz(adr));
|
||||
//printf("%s:adr=0x%x,got=0x%x\n",__FUNCTION__,adr,data);
|
||||
return data;
|
||||
}
|
||||
|
||||
static unsigned int _data_read;
|
||||
/**
|
||||
* bus->driver->(*read_start)
|
||||
*
|
||||
*/
|
||||
void ejtag_dma_bus_read_start(bus_t *bus, uint32_t adr)
|
||||
{
|
||||
_data_read = ejtag_dma_read(adr,get_sz(adr));
|
||||
//printf("%s:adr=0x%x, got=0x%x\n",__FUNCTION__,adr,_data_read);
|
||||
return;
|
||||
}
|
||||
/**
|
||||
* bus->driver->(*read_next)
|
||||
*
|
||||
*/
|
||||
unsigned int ejtag_dma_bus_read_next(bus_t *bus, uint32_t adr)
|
||||
{
|
||||
unsigned int tmp_value = _data_read;
|
||||
_data_read = ejtag_dma_read(adr,get_sz(adr));
|
||||
//printf("%s:adr=0x%x, got=0x%x\n",__FUNCTION__,adr,_data_read);
|
||||
return tmp_value;
|
||||
}
|
||||
/**
|
||||
* bus->driver->(*read_end)
|
||||
*
|
||||
*/
|
||||
unsigned int ejtag_dma_bus_read_end(bus_t *bus)
|
||||
{
|
||||
return _data_read;
|
||||
}
|
||||
|
||||
const bus_driver_t ejtag_dma_bus = {
|
||||
"ejtag_dma",
|
||||
N_("EJTAG compatible bus driver via DMA"),
|
||||
ejtag_dma_bus_new,
|
||||
generic_bus_free,
|
||||
ejtag_dma_bus_printinfo,
|
||||
ejtag_dma_bus_prepare,
|
||||
ejtag_dma_bus_area,
|
||||
ejtag_dma_bus_read_start,
|
||||
ejtag_dma_bus_read_next,
|
||||
ejtag_dma_bus_read_end,
|
||||
ejtag_dma_bus_read,
|
||||
ejtag_dma_bus_write,
|
||||
ejtag_dma_bus_init
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue