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@ -7,12 +7,13 @@ $Id $
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This document is formatted to be readable for "asciidoc". Before you
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make any changes, please read the use guide at the asciidoc home page
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www.methods.co.nz/asciidoc and try to adapt to the style used here; e.g.
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use the single-line section header style ("== header ==").
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use the single-line section header style ("== header =="). Please do not use
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any whitespace other than SPACE (ASCII 0x20) and break lines > 79 chars.
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/////////////////////////////////////////////////////////////////////////////
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== Copyright ==
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Copyright 2007, 2008 Kolja Waschk (and the respective authors)
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Copyright 2007, 2008 Kolja Waschk and the respective authors.
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Permission is granted to copy, distribute and/or modify this document under the
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terms of the GNU Free Documentation License, Version 1.2 or any later version
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@ -24,9 +25,10 @@ the section entitled "GNU Free Documentation License".
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== General ==
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=== JTAG ===
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// Contributed by Ralf Engels
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JTAG basics can be found all over the internet. This section should go into
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some more details about working with JTAG. What hardwarde do you need, what is
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some more details about working with JTAG. What hardware do you need, what is
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the usage of JTAG, where do I get files. What file formats are available...
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==== Introduction ====
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@ -52,9 +54,9 @@ directly control the statemachine (yet).
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==== Interfaces ====
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The simplest interface that you can build is the Xilinx parallel cable (also
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called DLC5). If your device works with a 5V or 3.3V supply voltage then this
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device can even be build just with passive parts. (picture missing here)
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The simplest interface that you can build is like the Xilinx parallel cable
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(also called DLC5). If your device works with a 5V or 3.3V supply voltage then
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this device can even be build just with passive parts. (picture missing here)
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UrJTAG also supports a number of other interface adapters.
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==== Additions ====
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@ -67,26 +69,42 @@ such as OpenOCD allow you to debug ARM processors with gdb.
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==== BSDL and UrJTAG data files ====
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The bsdl file format describes the jtag interface for one IC. It is a vhdl
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The BSDL file format describes the jtag interface for one IC. It is a VHDL
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syntax with the needed information (like pin-names, register lengths and
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commands) that is usually done by the supplier. e.g. the Xilinx .bsd files are
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all included in their free web-pack.
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commands) that is usually done by the supplier. e.g. Xilinx BSDL files are
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all included in their free web-pack (using file extension ".bsd").
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Urjtag uses a different file format internally. So in order to add a new device
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UrJTAG uses a different file format internally. So in order to add a new device
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to UrJTAG you need to convert those files and produce a directory structure.
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Currently there are at least three tools available to do that. Please ask on
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the mailing list in case of problems with that. Please also send proven working
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files back to this project.
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Currently there are at least three tools available to do that; included with
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UrJTAG is "bsdl2jtag". Please ask on the mailing list in case of problems with
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that. Please also send proven working files back to this project.
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We're working on implementing native BSDL support in UrJTAG itself, so that
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BSDL files do not have to be converted into UrJTAG format anymore.
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==== SVF files ====
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The svf file format contains a number of high level commands to drive the jtag
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The SVF file format contains a number of high level commands to drive the jtag
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bus. For example you can shift the IR or DR and even check for the results.
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The Xilinxs impact tool allows you to write this file to program devices.
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SVF is documented in http://www.asset-intertech.com/support/svf.pdf
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UrJTAG features an "SVF player" that can read SVF files and perform the
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described actions on the bus.
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==== JAM/STAPL files ====
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Another format for describing actions over JTAG interfaces is STAPL, actually
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standardized as JEDEC "JESD-71A". Compared to SVF, it looks more like an
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actual programming language and features looping, conditional execution, and
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more. STAPL is not yet supported by UrJTAG.
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//------------------------------------------------------------------------
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=== UrJTAG ===
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// Written by K.Waschk
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==== Introduction ====
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@ -106,6 +124,12 @@ WARNING: This software may damage your hardware!
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Feedback and contributions are welcome.
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==== About this document ====
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This documentation is far from being complete. You're encouraged to amend and
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supplement it and submit your changes in the Bugs or Enhancements tracker
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at the UrJTAG website.
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==== UrJTAG Website ====
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The most current version of this documentation and UrJTAG sourcecode
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@ -113,7 +137,7 @@ is always available from the project homepage at http://www.urjtag.org
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==== The name "UrJTAG" ====
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I (Kolja) favour short names, so I thought about adding only a few
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I (Kolja) favour short names, so I thought about adding only a few
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letters to "JTAG". The prefix "Ur" in German means "ancestral", an "Ur-Vater"
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is a forefather. UrJTAG shall become the forefather, the prototype for many
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other JTAG tools. By mere chance the "Ur" is also another name for an aurochs,
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@ -168,14 +192,18 @@ See 'help cable' command for up-to-date info.
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* Arcom JTAG Cable
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* Altera ByteBlaster/ByteBlaster II/ByteBlasterMV Parallel Port Download Cable
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* Altera USB-Blaster and compatible http://www.ixo.de/info/usb_jtag
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* Xilinx DLC5 JTAG Parallel Cable III
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* ETC EA253 JTAG Cable
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* ETC EI012 JTAG Cable
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* Ka-Ro TRITON (PXA255/250) JTAG Cable
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* Keith & Koep JTAG Cable
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* Lattice Parallel Port JTAG Cable
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* Mpcbdm JTAG Cable
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* Ka-Ro TRITON (PXA255/250) JTAG Cable
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* Macraigor Wiggler JTAG Cable
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* Olimex FT2232-based ARM-USB-JTAG
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* Other FT2232-based USB JTAG cables (experimental)
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* Xilinx Platform USB Cable (experimental)
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==== JTAG-aware parts (chips) ====
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@ -287,7 +315,8 @@ If you want to try the very newest version of UrJTAG...
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svn co http://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk urjtag
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cd urjtag/jtag ./autogen.sh
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cd urjtag/jtag
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./autogen.sh
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# ./configure done by autogen.sh; run it here with special options if needed
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make
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make install
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@ -299,7 +328,7 @@ If you want to try the very newest version of UrJTAG...
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== Usage ==
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=== Quick start ===
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//Contributed by Ralf Engels
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// Contributed by Ralf Engels
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==== Run the software ====
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@ -418,6 +447,7 @@ or:
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//------------------------------------------------------------------------
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=== JTAG commands ===
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// Various authors...
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==== Overview ====
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@ -599,30 +629,29 @@ be added soon...
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svf/
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==== Data file format ====
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//By Marcel Telka
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// By Marcel Telka
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JTAG declarations files are located in directory <filename>data</filename>. The
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files contains common part specific JTAG information in parseable form, e.g.
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list of the JTAG commands, boundary scan register, list of JTAG registers, etc.
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JTAG declarations files are located in directory "data". The files contains
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common part specific JTAG information in parseable form, e.g. list of the JTAG
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commands, boundary scan register, list of JTAG registers, etc.
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Syntax of the JTAG declaration file is defined in the following subsections.
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===== General rules =====
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<para>
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JTAG declaration file is text file which consists of lines. Empty lines are
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ignored. Text after first <constant>#</constant> on the line to the end of line
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is ignored. This is useful for comments. All other lines are significant.
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ignored. Text after first "#" on the line to the end of line is ignored. This
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is useful for comments. All other lines are significant.
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Each significant line consists of tokens separated by whitespace. Whitespace
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could be spaces and/or tabs.
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===== Signal Definition =====
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Signal definition line consists of word <constant>signal</constant> followed by
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whitespace and signal name (without spaces in the name). Rest of the line
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should contain whitespace separated list of pins of the part. This list is
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currently not used for any purpose in JTAG Tools. It is intended for future
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use.
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Signal definition line consists of word "signal" followed by whitespace and
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signal name (without spaces in the name). Rest of the line should contain
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whitespace separated list of pins of the part. This list is currently not used
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for any purpose in JTAG Tools. It is intended for future use.
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//------------------------------------------------------------------------
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