From 136f397c97f8fd30095c68042c49241955592ed2 Mon Sep 17 00:00:00 2001
From: Marcel Telka <marcel@telka.sk>
Date: Tue, 22 Oct 2002 15:24:02 +0000
Subject: [PATCH] Added MSC0/1/2 register bits.

git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@199 b68d4a1b-bc3d-0410-92ed-d4ac073336b7
---
 include/arm/pxa2x0/mc.h | 69 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/include/arm/pxa2x0/mc.h b/include/arm/pxa2x0/mc.h
index 26731a86..86cdc660 100644
--- a/include/arm/pxa2x0/mc.h
+++ b/include/arm/pxa2x0/mc.h
@@ -157,6 +157,75 @@ typedef volatile struct MC_registers {
 #define	MDREFR_DRI_MASK		bits(11,0)
 #define	MDREFR_DRI(x)		bits_val(11,0,x)
 
+/* MSC0 bits - see Table 6-21 in [1] */
+
+#define	MSC0_RBUFF1		bit(31)
+#define	MSC0_RRR1_MASK		bits(30,28)
+#define	MSC0_RRR1(x)		bits_val(30,28,x)
+#define	MSC0_RDN1_MASK		bits(27,24)
+#define	MSC0_RDN1(x)		bits_val(27,24,x)
+#define	MSC0_RDF1_MASK		bits(23,20)
+#define	MSC0_RDF1(x)		bits_val(23,20,x)
+#define	MSC0_RBW1		bit(19)
+#define	MSC0_RT1_MASK		bits(18,16)
+#define	MSC0_RT1(x)		bits_val(18,16,x)
+#define	MSC0_RBUFF0		bit(15)
+#define	MSC0_RRR0_MASK		bits(14,12)
+#define	MSC0_RRR0(x)		bits_val(14,12,x)
+#define	MSC0_RDN0_MASK		bits(11,9)
+#define	MSC0_RDN0(x)		bits_val(11,8,x)
+#define	MSC0_RDF0_MASK		bits(7,4)
+#define	MSC0_RDF0(x)		bits_val(7,4,x)
+#define	MSC0_RBW0		bit(3)
+#define	MSC0_RT0_MASK		bits(2,0)
+#define	MSC0_RT0(x)		bits_val(2,0,x)
+
+/* MSC1 bits - see Table 6-21 in [1] */
+
+#define	MSC1_RBUFF3		bit(31)
+#define	MSC1_RRR3_MASK		bits(30,28)
+#define	MSC1_RRR3(x)		bits_val(30,28,x)
+#define	MSC1_RDN3_MASK		bits(27,24)
+#define	MSC1_RDN3(x)		bits_val(27,24,x)
+#define	MSC1_RDF3_MASK		bits(23,20)
+#define	MSC1_RDF3(x)		bits_val(23,20,x)
+#define	MSC1_RBW3		bit(19)
+#define	MSC1_RT3_MASK		bits(18,16)
+#define	MSC1_RT3(x)		bits_val(18,16,x)
+#define	MSC1_RBUFF2		bit(15)
+#define	MSC1_RRR2_MASK		bits(14,12)
+#define	MSC1_RRR2(x)		bits_val(14,12,x)
+#define	MSC1_RDN2_MASK		bits(11,9)
+#define	MSC1_RDN2(x)		bits_val(11,8,x)
+#define	MSC1_RDF2_MASK		bits(7,4)
+#define	MSC1_RDF2(x)		bits_val(7,4,x)
+#define	MSC1_RBW2		bit(3)
+#define	MSC1_RT2_MASK		bits(2,0)
+#define	MSC1_RT2(x)		bits_val(2,0,x)
+
+/* MSC2 bits - see Table 6-21 in [1] */
+
+#define	MSC2_RBUFF5		bit(31)
+#define	MSC2_RRR5_MASK		bits(30,28)
+#define	MSC2_RRR5(x)		bits_val(30,28,x)
+#define	MSC2_RDN5_MASK		bits(27,24)
+#define	MSC2_RDN5(x)		bits_val(27,24,x)
+#define	MSC2_RDF5_MASK		bits(23,20)
+#define	MSC2_RDF5(x)		bits_val(23,20,x)
+#define	MSC2_RBW5		bit(19)
+#define	MSC2_RT5_MASK		bits(18,16)
+#define	MSC2_RT5(x)		bits_val(18,16,x)
+#define	MSC2_RBUFF4		bit(15)
+#define	MSC2_RRR4_MASK		bits(14,12)
+#define	MSC2_RRR4(x)		bits_val(14,12,x)
+#define	MSC2_RDN4_MASK		bits(11,9)
+#define	MSC2_RDN4(x)		bits_val(11,8,x)
+#define	MSC2_RDF4_MASK		bits(7,4)
+#define	MSC2_RDF4(x)		bits_val(7,4,x)
+#define	MSC2_RBW4		bit(3)
+#define	MSC2_RT4_MASK		bits(2,0)
+#define	MSC2_RT4(x)		bits_val(2,0,x)
+
 /* MDMRS bits - see Table 6-4 in [1] */
 
 #define	MDMRS_MDMRS2_MASK	bits(30,23)