2003-02-04 Marcel Telka <marcel@telka.sk>

* arm/pxa2x0/ac97.h: Added get_* macros for register bits. * arm/pxa2x0/cm.h: Ditto. * arm/pxa2x0/i2c.h: Ditto. * arm/pxa2x0/i2s.h: Ditto. * arm/pxa2x0/icp.h: Ditto. * arm/pxa2x0/mc.h: Ditto. * arm/pxa2x0/mmc.h: Ditto. * arm/pxa2x0/pwm.h: Ditto. * arm/pxa2x0/rtc.h: Ditto. * arm/pxa2x0/ssp.h: Ditto. * arm/pxa2x0/udc.h: Ditto. * configure.ac (AC_INIT): Changed version number to 0.2.1. (AM_INIT_AUTOMAKE): Added check-news and dist-bzip2 parameters. git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@332 b68d4a1b-bc3d-0410-92ed-d4ac073336b7
22 years ago · 173fc939cc
parent 3c3df6656b
commit 173fc939cc
15 changed files with 362 additions and 197 deletions
--- a/include/ChangeLog
+++ b/include/ChangeLog
@ -1,3 +1,19 @@
+2003-02-04  Marcel Telka  <marcel@telka.sk>
+
+	* arm/pxa2x0/ac97.h: Added get_* macros for register bits.
+	* arm/pxa2x0/cm.h: Ditto.
+	* arm/pxa2x0/i2c.h: Ditto.
+	* arm/pxa2x0/i2s.h: Ditto.
+	* arm/pxa2x0/icp.h: Ditto.
+	* arm/pxa2x0/mc.h: Ditto.
+	* arm/pxa2x0/mmc.h: Ditto.
+	* arm/pxa2x0/pwm.h: Ditto.
+	* arm/pxa2x0/rtc.h: Ditto.
+	* arm/pxa2x0/ssp.h: Ditto.
+	* arm/pxa2x0/udc.h: Ditto.
+	* configure.ac (AC_INIT): Changed version number to 0.2.1.
+	(AM_INIT_AUTOMAKE): Added check-news and dist-bzip2 parameters.
+
 2003-02-04  Marcel Telka  <marcel@telka.sk>

 	* arm/platform.h: Removed unused file.
--- a/include/NEWS
+++ b/include/NEWS
@ -5,10 +5,9 @@ $Id$
 		- added MMC commands (Juraj Fabo)
 		- added register bits for MECR, SXCNFG, SXMRS, MCMEMx, MCATTx, MCIOx, BOOT_DEF
 		- added OSMRx (x = 0 through 3) macros
-		- added get_* macros for LCD register bits
+		- added (completed) get_* macros for all register bits
 		- fixed TCR_TVBS macro declaration
 		- fixed CKEN_CKEN4 declaration
-		- added get_* macros for DMA register bits
 		- added symbolic names and offsets for DRCMR registers (suggested by Daniel
 			Samek, patch 675417)
 		- fixed typo in DCSR_BUSERRINTR macro name (patch 678112, Daniel Samek)
--- a/include/TODO
+++ b/include/TODO
@ -1,3 +1,2 @@
 $Id$

-* Change 26x to 255 in Intel PXA2x0 support.
--- a/include/arm/pxa2x0/ac97.h
+++ b/include/arm/pxa2x0/ac97.h
@ -190,13 +190,16 @@ typedef volatile struct AC97_registers {

 #define	PCDR_PCM_RDATA_MASK	bits(31,16)
 #define	PCDR_PCM_RDATA(x)	bits_val(31,16,x)
+#define	get_PCDR_PCM_RDATA(x)	bits_get(31,16,x)
 #define	PCDR_PCM_LDATA_MASK	bits(15,0)
 #define	PCDR_PCM_LDATA(x)	bits_val(15,0,x)
+#define	get_PCDR_PCM_LDATA(x)	bits_get(15,0,x)

 /* MCDR bits - see Table 13-58 in [1], Table 13-18 in [2] */

 #define	MCDR_MIC_IN_DAT_MASK	bits(15,0)
 #define	MCDR_MIC_IN_DAT(x)	bits_val(15,0,x)
+#define	get_MCDR_MIC_IN_DAT(x)	bits_get(15,0,x)

 /* MOCR bits - see Table 13-59 in [1], Table 13-19 in [2] */

@ -218,5 +221,6 @@ typedef volatile struct AC97_registers {

 #define	MODR_MODEM_DAT_MASK	bits(15,0)
 #define	MODR_MODEM_DAT(x)	bits_val(15,0,x)
+#define	get_MODR_MODEM_DAT(x)	bits_get(15,0,x)

 #endif /* PXA2X0_AC97_H */
--- a/include/arm/pxa2x0/cm.h
+++ b/include/arm/pxa2x0/cm.h
@ -79,10 +79,13 @@ typedef volatile struct CM_registers {

 #define	CCCR_N_MASK	bits(9,7)
 #define	CCCR_N(x)	bits_val(9,7,x)
+#define	get_CCCR_N(x)	bits_get(9,7,x)
 #define	CCCR_M_MASK	bits(6,5)
 #define	CCCR_M(x)	bits_val(6,5,x)
+#define	get_CCCR_M(x)	bits_get(6,5,x)
 #define	CCCR_L_MASK	bits(4,0)
 #define	CCCR_L(x)	bits_val(4,0,x)
+#define	get_CCCR_L(x)	bits_get(4,0,x)

 #define	CCCR_N_1_0	CCCR_N(0x2)
 #define	CCCR_N_1_5	CCCR_N(0x3)
--- a/include/arm/pxa2x0/i2c.h
+++ b/include/arm/pxa2x0/i2c.h
@ -91,6 +91,7 @@ typedef volatile struct I2C_registers {

 #define	IDBR_IDB_MASK	bits(7,0)
 #define	IDBR_IDB(x)	bits_val(7,0,x)
+#define	get_IDBR_IDB(x)	bits_get(7,0,x)

 /* ICR bits - see Table 9-11 in [1], Table 9-11 in [2] */

@ -129,5 +130,6 @@ typedef volatile struct I2C_registers {

 #define	ISAR_ISA_MASK	bits(6,0)
 #define	ISAR_ISA(x)	bits_val(6,0,x)
+#define	get_ISAR_ISA(x)	bits_get(6,0,x)

 #endif /* PXA2X0_I2C_H */
--- a/include/arm/pxa2x0/i2s.h
+++ b/include/arm/pxa2x0/i2s.h
@ -91,8 +91,10 @@ typedef volatile struct I2S_registers {

 #define	SACR0_RFTH_MASK		bits(15,12)
 #define	SACR0_RFTH(x)		bits_val(15,12,x)
+#define	get_SACR0_RFTH(x)	bits_get(15,12,x)
 #define	SACR0_TFTH_MASK		bits(11,8)
 #define	SACR0_TFTH(x)		bits_val(11,8,x)
+#define	get_SACR0_TFTH(x)	bits_get(11,8,x)
 #define	SACR0_STRF		bit(5)
 #define	SACR0_EFWR		bit(4)
 #define	SACR0_RST		bit(3)
@ -110,8 +112,10 @@ typedef volatile struct I2S_registers {

 #define	SASR0_RFL_MASK		bits(15,12)
 #define	SASR0_RFL(x)		bits_val(15,12,x)
+#define	get_SASR0_RFL(x)	bits_get(15,12,x)
 #define	SASR0_TFL_MASK		bits(11,8)
 #define	SASR0_TFL(x)		bits_val(11,8,x)
+#define	get_SASR0_TFL(x)	bits_get(11,8,x)
 #define	SASR0_ROR		bit(6)
 #define	SASR0_TUR		bit(5)
 #define	SASR0_RFS		bit(4)
@ -136,12 +140,15 @@ typedef volatile struct I2S_registers {

 #define	SADIV_SADIV_MASK	bits(6,0)
 #define	SADIV_SADIV(x)		bits_val(6,0,x)
+#define	get_SADIV_SADIV(x)	bits_get(6,0,x)

 /* SADR bits - see Table 14-11 in [1], Table 14-11 in [2] */

 #define	SADR_DTH_MASK		bits(31,16)
 #define	SADR_DTH(x)		bits_val(31,16,x)
+#define	get_SADR_DTH(x)		bits_get(31,16,x)
 #define	SADR_DTL_MASK		bits(15,0)
 #define	SADR_DTL(x)		bits_val(15,0,x)
+#define	get_SADR_DTL(x)		bits_get(15,0,x)

 #endif /* PXA2X0_I2S_H */
--- a/include/arm/pxa2x0/icp.h
+++ b/include/arm/pxa2x0/icp.h
@ -94,20 +94,23 @@ typedef volatile struct ICP_registers {

 /* ICCR1 bits - see Table 11-3 in [1], Table 11-3 in [2] */

-#define	ICCR1_AMV_MASK	bits(7,0)
-#define	ICCR1_AMV(x)	bits_val(7,0,x)
+#define	ICCR1_AMV_MASK		bits(7,0)
+#define	ICCR1_AMV(x)		bits_val(7,0,x)
+#define	get_ICCR1_AMV(x)	bits_get(7,0,x)

 /* ICCR2 bits - see Table 11-4 in [1], Table 11-4 in [2] */

-#define	ICCR2_RXP	bit(3)
-#define	ICCR2_TXP	bit(2)
-#define	ICCR2_TRIG_MASK	bits(1,0)
-#define	ICCR2_TRIG(x)	bits_val(1,0,x)
+#define	ICCR2_RXP		bit(3)
+#define	ICCR2_TXP		bit(2)
+#define	ICCR2_TRIG_MASK		bits(1,0)
+#define	ICCR2_TRIG(x)		bits_val(1,0,x)
+#define	get_ICCR2_TRIG(x)	bits_get(1,0,x)

 /* ICDR bits - see Table 11-5 in [1], Table 11-5 in [2] */

-#define	ICDR_DATA_MASK	bits(7,0)
-#define	ICDR_DATA(x)	bits_val(7,0,x)
+#define	ICDR_DATA_MASK		bits(7,0)
+#define	ICDR_DATA(x)		bits_val(7,0,x)
+#define	get_ICDR_DATA(x)	bits_get(7,0,x)

 /* ICSR0 bits - see Table 11-6 in [1], Table 11-6 in [2] */

--- a/include/arm/pxa2x0/mc.h
+++ b/include/arm/pxa2x0/mc.h
@ -34,7 +34,7 @@
 * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
 *     Developer's Manual", February 2002, Order Number: 278522-001
 * [2] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
- *     Specification Update", October 2002, Order Number: 278534-009
+ *     Specification Update", January 2003, Order Number: 278534-0011
 * [3] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
 *     October 2002, Order Number: 278638-001
 *
@ -138,11 +138,14 @@ typedef volatile struct MC_registers {
 #define	MDCNFG_DLATCH2		bit(27)
 #define	MDCNFG_DTC2_MASK	bits(25,24)
 #define	MDCNFG_DTC2(x)		bits_val(25,24,x)
+#define	get_MDCNFG_DTC2(x)	bits_get(25,24,x)
 #define	MDCNFG_DNB2		bit(23)
 #define	MDCNFG_DRAC2_MASK	bits(22,21)
 #define	MDCNFG_DRAC2(x)		bits_val(22,21,x)
+#define	get_MDCNFG_DRAC2(x)	bits_get(22,21,x)
 #define	MDCNFG_DCAC2_MASK	bits(20,19)
 #define	MDCNFG_DCAC2(x)		bits_val(20,19,x)
+#define	get_MDCNFG_DCAC2(x)	bits_get(20,19,x)
 #define	MDCNFG_DWID2		bit(18)
 #define	MDCNFG_DE3		bit(17)
 #define	MDCNFG_DE2		bit(16)
@ -150,11 +153,14 @@ typedef volatile struct MC_registers {
 #define	MDCNFG_DLATCH0		bit(11)
 #define	MDCNFG_DTC0_MASK	bits(9,8)
 #define	MDCNFG_DTC0(x)		bits_val(9,8,x)
+#define	get_MDCNFG_DTC0(x)	bits_get(9,8,x)
 #define	MDCNFG_DNB0		bit(7)
 #define	MDCNFG_DRAC0_MASK	bits(6,5)
 #define	MDCNFG_DRAC0(x)		bits_val(6,5,x)
+#define	get_MDCNFG_DRAC0(x)	bits_get(6,5,x)
 #define	MDCNFG_DCAC0_MASK	bits(4,3)
 #define	MDCNFG_DCAC0(x)		bits_val(4,3,x)
+#define	get_MDCNFG_DCAC0(x)	bits_get(4,3,x)
 #define	MDCNFG_DWID0		bit(2)
 #define	MDCNFG_DE1		bit(1)
 #define	MDCNFG_DE0		bit(0)
@ -176,75 +182,100 @@ typedef volatile struct MC_registers {
 #define	MDREFR_E0PIN		bit(12)
 #define	MDREFR_DRI_MASK		bits(11,0)
 #define	MDREFR_DRI(x)		bits_val(11,0,x)
+#define	get_MDREFR_DRI(x)	bits_get(11,0,x)

 /* MSC0 bits - see Table 6-21 in [1], Table 6-25 in [3] */

 #define	MSC0_RBUFF1		bit(31)
 #define	MSC0_RRR1_MASK		bits(30,28)
 #define	MSC0_RRR1(x)		bits_val(30,28,x)
+#define	get_MSC0_RRR1(x)	bits_get(30,28,x)
 #define	MSC0_RDN1_MASK		bits(27,24)
 #define	MSC0_RDN1(x)		bits_val(27,24,x)
+#define	get_MSC0_RDN1(x)	bits_get(27,24,x)
 #define	MSC0_RDF1_MASK		bits(23,20)
 #define	MSC0_RDF1(x)		bits_val(23,20,x)
+#define	get_MSC0_RDF1(x)	bits_get(23,20,x)
 #define	MSC0_RBW1		bit(19)
 #define	MSC0_RT1_MASK		bits(18,16)
 #define	MSC0_RT1(x)		bits_val(18,16,x)
+#define	get_MSC0_RT1(x)		bits_get(18,16,x)
 #define	MSC0_RBUFF0		bit(15)
 #define	MSC0_RRR0_MASK		bits(14,12)
 #define	MSC0_RRR0(x)		bits_val(14,12,x)
+#define	get_MSC0_RRR0(x)	bits_get(14,12,x)
 #define	MSC0_RDN0_MASK		bits(11,9)
 #define	MSC0_RDN0(x)		bits_val(11,8,x)
+#define	get_MSC0_RDN0(x)	bits_get(11,8,x)
 #define	MSC0_RDF0_MASK		bits(7,4)
 #define	MSC0_RDF0(x)		bits_val(7,4,x)
+#define	get_MSC0_RDF0(x)	bits_get(7,4,x)
 #define	MSC0_RBW0		bit(3)
 #define	MSC0_RT0_MASK		bits(2,0)
 #define	MSC0_RT0(x)		bits_val(2,0,x)
+#define	get_MSC0_RT0(x)		bits_get(2,0,x)

 /* MSC1 bits - see Table 6-21 in [1], Table 6-25 in [3] */

 #define	MSC1_RBUFF3		bit(31)
 #define	MSC1_RRR3_MASK		bits(30,28)
 #define	MSC1_RRR3(x)		bits_val(30,28,x)
+#define	get_MSC1_RRR3(x)	bits_get(30,28,x)
 #define	MSC1_RDN3_MASK		bits(27,24)
 #define	MSC1_RDN3(x)		bits_val(27,24,x)
+#define	get_MSC1_RDN3(x)	bits_get(27,24,x)
 #define	MSC1_RDF3_MASK		bits(23,20)
 #define	MSC1_RDF3(x)		bits_val(23,20,x)
+#define	get_MSC1_RDF3(x)	bits_get(23,20,x)
 #define	MSC1_RBW3		bit(19)
 #define	MSC1_RT3_MASK		bits(18,16)
 #define	MSC1_RT3(x)		bits_val(18,16,x)
+#define	get_MSC1_RT3(x)		bits_get(18,16,x)
 #define	MSC1_RBUFF2		bit(15)
 #define	MSC1_RRR2_MASK		bits(14,12)
 #define	MSC1_RRR2(x)		bits_val(14,12,x)
+#define	get_MSC1_RRR2(x)	bits_get(14,12,x)
 #define	MSC1_RDN2_MASK		bits(11,9)
 #define	MSC1_RDN2(x)		bits_val(11,8,x)
+#define	get_MSC1_RDN2(x)	bits_get(11,8,x)
 #define	MSC1_RDF2_MASK		bits(7,4)
 #define	MSC1_RDF2(x)		bits_val(7,4,x)
+#define	get_MSC1_RDF2(x)	bits_get(7,4,x)
 #define	MSC1_RBW2		bit(3)
 #define	MSC1_RT2_MASK		bits(2,0)
 #define	MSC1_RT2(x)		bits_val(2,0,x)
+#define	get_MSC1_RT2(x)		bits_get(2,0,x)

 /* MSC2 bits - see Table 6-21 in [1], Table 6-25 in [3] */

 #define	MSC2_RBUFF5		bit(31)
 #define	MSC2_RRR5_MASK		bits(30,28)
 #define	MSC2_RRR5(x)		bits_val(30,28,x)
+#define	get_MSC2_RRR5(x)	bits_get(30,28,x)
 #define	MSC2_RDN5_MASK		bits(27,24)
 #define	MSC2_RDN5(x)		bits_val(27,24,x)
+#define	get_MSC2_RDN5(x)	bits_get(27,24,x)
 #define	MSC2_RDF5_MASK		bits(23,20)
 #define	MSC2_RDF5(x)		bits_val(23,20,x)
+#define	get_MSC2_RDF5(x)	bits_get(23,20,x)
 #define	MSC2_RBW5		bit(19)
 #define	MSC2_RT5_MASK		bits(18,16)
 #define	MSC2_RT5(x)		bits_val(18,16,x)
+#define	get_MSC2_RT5(x)		bits_get(18,16,x)
 #define	MSC2_RBUFF4		bit(15)
 #define	MSC2_RRR4_MASK		bits(14,12)
 #define	MSC2_RRR4(x)		bits_val(14,12,x)
+#define	get_MSC2_RRR4(x)	bits_get(14,12,x)
 #define	MSC2_RDN4_MASK		bits(11,9)
 #define	MSC2_RDN4(x)		bits_val(11,8,x)
+#define	get_MSC2_RDN4(x)	bits_get(11,8,x)
 #define	MSC2_RDF4_MASK		bits(7,4)
 #define	MSC2_RDF4(x)		bits_val(7,4,x)
+#define	get_MSC2_RDF4(x)	bits_get(7,4,x)
 #define	MSC2_RBW4		bit(3)
 #define	MSC2_RT4_MASK		bits(2,0)
 #define	MSC2_RT4(x)		bits_val(2,0,x)
+#define	get_MSC2_RT4(x)		bits_get(2,0,x)

 /* MECR bits - see Table 6-27 in [1], Table 6-31 in [3] */

@ -256,86 +287,114 @@ typedef volatile struct MC_registers {
 #define	SXCNFG_SXLATCH2		bit(30)
 #define	SXCNFG_SXTP2_MASK	bits(29,28)
 #define	SXCNFG_SXTP2(x)		bits_val(29,28,x)
+#define	get_SXCNFG_SXTP2(x)	bits_get(29,28,x)
 #define	SXCNFG_SXCA2_MASK	bits(27,26)
 #define	SXCNFG_SXCA2(x)		bits_val(27,26,x)
+#define	get_SXCNFG_SXCA2(x)	bits_get(27,26,x)
 #define	SXCNFG_SXRA2_MASK	bits(25,24)
 #define	SXCNFG_SXRA2(x)		bits_val(25,24,x)
+#define	get_SXCNFG_SXRA2(x)	bits_get(25,24,x)
 #define	SXCNFG_SXRL2_MASK	bits(23,21)
 #define	SXCNFG_SXRL2(x)		bits(23,21,x)
 #define	SXCNFG_SXCL2_MASK	bits(20,18)
 #define	SXCNFG_SXCL2(x)		bits_val(20,18,x)
+#define	get_SXCNFG_SXCL2(x)	bits_get(20,18,x)
 #define	SXCNFG_SXEN2_MASK	bits(17,16)
 #define	SXCNFG_SXEN2(x)		bits_val(17,16,x)
+#define	get_SXCNFG_SXEN2(x)	bits_get(17,16,x)
 #define	SXCNFG_SXLATCH0		bit(14)
 #define	SXCNFG_SXTP0_MASK	bits(13,12)
 #define	SXCNFG_SXTP0(x)		bits_val(13,12,x)
+#define	get_SXCNFG_SXTP0(x)	bits_get(13,12,x)
 #define	SXCNFG_SXCA0_MASK	bits(11,10)
 #define	SXCNFG_SXCA0(x)		bits_val(11,10,x)
+#define	get_SXCNFG_SXCA0(x)	bits_get(11,10,x)
 #define	SXCNFG_SXRA0_MASK	bits(9,8)
 #define	SXCNFG_SXRA0(x)		bits_val(9,8,x)
+#define	get_SXCNFG_SXRA0(x)	bits_get(9,8,x)
 #define	SXCNFG_SXRL0_MASK	bits(7,5)
 #define	SXCNFG_SXRL0(x)		bits(7,5,x)
 #define	SXCNFG_SXCL0_MASK	bits(4,2)
 #define	SXCNFG_SXCL0(x)		bits_val(4,2,x)
+#define	get_SXCNFG_SXCL0(x)	bits_get(4,2,x)
 #define	SXCNFG_SXEN0_MASK	bits(1,0)
 #define	SXCNFG_SXEN0(x)		bits_val(1,0,x)
+#define	get_SXCNFG_SXEN0(x)	bits_get(1,0,x)

 /* SXMRS bits - see Table 6-16 in [1], Table 6-17 in [3] */

 #define	SXMRS_SXMRS2_MASK	bits(30,16)
 #define	SXMRS_SXMRS2(x)		bits_val(30,16,x)
+#define	get_SXMRS_SXMRS2(x)	bits_get(30,16,x)
 #define	SXMRS_SXMRS0_MASK	bits(14,0)
 #define	SXMRS_SXMRS0(x)		bits_val(14,0,x)
+#define	get_SXMRS_SXMRS0(x)	bits_get(14,0,x)

 /* MCMEMx bits - see Table 6-23 in [1], Table 6-27 in [3] */

 #define	MCMEM_HOLD_MASK		bits(19,14)
 #define	MCMEM_HOLD(x)		bits_val(19,14,x)
+#define	get_MCMEM_HOLD(x)	bits_get(19,14,x)
 #define	MCMEM_ASST_MASK		bits(11,7)
 #define	MCMEM_ASST(x)		bits_val(11,7,x)
+#define	get_MCMEM_ASST(x)	bits_get(11,7,x)
 #define	MCMEM_SET_MASK		bits(6,0)
 #define	MCMEM_SET(x)		bits_val(6,0,x)
+#define	get_MCMEM_SET(x)	bits_get(6,0,x)

 /* MCATTx bits - see Table 6-24 in [1], Table 6-28 in [3] */

 #define	MCATT_HOLD_MASK		bits(19,14)
 #define	MCATT_HOLD(x)		bits_val(19,14,x)
+#define	get_MCATT_HOLD(x)	bits_get(19,14,x)
 #define	MCATT_ASST_MASK		bits(11,7)
 #define	MCATT_ASST(x)		bits_val(11,7,x)
+#define	get_MCATT_ASST(x)	bits_get(11,7,x)
 #define	MCATT_SET_MASK		bits(6,0)
 #define	MCATT_SET(x)		bits_val(6,0,x)
+#define	get_MCATT_SET(x)	bits_get(6,0,x)

 /* MCIOx bits - see Table 6-25 in [1], Table 6-29 in [3] */

 #define	MCIO_HOLD_MASK		bits(19,14)
 #define	MCIO_HOLD(x)		bits_val(19,14,x)
+#define	get_MCIO_HOLD(x)	bits_get(19,14,x)
 #define	MCIO_ASST_MASK		bits(11,7)
 #define	MCIO_ASST(x)		bits_val(11,7,x)
+#define	get_MCIO_ASST(x)	bits_get(11,7,x)
 #define	MCIO_SET_MASK		bits(6,0)
 #define	MCIO_SET(x)		bits_val(6,0,x)
+#define	get_MCIO_SET(x)		bits_get(6,0,x)

 /* MDMRS bits - see Table 6-4 in [1], Table 6-4 in [3] */

 #define	MDMRS_MDMRS2_MASK	bits(30,23)
 #define	MDMRS_MDMRS2(x)		bits_val(30,23,x)
+#define	get_MDMRS_MDMRS2(x)	bits_get(30,23,x)
 #define	MDMRS_MDCL2_MASK	bits(22,20)
 #define	MDMRS_MDCL2(x)		bits_val(22,20,x)
+#define	get_MDMRS_MDCL2(x)	bits_get(22,20,x)
 #define	MDMRS_MDADD2		bit(19)
 #define	MDMRS_MDBL2_MASK	bits(18,16)
 #define	MDMRS_MDBL2(x)		bits_val(18,16,x)
+#define	get_MDMRS_MDBL2(x)	bits_get(18,16,x)
 #define	MDMRS_MDMRS0_MASK	bits(14,7)
 #define	MDMRS_MDMRS0(x)		bits_val(14,7,x)
+#define	get_MDMRS_MDMRS0(x)	bits_get(14,7,x)
 #define	MDMRS_MDCL0_MASK	bits(6,4)
 #define	MDMRS_MDCL0(x)		bits_val(6,4,x)
+#define	get_MDMRS_MDCL0(x)	bits_get(6,4,x)
 #define	MDMRS_MDADD0		bit(3)
 #define	MDMRS_MDBL0_MASK	bits(2,0)
 #define	MDMRS_MDBL0(x)		bits_val(2,0,x)
+#define	get_MDMRS_MDBL0(x)	bits_get(2,0,x)

 /* BOOT_DEF bits - see Table 6-37 in [1], Table 6-40 in [3] */

 #define	BOOT_DEF_PKG_TYPE	bit(3)
 #define	BOOT_DEF_BOOT_SEL_MASK	bits(2,0)
 #define	BOOT_DEF_BOOT_SEL(x)	bits_val(2,0,x)
+#define	get_BOOT_DEF_BOOT_SEL(x)	bits_get(2,0,x)

 #if !defined(PXA2X0_NOPXA26X)
 /* MDMRSLP bits - see Table 6-5 in [3] */
@ -343,9 +402,11 @@ typedef volatile struct MC_registers {
 #define	MDMRSLP_MDLPEN2		bit(31)
 #define	MDMRSLP_MDMRSLP2_MASK	bits(30,16)
 #define	MDMRSLP_MDMRSLP2(x)	bits_val(30,16,x)
+#define	get_MDMRSLP_MDMRSLP2(x)	bits_get(30,16,x)
 #define	MDMRSLP_MDLPEN0		bit(15)
 #define	MDMRSLP_MDMRSLP0_MASK	bits(14,0)
 #define	MDMRSLP_MDMRSLP0(x)	bits_val(14,0,x)
+#define	get_MDMRSLP_MDMRSLP0(x)	bits_get(14,0,x)

 /* SA1111CR bits - see Table 6-24 in [3] */

--- a/include/arm/pxa2x0/mmc.h
+++ b/include/arm/pxa2x0/mmc.h
@ -120,6 +120,7 @@ typedef volatile struct MMC_registers {

 #define	MMC_STRPCL_STRPCL_MASK		bits(1,0)
 #define	MMC_STRPCL_STRPCL(x)		bits_val(1,0,x)
+#define	get_MMC_STRPCL_STRPCL(x)	bits_get(1,0,x)

 /* MMC_STAT bits - see Table 15-7 in [1], Table 15-7 in [2] */

@ -140,6 +141,7 @@ typedef volatile struct MMC_registers {

 #define	MMC_CLKRT_CLK_RATE_MASK		bits(2,0)
 #define	MMC_CLKRT_CLK_RATE(x)		bits_val(2,0,x)
+#define	get_MMC_CLKRT_CLK_RATE(x)	bits_get(2,0,x)

 /* MMC_SPI bits - see Table 15-9 in [1], Table 15-9 in [2] */

@ -158,26 +160,31 @@ typedef volatile struct MMC_registers {
 #define	MMC_CMDAT_DATA_EN		bit(2)
 #define	MMC_CMDAT_RESPONSE_FORMAT_MASK	bits(1,0)
 #define	MMC_CMDAT_RESPONSE_FORMAT(x)	bits_val(1,0,x)
+#define	get_MMC_CMDAT_RESPONSE_FORMAT(x)	bits_get(1,0,x)

 /* MMC_RESTO bits - see Table 15-11 in [1], Table 15-11 in [2] */

 #define	MMC_RESTO_RES_TO_MASK		bits(6,0)
 #define	MMC_RESTO_RES_TO(x)		bits_val(6,0,x)
+#define	get_MMC_RESTO_RES_TO(x)		bits_get(6,0,x)

 /* MMC_RDTO bits - see Table 15-12 in [1], Table 15-12 in [2] */

 #define	MMC_RDTO_READ_TO_MASK		bits(15,0)
 #define	MMC_RDTO_READ_TO(x)		bits_val(15,0,x)
+#define	get_MMC_RDTO_READ_TO(x)		bits_get(15,0,x)

 /* MMC_BLKLEN bits - see Table 15-13 in [1], Table 15-13 in [2] */

 #define	MMC_BLKLEN_BLK_LEN_MASK		bits(9,0)
 #define	MMC_BLKLEN_BLK_LEN(x)		bits_val(9,0,x)
+#define	get_MMC_BLKLEN_BLK_LEN(x)	bits_get(9,0,x)

 /* MMC_NOB bits - see Table 15-14 in [1], Table 15-14 in [2] */

 #define	MMC_NOB_MMC_NOB_MASK		bits(15,0)
 #define	MMC_NOB_MMC_NOB(x)		bits_val(15,0,x)
+#define	get_MMC_NOB_MMC_NOB(x)		bits_get(15,0,x)

 /* MMC_PRTBUF bits - see Table 15-15 in [1], Table 15-15 in [2] */

@ -207,6 +214,7 @@ typedef volatile struct MMC_registers {

 #define	MMC_CMD_CMD_INDEX_MASK		bits(5,0)
 #define	MMC_CMD_CMD_INDEX(x)		bits_val(5,0,x)
+#define	get_MMC_CMD_CMD_INDEX(x)	bits_get(5,0,x)

 /* MMC commands (for MMC_CMD) - see Table 15-19 in [1], Table 15-19 in [2] */

@ -252,25 +260,30 @@ typedef volatile struct MMC_registers {

 #define	MMC_ARGH_ARG_H_MASK		bits(15,0)
 #define	MMC_ARGH_ARG_H(x)		bits_val(15,0,x)
+#define	get_MMC_ARGH_ARG_H(x)		bits_get(15,0,x)

 /* MMC_ARGL bits - see Table 15-21 in [1], Table 15-21 in [2] */

 #define	MMC_ARGL_ARG_L_MASK		bits(15,0)
 #define	MMC_ARGL_ARG_L(x)		bits_val(15,0,x)
+#define	get_MMC_ARGL_ARG_L(x)		bits_get(15,0,x)

 /* MMC_RES bits - see Table 15-22 in [1], Table 15-22 in [2] */

 #define	MMC_RES_RESPONSE_DATA_MASK	bits(15,0)
 #define	MMC_RES_RESPONSE_DATA(x)	bits_val(15,0,x)
+#define	get_MMC_RES_RESPONSE_DATA(x)	bits_get(15,0,x)

 /* MMC_RXFIFO bits - see Table 15-23 in [1], Table 15-23 in [2] */

 #define	MMC_RXFIFO_READ_DATA_MASK	bits(7,0)
 #define	MMC_RXFIFO_READ_DATA(x)		bits_val(7,0,x)
+#define	get_MMC_RXFIFO_READ_DATA(x)	bits_get(7,0,x)

 /* MMC_TXFIFO bits - see Table 15-24 in [1], Table 15-24 in [2] */

 #define	MMC_TXFIFO_WRITE_DATA_MASK	bits(7,0)
 #define	MMC_TXFIFO_WRITE_DATA(x)	bits_val(7,0,x)
+#define	get_MMC_TXFIFO_WRITE_DATA(x)	bits_get(7,0,x)

 #endif /* PXA2X0_MMC_H */
--- a/include/arm/pxa2x0/pwm.h
+++ b/include/arm/pxa2x0/pwm.h
@ -83,19 +83,22 @@ typedef volatile struct PWM_registers {

 /* PWM_CTRL bits - see Table 4-49 in [1], Table 4-50 in [2] */

-#define	PWM_CTRL_PWM_SD		bit(6)
-#define	PWM_CTRL_PRESCALE_MASK	bits(5,0)
-#define	PWM_CTRL_PRESCALE(x)	bits_val(5,0,x)
+#define	PWM_CTRL_PWM_SD			bit(6)
+#define	PWM_CTRL_PRESCALE_MASK		bits(5,0)
+#define	PWM_CTRL_PRESCALE(x)		bits_val(5,0,x)
+#define	get_PWM_CTRL_PRESCALE(x)	bits_get(5,0,x)

 /* PWM_PWDUTY bits - see Table 4-50 in [1], Table 4-51 in [2] */

-#define	PWM_PWDUTY_FDCYCLE	bit(10)
-#define	PWM_PWDUTY_DCYCLE_MASK	bits(9,0)
-#define	PWM_PWDUTY_DCYCLE(x)	bits_val(9,0,x)
+#define	PWM_PWDUTY_FDCYCLE		bit(10)
+#define	PWM_PWDUTY_DCYCLE_MASK		bits(9,0)
+#define	PWM_PWDUTY_DCYCLE(x)		bits_val(9,0,x)
+#define	get_PWM_PWDUTY_DCYCLE(x)	bits_get(9,0,x)

 /* PWM_PERVAL bits - see Table 4-51 in [1], Table 4-52 in [2] */

-#define	PWM_PERVAL_PV_MASK	bits(9,0)
-#define	PWM_PERVAL_PV(x)	bits_val(9,0,x)
+#define	PWM_PERVAL_PV_MASK		bits(9,0)
+#define	PWM_PERVAL_PV(x)		bits_val(9,0,x)
+#define	get_PWM_PERVAL_PV(x)		bits_get(9,0,x)

 #endif /* PXA2X0_PWM_H */
--- a/include/arm/pxa2x0/rtc.h
+++ b/include/arm/pxa2x0/rtc.h
@ -86,7 +86,9 @@ typedef volatile struct RTC_registers {
 #define	RTTR_LCK		bit(31)
 #define	RTTR_DEL_MASK		bits(25,16)
 #define	RTTR_DEL(x)		bits_val(25,16,x)
+#define	get_RTTR_DEL(x)		bits_get(25,16,x)
 #define	RTTR_CK_DIV_MASK	bits(15,0)
 #define	RTTR_CK_DIV(x)		bits_val(15,0,x)
+#define	get_RTTR_CK_DIV(x)	bits_get(15,0,x)

 #endif /* PXA2X0_RTC_H */
--- a/include/arm/pxa2x0/ssp.h
+++ b/include/arm/pxa2x0/ssp.h
@ -155,260 +155,309 @@ typedef volatile struct SSP_registers {

 /* SSCR0 bits - see Table 8-2 in [1], Table 8-2 in [2] */

-#define	SSCR0_SCR_MASK	bits(15,8)
-#define	SSCR0_SCR(x)	bits_val(15,8,x)
-#define	SSCR0_SSE	bit(7)
-#define	SSCR0_ECS	bit(6)
-#define	SSCR0_FRF_MASK	bits(5,4)
-#define	SSCR0_FRF(x)	bits_val(5,4,x)
-#define	SSCR0_DSS_MASK	bits(3,0)
-#define	SSCR0_DSS(x)	bits_val(3,0,x)
+#define	SSCR0_SCR_MASK		bits(15,8)
+#define	SSCR0_SCR(x)		bits_val(15,8,x)
+#define	get_SSCR0_SCR(x)	bits_get(15,8,x)
+#define	SSCR0_SSE		bit(7)
+#define	SSCR0_ECS		bit(6)
+#define	SSCR0_FRF_MASK		bits(5,4)
+#define	SSCR0_FRF(x)		bits_val(5,4,x)
+#define	get_SSCR0_FRF(x)	bits_get(5,4,x)
+#define	SSCR0_DSS_MASK		bits(3,0)
+#define	SSCR0_DSS(x)		bits_val(3,0,x)
+#define	get_SSCR0_DSS(x)	bits_get(3,0,x)

 /* SSCR1 bits - see Table 8-3 in [1], Table 8-3 in [2] */

-#define	SSCR1_RFT_MASK	bits(13,10)
-#define	SSCR1_RFT(x)	bits_val(13,10,x)
-#define	SSCR1_TFT_MASK	bits(9,6)
-#define	SSCR1_TFT(x)	bits_val(9,6,x)
-#define	SSCR1_MWDS	bit(5)
-#define	SSCR1_SPH	bit(4)
-#define	SSCR1_SPO	bit(3)
-#define	SSCR1_LBM	bit(2)
-#define	SSCR1_TIE	bit(1)
-#define	SSCR1_RIE	bit(0)
+#define	SSCR1_RFT_MASK		bits(13,10)
+#define	SSCR1_RFT(x)		bits_val(13,10,x)
+#define	get_SSCR1_RFT(x)	bits_get(13,10,x)
+#define	SSCR1_TFT_MASK		bits(9,6)
+#define	SSCR1_TFT(x)		bits_val(9,6,x)
+#define	get_SSCR1_TFT(x)	bits_get(9,6,x)
+#define	SSCR1_MWDS		bit(5)
+#define	SSCR1_SPH		bit(4)
+#define	SSCR1_SPO		bit(3)
+#define	SSCR1_LBM		bit(2)
+#define	SSCR1_TIE		bit(1)
+#define	SSCR1_RIE		bit(0)

 /* SSSR bits - see Table 8-6 in [1], Table 8-6 in [2] */

-#define	SSSR_RFL_MASK	bits(15,12)
-#define	SSSR_RFL(x)	bits_val(15,12,x)
-#define	SSSR_TFL_MASK	bits(11,8)
-#define	SSSR_TFL(x)	bits_val(11,8,x)
-#define	SSSR_ROR	bit(7)
-#define	SSSR_RFS	bit(6)
-#define	SSSR_TFS	bit(5)
-#define	SSSR_BSY	bit(4)
-#define	SSSR_RNE	bit(3)
-#define	SSSR_TNF	bit(2)
+#define	SSSR_RFL_MASK		bits(15,12)
+#define	SSSR_RFL(x)		bits_val(15,12,x)
+#define	get_SSSR_RFL(x)		bits_get(15,12,x)
+#define	SSSR_TFL_MASK		bits(11,8)
+#define	SSSR_TFL(x)		bits_val(11,8,x)
+#define	get_SSSR_TFL(x)		bits_get(11,8,x)
+#define	SSSR_ROR		bit(7)
+#define	SSSR_RFS		bit(6)
+#define	SSSR_TFS		bit(5)
+#define	SSSR_BSY		bit(4)
+#define	SSSR_RNE		bit(3)
+#define	SSSR_TNF		bit(2)

 #if !defined(PXA2X0_NOPXA26X)
 /* NSSCR0/ASSCR0 bits - see Table 16-3 in [2] */

-#define	NSSCR0_EDSS	bit(20)
-#define	NSSCR0_SCR_MASK	bits(19,8)
-#define	NSSCR0_SCR(x)	bits_val(19,8,x)
-#define	NSSCR0_SSE	bit(7)
-#define	NSSCR0_FRF_MASK	bits(5,4)
-#define	NSSCR0_FRF(x)	bits_val(5,4,x)
-#define	NSSCR0_DSS_MASK	bits(3,0)
-#define	NSSCR0_DSS(x)	bits_val(3,0,x)
-
-#define	ASSCR0_EDSS	bit(20)
-#define	ASSCR0_SCR_MASK	bits(19,8)
-#define	ASSCR0_SCR(x)	bits_val(19,8,x)
-#define	ASSCR0_SSE	bit(7)
-#define	ASSCR0_FRF_MASK	bits(5,4)
-#define	ASSCR0_FRF(x)	bits_val(5,4,x)
-#define	ASSCR0_DSS_MASK	bits(3,0)
-#define	ASSCR0_DSS(x)	bits_val(3,0,x)
-
-#define	XSSCR0_EDSS	bit(20)
-#define	XSSCR0_SCR_MASK	bits(19,8)
-#define	XSSCR0_SCR(x)	bits_val(19,8,x)
-#define	XSSCR0_SSE	bit(7)
-#define	XSSCR0_FRF_MASK	bits(5,4)
-#define	XSSCR0_FRF(x)	bits_val(5,4,x)
-#define	XSSCR0_DSS_MASK	bits(3,0)
-#define	XSSCR0_DSS(x)	bits_val(3,0,x)
+#define	NSSCR0_EDSS		bit(20)
+#define	NSSCR0_SCR_MASK		bits(19,8)
+#define	NSSCR0_SCR(x)		bits_val(19,8,x)
+#define	get_NSSCR0_SCR(x)	bits_get(19,8,x)
+#define	NSSCR0_SSE		bit(7)
+#define	NSSCR0_FRF_MASK		bits(5,4)
+#define	NSSCR0_FRF(x)		bits_val(5,4,x)
+#define	get_NSSCR0_FRF(x)	bits_get(5,4,x)
+#define	NSSCR0_DSS_MASK		bits(3,0)
+#define	NSSCR0_DSS(x)		bits_val(3,0,x)
+#define	get_NSSCR0_DSS(x)	bits_get(3,0,x)
+
+#define	ASSCR0_EDSS		bit(20)
+#define	ASSCR0_SCR_MASK		bits(19,8)
+#define	ASSCR0_SCR(x)		bits_val(19,8,x)
+#define	get_ASSCR0_SCR(x)	bits_get(19,8,x)
+#define	ASSCR0_SSE		bit(7)
+#define	ASSCR0_FRF_MASK		bits(5,4)
+#define	ASSCR0_FRF(x)		bits_val(5,4,x)
+#define	get_ASSCR0_FRF(x)	bits_get(5,4,x)
+#define	ASSCR0_DSS_MASK		bits(3,0)
+#define	ASSCR0_DSS(x)		bits_val(3,0,x)
+#define	get_ASSCR0_DSS(x)	bits_get(3,0,x)
+
+#define	XSSCR0_EDSS		bit(20)
+#define	XSSCR0_SCR_MASK		bits(19,8)
+#define	XSSCR0_SCR(x)		bits_val(19,8,x)
+#define	get_XSSCR0_SCR(x)	bits_get(19,8,x)
+#define	XSSCR0_SSE		bit(7)
+#define	XSSCR0_FRF_MASK		bits(5,4)
+#define	XSSCR0_FRF(x)		bits_val(5,4,x)
+#define	get_XSSCR0_FRF(x)	bits_get(5,4,x)
+#define	XSSCR0_DSS_MASK		bits(3,0)
+#define	XSSCR0_DSS(x)		bits_val(3,0,x)
+#define	get_XSSCR0_DSS(x)	bits_get(3,0,x)

 /* NSSCR1/ASSCR1 bits - see Table 16-4 in [2] */

-#define	NSSCR1_TTELP	bit(31)
-#define	NSSCR1_TTE	bit(30)
-#define	NSSCR1_EBCEI	bit(29)
-#define	NSSCR1_SCFR	bit(28)
-#define	NSSCR1_SCLKDIR	bit(25)
-#define	NSSCR1_SFRMDIR	bit(24)
-#define	NSSCR1_RWOT	bit(23)
-#define	NSSCR1_TSRE	bit(21)
-#define	NSSCR1_RSRE	bit(20)
-#define	NSSCR1_TINTE	bit(19)
-#define	NSSCR1_STRF	bit(15)
-#define	NSSCR1_EFWR	bit(14)
-#define	NSSCR1_RFT_MASK	bits(13,10)
-#define	NSSCR1_RFT(x)	bits_val(13,10,x)
-#define	NSSCR1_TFT_MASK	bits(9,6)
-#define	NSSCR1_TFT(x)	bits_val(9,6,x)
-#define	NSSCR1_MWDS	bit(5)
-#define	NSSCR1_SPH	bit(4)
-#define	NSSCR1_SPO	bit(3)
-#define	NSSCR1_LBM	bit(2)
-#define	NSSCR1_TIE	bit(1)
-#define	NSSCR1_RIE	bit(0)
-
-#define	ASSCR1_TTELP	bit(31)
-#define	ASSCR1_TTE	bit(30)
-#define	ASSCR1_EBCEI	bit(29)
-#define	ASSCR1_SCFR	bit(28)
-#define	ASSCR1_SCLKDIR	bit(25)
-#define	ASSCR1_SFRMDIR	bit(24)
-#define	ASSCR1_RWOT	bit(23)
-#define	ASSCR1_TSRE	bit(21)
-#define	ASSCR1_RSRE	bit(20)
-#define	ASSCR1_TINTE	bit(19)
-#define	ASSCR1_STRF	bit(15)
-#define	ASSCR1_EFWR	bit(14)
-#define	ASSCR1_RFT_MASK	bits(13,10)
-#define	ASSCR1_RFT(x)	bits_val(13,10,x)
-#define	ASSCR1_TFT_MASK	bits(9,6)
-#define	ASSCR1_TFT(x)	bits_val(9,6,x)
-#define	ASSCR1_MWDS	bit(5)
-#define	ASSCR1_SPH	bit(4)
-#define	ASSCR1_SPO	bit(3)
-#define	ASSCR1_LBM	bit(2)
-#define	ASSCR1_TIE	bit(1)
-#define	ASSCR1_RIE	bit(0)
-
-#define	XSSCR1_TTELP	bit(31)
-#define	XSSCR1_TTE	bit(30)
-#define	XSSCR1_EBCEI	bit(29)
-#define	XSSCR1_SCFR	bit(28)
-#define	XSSCR1_SCLKDIR	bit(25)
-#define	XSSCR1_SFRMDIR	bit(24)
-#define	XSSCR1_RWOT	bit(23)
-#define	XSSCR1_TSRE	bit(21)
-#define	XSSCR1_RSRE	bit(20)
-#define	XSSCR1_TINTE	bit(19)
-#define	XSSCR1_STRF	bit(15)
-#define	XSSCR1_EFWR	bit(14)
-#define	XSSCR1_RFT_MASK	bits(13,10)
-#define	XSSCR1_RFT(x)	bits_val(13,10,x)
-#define	XSSCR1_TFT_MASK	bits(9,6)
-#define	XSSCR1_TFT(x)	bits_val(9,6,x)
-#define	XSSCR1_MWDS	bit(5)
-#define	XSSCR1_SPH	bit(4)
-#define	XSSCR1_SPO	bit(3)
-#define	XSSCR1_LBM	bit(2)
-#define	XSSCR1_TIE	bit(1)
-#define	XSSCR1_RIE	bit(0)
+#define	NSSCR1_TTELP		bit(31)
+#define	NSSCR1_TTE		bit(30)
+#define	NSSCR1_EBCEI		bit(29)
+#define	NSSCR1_SCFR		bit(28)
+#define	NSSCR1_SCLKDIR		bit(25)
+#define	NSSCR1_SFRMDIR		bit(24)
+#define	NSSCR1_RWOT		bit(23)
+#define	NSSCR1_TSRE		bit(21)
+#define	NSSCR1_RSRE		bit(20)
+#define	NSSCR1_TINTE		bit(19)
+#define	NSSCR1_STRF		bit(15)
+#define	NSSCR1_EFWR		bit(14)
+#define	NSSCR1_RFT_MASK		bits(13,10)
+#define	NSSCR1_RFT(x)		bits_val(13,10,x)
+#define	get_NSSCR1_RFT(x)	bits_get(13,10,x)
+#define	NSSCR1_TFT_MASK		bits(9,6)
+#define	NSSCR1_TFT(x)		bits_val(9,6,x)
+#define	get_NSSCR1_TFT(x)	bits_get(9,6,x)
+#define	NSSCR1_MWDS		bit(5)
+#define	NSSCR1_SPH		bit(4)
+#define	NSSCR1_SPO		bit(3)
+#define	NSSCR1_LBM		bit(2)
+#define	NSSCR1_TIE		bit(1)
+#define	NSSCR1_RIE		bit(0)
+
+#define	ASSCR1_TTELP		bit(31)
+#define	ASSCR1_TTE		bit(30)
+#define	ASSCR1_EBCEI		bit(29)
+#define	ASSCR1_SCFR		bit(28)
+#define	ASSCR1_SCLKDIR		bit(25)
+#define	ASSCR1_SFRMDIR		bit(24)
+#define	ASSCR1_RWOT		bit(23)
+#define	ASSCR1_TSRE		bit(21)
+#define	ASSCR1_RSRE		bit(20)
+#define	ASSCR1_TINTE		bit(19)
+#define	ASSCR1_STRF		bit(15)
+#define	ASSCR1_EFWR		bit(14)
+#define	ASSCR1_RFT_MASK		bits(13,10)
+#define	ASSCR1_RFT(x)		bits_val(13,10,x)
+#define	get_ASSCR1_RFT(x)	bits_get(13,10,x)
+#define	ASSCR1_TFT_MASK		bits(9,6)
+#define	ASSCR1_TFT(x)		bits_val(9,6,x)
+#define	get_ASSCR1_TFT(x)	bits_get(9,6,x)
+#define	ASSCR1_MWDS		bit(5)
+#define	ASSCR1_SPH		bit(4)
+#define	ASSCR1_SPO		bit(3)
+#define	ASSCR1_LBM		bit(2)
+#define	ASSCR1_TIE		bit(1)
+#define	ASSCR1_RIE		bit(0)
+
+#define	XSSCR1_TTELP		bit(31)
+#define	XSSCR1_TTE		bit(30)
+#define	XSSCR1_EBCEI		bit(29)
+#define	XSSCR1_SCFR		bit(28)
+#define	XSSCR1_SCLKDIR		bit(25)
+#define	XSSCR1_SFRMDIR		bit(24)
+#define	XSSCR1_RWOT		bit(23)
+#define	XSSCR1_TSRE		bit(21)
+#define	XSSCR1_RSRE		bit(20)
+#define	XSSCR1_TINTE		bit(19)
+#define	XSSCR1_STRF		bit(15)
+#define	XSSCR1_EFWR		bit(14)
+#define	XSSCR1_RFT_MASK		bits(13,10)
+#define	XSSCR1_RFT(x)		bits_val(13,10,x)
+#define	get_XSSCR1_RFT(x)	bits_get(13,10,x)
+#define	XSSCR1_TFT_MASK		bits(9,6)
+#define	XSSCR1_TFT(x)		bits_val(9,6,x)
+#define	get_XSSCR1_TFT(x)	bits_get(9,6,x)
+#define	XSSCR1_MWDS		bit(5)
+#define	XSSCR1_SPH		bit(4)
+#define	XSSCR1_SPO		bit(3)
+#define	XSSCR1_LBM		bit(2)
+#define	XSSCR1_TIE		bit(1)
+#define	XSSCR1_RIE		bit(0)

 /* NSSITR/ASSITR bits - see Table 16-7 in [2] */

-#define	NSSITR_TROR	bit(7)
-#define	NSSITR_TRFS	bit(6)
-#define	NSSITR_TTFS	bit(5)
+#define	NSSITR_TROR		bit(7)
+#define	NSSITR_TRFS		bit(6)
+#define	NSSITR_TTFS		bit(5)

-#define	ASSITR_TROR	bit(7)
-#define	ASSITR_TRFS	bit(6)
-#define	ASSITR_TTFS	bit(5)
+#define	ASSITR_TROR		bit(7)
+#define	ASSITR_TRFS		bit(6)
+#define	ASSITR_TTFS		bit(5)

-#define	XSSITR_TROR	bit(7)
-#define	XSSITR_TRFS	bit(6)
-#define	XSSITR_TTFS	bit(5)
+#define	XSSITR_TROR		bit(7)
+#define	XSSITR_TRFS		bit(6)
+#define	XSSITR_TTFS		bit(5)

 /* NSSSR/ASSSR bits - see Table 16-8 in [2] */

-#define	NSSSR_BCE	bit(23)
-#define	NSSSR_CSS	bit(22)
-#define	NSSSR_TUR	bit(21)
-#define	NSSSR_TINT	bit(19)
-#define	NSSSR_RFL_MASK	bits(15,12)
-#define	NSSSR_RFL(x)	bits_val(15,12,x)
-#define	NSSSR_TFL_MASK	bits(11,8)
-#define	NSSSR_TFL(x)	bits_val(11,8,x)
-#define	NSSSR_ROR	bit(7)
-#define	NSSSR_RFS	bit(6)
-#define	NSSSR_TFS	bit(5)
-#define	NSSSR_BSY	bit(4)
-#define	NSSSR_RNE	bit(3)
-#define	NSSSR_TNF	bit(2)
-
-#define	ASSSR_BCE	bit(23)
-#define	ASSSR_CSS	bit(22)
-#define	ASSSR_TUR	bit(21)
-#define	ASSSR_TINT	bit(19)
-#define	ASSSR_RFL_MASK	bits(15,12)
-#define	ASSSR_RFL(x)	bits_val(15,12,x)
-#define	ASSSR_TFL_MASK	bits(11,8)
-#define	ASSSR_TFL(x)	bits_val(11,8,x)
-#define	ASSSR_ROR	bit(7)
-#define	ASSSR_RFS	bit(6)
-#define	ASSSR_TFS	bit(5)
-#define	ASSSR_BSY	bit(4)
-#define	ASSSR_RNE	bit(3)
-#define	ASSSR_TNF	bit(2)
-
-#define	XSSSR_BCE	bit(23)
-#define	XSSSR_CSS	bit(22)
-#define	XSSSR_TUR	bit(21)
-#define	XSSSR_TINT	bit(19)
-#define	XSSSR_RFL_MASK	bits(15,12)
-#define	XSSSR_RFL(x)	bits_val(15,12,x)
-#define	XSSSR_TFL_MASK	bits(11,8)
-#define	XSSSR_TFL(x)	bits_val(11,8,x)
-#define	XSSSR_ROR	bit(7)
-#define	XSSSR_RFS	bit(6)
-#define	XSSSR_TFS	bit(5)
-#define	XSSSR_BSY	bit(4)
-#define	XSSSR_RNE	bit(3)
-#define	XSSSR_TNF	bit(2)
+#define	NSSSR_BCE		bit(23)
+#define	NSSSR_CSS		bit(22)
+#define	NSSSR_TUR		bit(21)
+#define	NSSSR_TINT		bit(19)
+#define	NSSSR_RFL_MASK		bits(15,12)
+#define	NSSSR_RFL(x)		bits_val(15,12,x)
+#define	get_NSSSR_RFL(x)	bits_get(15,12,x)
+#define	NSSSR_TFL_MASK		bits(11,8)
+#define	NSSSR_TFL(x)		bits_val(11,8,x)
+#define	get_NSSSR_TFL(x)	bits_get(11,8,x)
+#define	NSSSR_ROR		bit(7)
+#define	NSSSR_RFS		bit(6)
+#define	NSSSR_TFS		bit(5)
+#define	NSSSR_BSY		bit(4)
+#define	NSSSR_RNE		bit(3)
+#define	NSSSR_TNF		bit(2)
+
+#define	ASSSR_BCE		bit(23)
+#define	ASSSR_CSS		bit(22)
+#define	ASSSR_TUR		bit(21)
+#define	ASSSR_TINT		bit(19)
+#define	ASSSR_RFL_MASK		bits(15,12)
+#define	ASSSR_RFL(x)		bits_val(15,12,x)
+#define	get_ASSSR_RFL(x)	bits_get(15,12,x)
+#define	ASSSR_TFL_MASK		bits(11,8)
+#define	ASSSR_TFL(x)		bits_val(11,8,x)
+#define	get_ASSSR_TFL(x)	bits_get(11,8,x)
+#define	ASSSR_ROR		bit(7)
+#define	ASSSR_RFS		bit(6)
+#define	ASSSR_TFS		bit(5)
+#define	ASSSR_BSY		bit(4)
+#define	ASSSR_RNE		bit(3)
+#define	ASSSR_TNF		bit(2)
+
+#define	XSSSR_BCE		bit(23)
+#define	XSSSR_CSS		bit(22)
+#define	XSSSR_TUR		bit(21)
+#define	XSSSR_TINT		bit(19)
+#define	XSSSR_RFL_MASK		bits(15,12)
+#define	XSSSR_RFL(x)		bits_val(15,12,x)
+#define	get_XSSSR_RFL(x)	bits_get(15,12,x)
+#define	XSSSR_TFL_MASK		bits(11,8)
+#define	XSSSR_TFL(x)		bits_val(11,8,x)
+#define	get_XSSSR_TFL(x)	bits_get(11,8,x)
+#define	XSSSR_ROR		bit(7)
+#define	XSSSR_RFS		bit(6)
+#define	XSSSR_TFS		bit(5)
+#define	XSSSR_BSY		bit(4)
+#define	XSSSR_RNE		bit(3)
+#define	XSSSR_TNF		bit(2)

 /* NSSTO/ASSTO bits - see Table 16-6 in [2] */

 #define	NSSTO_TIMEOUT_MASK	bits(23,0)
 #define	NSSTO_TIMEOUT(x)	bits_val(23,0,x)
+#define	get_NSSTO_TIMEOUT(x)	bits_get(23,0,x)

 #define	ASSTO_TIMEOUT_MASK	bits(23,0)
 #define	ASSTO_TIMEOUT(x)	bits_val(23,0,x)
+#define	get_ASSTO_TIMEOUT(x)	bits_get(23,0,x)

 #define	XSSTO_TIMEOUT_MASK	bits(23,0)
 #define	XSSTO_TIMEOUT(x)	bits_val(23,0,x)
+#define	get_XSSTO_TIMEOUT(x)	bits_get(23,0,x)

 /* NSSPSP/ASSPSP bits - see Table 16-5 in [2] */

 #define	NSSPSP_DMYSTOP_MASK	bits(24,23)
 #define	NSSPSP_DMYSTOP(x)	bits_val(24,23,x)
+#define	get_NSSPSP_DMYSTOP(x)	bits_get(24,23,x)
 #define	NSSPSP_SFRMWDTH_MASK	bits(21,16)
 #define	NSSPSP_SFRMWDTH(x)	bits_val(21,16,x)
+#define	get_NSSPSP_SFRMWDTH(x)	bits_get(21,16,x)
 #define	NSSPSP_SFRMDLY_MASK	bits(15,9)
 #define	NSSPSP_SFRMDLY(x)	bits_val(15,9,x)
+#define	get_NSSPSP_SFRMDLY(x)	bits_get(15,9,x)
 #define	NSSPSP_DMYSTRT_MASK	bits(8,7)
 #define	NSSPSP_DMYSTRT(x)	bits_val(8,7,x)
+#define	get_NSSPSP_DMYSTRT(x)	bits_get(8,7,x)
 #define	NSSPSP_STRTDLY_MASK	bits(6,4)
 #define	NSSPSP_STRTDLY(x)	bits_val(6,4,x)
+#define	get_NSSPSP_STRTDLY(x)	bits_get(6,4,x)
 #define	NSSPSP_ETDS		bit(3)
 #define	NSSPSP_SFRMP		bit(2)
 #define	NSSPSP_SCMODE_MASK	bits(1,0)
 #define	NSSPSP_SCMODE(x)	bits_val(1,0,x)
+#define	get_NSSPSP_SCMODE(x)	bits_get(1,0,x)

 #define	ASSPSP_DMYSTOP_MASK	bits(24,23)
 #define	ASSPSP_DMYSTOP(x)	bits_val(24,23,x)
+#define	get_ASSPSP_DMYSTOP(x)	bits_get(24,23,x)
 #define	ASSPSP_SFRMWDTH_MASK	bits(21,16)
 #define	ASSPSP_SFRMWDTH(x)	bits_val(21,16,x)
+#define	get_ASSPSP_SFRMWDTH(x)	bits_get(21,16,x)
 #define	ASSPSP_SFRMDLY_MASK	bits(15,9)
 #define	ASSPSP_SFRMDLY(x)	bits_val(15,9,x)
+#define	get_ASSPSP_SFRMDLY(x)	bits_get(15,9,x)
 #define	ASSPSP_DMYSTRT_MASK	bits(8,7)
 #define	ASSPSP_DMYSTRT(x)	bits_val(8,7,x)
+#define	get_ASSPSP_DMYSTRT(x)	bits_get(8,7,x)
 #define	ASSPSP_STRTDLY_MASK	bits(6,4)
 #define	ASSPSP_STRTDLY(x)	bits_val(6,4,x)
+#define	get_ASSPSP_STRTDLY(x)	bits_get(6,4,x)
 #define	ASSPSP_ETDS		bit(3)
 #define	ASSPSP_SFRMP		bit(2)
 #define	ASSPSP_SCMODE_MASK	bits(1,0)
 #define	ASSPSP_SCMODE(x)	bits_val(1,0,x)
+#define	get_ASSPSP_SCMODE(x)	bits_get(1,0,x)

 #define	XSSPSP_DMYSTOP_MASK	bits(24,23)
 #define	XSSPSP_DMYSTOP(x)	bits_val(24,23,x)
+#define	get_XSSPSP_DMYSTOP(x)	bits_get(24,23,x)
 #define	XSSPSP_SFRMWDTH_MASK	bits(21,16)
 #define	XSSPSP_SFRMWDTH(x)	bits_val(21,16,x)
+#define	get_XSSPSP_SFRMWDTH(x)	bits_get(21,16,x)
 #define	XSSPSP_SFRMDLY_MASK	bits(15,9)
 #define	XSSPSP_SFRMDLY(x)	bits_val(15,9,x)
+#define	get_XSSPSP_SFRMDLY(x)	bits_get(15,9,x)
 #define	XSSPSP_DMYSTRT_MASK	bits(8,7)
 #define	XSSPSP_DMYSTRT(x)	bits_val(8,7,x)
+#define	get_XSSPSP_DMYSTRT(x)	bits_get(8,7,x)
 #define	XSSPSP_STRTDLY_MASK	bits(6,4)
 #define	XSSPSP_STRTDLY(x)	bits_val(6,4,x)
+#define	get_XSSPSP_STRTDLY(x)	bits_get(6,4,x)
 #define	XSSPSP_ETDS		bit(3)
 #define	XSSPSP_SFRMP		bit(2)
 #define	XSSPSP_SCMODE_MASK	bits(1,0)
 #define	XSSPSP_SCMODE(x)	bits_val(1,0,x)
+#define	get_XSSPSP_SCMODE(x)	bits_get(1,0,x)
 #endif /* PXA26x only */

 #endif /* PXA2X0_SSP_H */
--- a/include/arm/pxa2x0/udc.h
+++ b/include/arm/pxa2x0/udc.h
@ -416,20 +416,24 @@ typedef volatile struct UDC_registers {
 #define	UFNHR_IPE4		bit(3)
 #define	UFNHR_FNMSB_MASK	bits(2,0)
 #define	UFNHR_FNMSB(x)		bits_val(2,0,x)
+#define	get_UFNHR_FNMSB(x)	bits_get(2,0,x)

 /* UFNLR bits - see Table 12-32 in [1], Table 12-24 in [2] */

 #define	UNFLR_FNLSB_MASK	bits(7,0)
 #define	UFNLR_FNLSB(x)		bits_val(7,0,x)
+#define	get_UFNLR_FNLSB(x)	bits_get(7,0,x)

 /* UBCRx bits - see Table 12-33 in [1], Table 12-25 in [2] */

 #define	UBCR_BC_MASK		bits(7,0)
 #define	UBCR_BC(x)		bits_val(7,0,x)
+#define	get_UBCR_BC(x)		bits_get(7,0,x)

 /* UDDRx bits - see 12.6.15 - 12.6.20 in [1], 12.6.15 - 12.6.20 in [2] */

 #define	UDDR_DATA_MASK		bits(7,0)
 #define	UDDR_DATA(x)		bits_val(7,0,x)
+#define	get_UDDR_DATA(x)	bits_get(7,0,x)

 #endif /* PXA2X0_UDC_H */
--- a/include/configure.ac
+++ b/include/configure.ac
@ -30,14 +30,14 @@
 # Written by Marcel Telka <marcel@telka.sk>, 2002.
 #

-AC_INIT(include,0.2)
+AC_INIT(include,0.2.1)

 AC_PREREQ(2.53)
 AC_REVISION($Revision$)

 AC_CONFIG_AUX_DIR(tools)

-AM_INIT_AUTOMAKE(AC_PACKAGE_NAME,AC_PACKAGE_VERSION)
+AM_INIT_AUTOMAKE([check-news dist-bzip2])

 AC_CONFIG_FILES(
 	Makefile