diff --git a/web/htdocs/book/UrJTAG.dbk b/web/htdocs/book/UrJTAG.dbk index 95c35943..e66cdc2c 100644 --- a/web/htdocs/book/UrJTAG.dbk +++ b/web/htdocs/book/UrJTAG.dbk @@ -4,7 +4,7 @@ Universal JTAG library, server and tools - 2009-02-27 + 2009-04-08 Kolja Waschk @@ -12,7 +12,7 @@ KW( -14452009-02-27KW( +14822009-04-08KW( @@ -104,8 +104,8 @@ that. Please also send proven working files back to this project. Starting with post-0.7 releases, UrJTAG contains a BSDL subsystem that retrieves the descriptions for chips in the chain from BSDL files on the -fly. Be aware that this feature is currently experimental and may not work -with every BSDL file yet. +fly. "bsdl2jtag" is in fact a wrapper that uses the BSDL subsystem to +convert the BSDL file.
@@ -308,7 +308,7 @@ Amontec JTAGkey-Tiny (supported as cable "JTAGkey") -TinCanTools Flyswatter +KrisTech UsbScarab2 ARM JTAG http://www.kristech.eu/ @@ -333,12 +333,27 @@ Other FT2232-based USB JTAG cables (experimental) +TinCanTools Flyswatter + + + + Turtelizer 2 (experimental) http://www.ethernut.de/en/hardware/turtelizer/ -USB to JTAG Interface (experimental) http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html +USB to JTAG Interface (experimental) + + + + +http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html + + + + +Black gnICE http://docs.blackfin.uclinux.org/doku.php?id=hw:jtag:gnice @@ -383,11 +398,21 @@ Altera EP1C20F400 +Altera MAX7000 (w/ BSDL) + + + + Altera EPM7128AETC100 +Altera Cyclone I & II (w/ BSDL) + + + + Analog Devices Sharc-21065L @@ -521,6 +546,21 @@ Xilinx XCR3128XL-VQ100 Xilinx XCR3256XL-FT256 + + +Xilinx Spartan-IIE + + + + +Xilinx Spartan-3/E + + + + +Xilinx Spartan-3AN + +
@@ -554,6 +594,18 @@ AMD Am29xx040B (Am29F040B, Am29LV040B) +UrJTAG uses the multi-byte write mode if supported by the particular flash +device. The flash code will automatically switch to this algorithm if the +Device Geometry Definition reports that more than one memory location can be +written in a single step (refer to CFI details shown by detectflash). Since +multiple locations are written in a burst-like manner with only one polling +sequence afterwards, the overall flashing performance increases by factor of +5-17. + +In case you encounter any issues with the multi-byte write mode, run configure +with the —disable-flash-multi-byte option and re-compile to disable this +algorithm. +
@@ -632,7 +684,7 @@ There is a libusb-win32 variant that can be used in a Cygwin environment: For specific notes regarding the use of these libraries in a Cygwin -environmen, see below. +environment, see below.
@@ -1382,6 +1434,13 @@ located there. writing a new bus driver that utilizes a debug module to upload specific code to access the bus is inevitable. +
+
+bus +It's possible to initialize more than one bus for part(s) within a chain. The +"bus" command allows to select the active bus for readmem, flashmem, +etc. operation. +
diff --git a/web/htdocs/book/UrJTAG.html b/web/htdocs/book/UrJTAG.html index bdf22e37..fd575961 100644 --- a/web/htdocs/book/UrJTAG.html +++ b/web/htdocs/book/UrJTAG.html @@ -568,8 +568,8 @@ that. Please also send proven working files back to this project.

Starting with post-0.7 releases, UrJTAG contains a BSDL subsystem that retrieves the descriptions for chips in the chain from BSDL files on the -fly. Be aware that this feature is currently experimental and may not work -with every BSDL file yet.

  • TinCanTools Flyswatter +> KrisTech UsbScarab2 ARM JTAG http://www.kristech.eu/

  • TinCanTools Flyswatter +

  • Turtelizer 2 (experimental)

  • USB to JTAG Interface (experimental) USB to JTAG Interface (experimental) +

  • http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html

  • Black gnICE http://docs.blackfin.uclinux.org/doku.php?id=hw:jtag:gnice +

  • Xverve Signalyzer Tool (experimental)

  • Altera MAX7000 (w/ BSDL) +

  • Altera EPM7128AETC100

  • Altera Cyclone I & II (w/ BSDL) +

  • Analog Devices Sharc-21065L

    • Xilinx XCR3256XL-FT256

  • Xilinx Spartan-IIE +

  • Xilinx Spartan-3/E +

  • Xilinx Spartan-3AN +

    • UrJTAG uses the multi-byte write mode if supported by the particular flash +device. The flash code will automatically switch to this algorithm if the +Device Geometry Definition reports that more than one memory location can be +written in a single step (refer to CFI details shown by detectflash). Since +multiple locations are written in a burst-like manner with only one polling +sequence afterwards, the overall flashing performance increases by factor of +5-17.

    In case you encounter any issues with the multi-byte write mode, run configure +with the —disable-flash-multi-byte option and re-compile to disable this +algorithm.

    For specific notes regarding the use of these libraries in a Cygwin -environmen, see below.

    3.2.3.5. bus

    It's possible to initialize more than one bus for part(s) within a chain. The +"bus" command allows to select the active bus for readmem, flashmem, +etc. operation.

    For specific notes regarding the use of these libraries in a Cygwin -environmen, see below.

    Starting with post-0.7 releases, UrJTAG contains a BSDL subsystem that retrieves the descriptions for chips in the chain from BSDL files on the -fly. Be aware that this feature is currently experimental and may not work -with every BSDL file yet.

    3.2.3.5. bus

    It's possible to initialize more than one bus for part(s) within a chain. The +"bus" command allows to select the active bus for readmem, flashmem, +etc. operation.

  • TinCanTools Flyswatter +> KrisTech UsbScarab2 ARM JTAG http://www.kristech.eu/

  • TinCanTools Flyswatter +

  • Turtelizer 2 (experimental)

  • USB to JTAG Interface (experimental) USB to JTAG Interface (experimental) +

  • http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html

  • Black gnICE http://docs.blackfin.uclinux.org/doku.php?id=hw:jtag:gnice +

  • Xverve Signalyzer Tool (experimental)

  • Altera MAX7000 (w/ BSDL) +

  • Altera EPM7128AETC100

  • Altera Cyclone I & II (w/ BSDL) +

  • Analog Devices Sharc-21065L

    • Xilinx XCR3256XL-FT256

  • Xilinx Spartan-IIE +

  • Xilinx Spartan-3/E +

  • Xilinx Spartan-3AN +

    • UrJTAG uses the multi-byte write mode if supported by the particular flash +device. The flash code will automatically switch to this algorithm if the +Device Geometry Definition reports that more than one memory location can be +written in a single step (refer to CFI details shown by detectflash). Since +multiple locations are written in a burst-like manner with only one polling +sequence afterwards, the overall flashing performance increases by factor of +5-17.

    In case you encounter any issues with the multi-byte write mode, run configure +with the —disable-flash-multi-byte option and re-compile to disable this +algorithm.