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@ -25,7 +25,7 @@
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* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
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* Developer's Manual", February 2002, Order Number: 278522-001
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* [2] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
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* Specification Update", May 2002, Order Number: 278534-005
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* Specification Update", June 2002, Order Number: 278534-007
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*
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*/
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@ -103,11 +103,10 @@ typedef volatile struct MC_registers {
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#define MDMRS_OFFSET 0x40
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#define BOOT_DEF 0x44
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/* MDCNFG bits */
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/* MDCNFG bits - see Table 6-3 in [1] and D25. in [2] */
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#define MDCNFG_DSA1111_2 bit(28)
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#define MDCNFG_DLATCH2 bit(27)
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#define MDCNFG_DADDR2 bit(26)
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#define MDCNFG_DTC2_MASK 0x03000000
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#define MDCNFG_DTC2(x) ((x << 24) & MDCNFG_DTC2_MASK)
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#define MDCNFG_DNB2 bit(23)
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@ -120,7 +119,6 @@ typedef volatile struct MC_registers {
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#define MDCNFG_DE2 bit(16)
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#define MDCNFG_DSA1111_0 bit(12)
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#define MDCNFG_DLATCH0 bit(11)
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#define MDCNFG_DADDR0 bit(10)
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#define MDCNFG_DTC0_MASK 0x00000300
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#define MDCNFG_DTC0(x) ((x << 8) & MDCNFG_DTC0_MASK)
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#define MDCNFG_DNB0 bit(7)
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@ -132,7 +130,7 @@ typedef volatile struct MC_registers {
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#define MDCNFG_DE1 bit(1)
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#define MDCNFG_DE0 bit(0)
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/* MDREFR bits */
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/* MDREFR bits - see Table 6-5 in [1] */
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#define MDREFR_K2FREE bit(25)
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#define MDREFR_K1FREE bit(24)
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@ -150,7 +148,7 @@ typedef volatile struct MC_registers {
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#define MDREFR_DRI_MASK 0x00000FFF
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#define MDREFR_DRI(x) (x & MDREFR_DRI_MASK)
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/* MDMRS bits */
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/* MDMRS bits - see Table 6-4 in [1] */
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#define MDMRS_MDMRS2_MASK 0x7F800000
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#define MDMRS_MDMRS2(x) ((x << 23) & MDMRS_MDMRS2_MASK)
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