Added detect_cfi().

git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@236 b68d4a1b-bc3d-0410-92ed-d4ac073336b7
master
Marcel Telka 22 years ago
parent 75940cb85b
commit 23f6927ce7

@ -27,7 +27,7 @@ SUBDIRS = \
bin_PROGRAMS = jtag
jtag_SOURCES = jtag.c detect.c readmem.c detect.h bus.h pxa250.c sa1110.c flash.c
jtag_SOURCES = jtag.c detect.c readmem.c detect.h bus.h pxa250.c sa1110.c cfi.c flash.c
jtag_DEPENDENCIES = tap/libtap.a part/libpart.a

@ -0,0 +1,162 @@
/*
* $Id$
*
* Copyright (C) 2002 ETC s.r.o.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
* 02111-1307, USA.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
*
* Documentation:
* [1] JEDEC Solid State Technology Association, "Common Flash Interface (CFI)",
* September 1999, Order Number: JESD68
* [2] Intel Corporation, "Common Flash Interface (CFI) and Command Sets
* Application Note 646", April 2000, Order Number: 292204-004
*
*/
#include <stdint.h>
#include <stdlib.h>
#include <flash/cfi.h>
#include "bus.h"
static uint16_t
read2( parts *ps, uint32_t adr, int o )
{
uint16_t r;
bus_read_start( ps, adr << o );
r = bus_read_next( ps, (adr + 1) << o );
return ((bus_read_end( ps ) & 0xFF) << 8) | (r & 0xFF);
}
cfi_query_structure_t *
detect_cfi( parts *ps )
{
cfi_query_structure_t *cfi;
int o = 2;
uint32_t tmp;
/* TODO: 2 x 16 bit only */
/* detect CFI capable devices - see Table 1 in [1] */
bus_write( ps, CFI_CMD_QUERY_OFFSET << o, (CFI_CMD_QUERY << 16) | CFI_CMD_QUERY );
if (bus_read( ps, CFI_QUERY_ID_OFFSET << o ) != (('Q' << 16) | 'Q')) {
printf( "No CFI device detected (Q)!\n" );
return NULL;
}
if (bus_read( ps, (CFI_QUERY_ID_OFFSET + 1) << o ) != (('R' << 16) | 'R')) {
printf( "No CFI device detected (R)!\n" );
return NULL;
}
if (bus_read( ps, (CFI_QUERY_ID_OFFSET + 2) << o ) != (('Y' << 16) | 'Y')) {
printf( "No CFI device detected (Y)!\n" );
return NULL;
}
printf( "\n2 x 16 bit CFI devices detected (QRY ok)!\n\n" );
cfi = malloc( sizeof *cfi );
if (!cfi)
return NULL;
/* TODO: Low chip only (bits 15:0) */
/* Identification string - see Table 6 in [1] */
cfi->identification_string.pri_id_code = read2( ps, PRI_VENDOR_ID_OFFSET, o );
cfi->identification_string.pri_vendor_tbl = NULL;
cfi->identification_string.alt_id_code = read2( ps, ALT_VENDOR_ID_OFFSET, o );
cfi->identification_string.alt_vendor_tbl = NULL;
/* System interface information - see Table 7 in [1] */
tmp = bus_read( ps, VCC_MIN_WEV_OFFSET << o );
cfi->system_interface_info.vcc_min_wev = ((tmp >> 4) & 0xF) * 1000 + (tmp & 0xF) * 100;
tmp = bus_read( ps, VCC_MAX_WEV_OFFSET << o );
cfi->system_interface_info.vcc_max_wev = ((tmp >> 4) & 0xF) * 1000 + (tmp & 0xF) * 100;
tmp = bus_read( ps, VPP_MIN_WEV_OFFSET << o );
cfi->system_interface_info.vpp_min_wev = ((tmp >> 4) & 0xF) * 1000 + (tmp & 0xF) * 100;
tmp = bus_read( ps, VPP_MAX_WEV_OFFSET << o );
cfi->system_interface_info.vpp_max_wev = ((tmp >> 4) & 0xF) * 1000 + (tmp & 0xF) * 100;
/* TODO: Add out of range checks for timeouts */
tmp = bus_read( ps, TYP_SINGLE_WRITE_TIMEOUT_OFFSET << o ) & 0xFF;
cfi->system_interface_info.typ_single_write_timeout = tmp ? (1 << tmp) : 0;
tmp = bus_read( ps, TYP_BUFFER_WRITE_TIMEOUT_OFFSET << o ) & 0xFF;
cfi->system_interface_info.typ_buffer_write_timeout = tmp ? (1 << tmp) : 0;
tmp = bus_read( ps, TYP_BLOCK_ERASE_TIMEOUT_OFFSET << o ) & 0xFF;
cfi->system_interface_info.typ_block_erase_timeout = tmp ? (1 << tmp) : 0;
tmp = bus_read( ps, TYP_CHIP_ERASE_TIMEOUT_OFFSET << o ) & 0xFF;
cfi->system_interface_info.typ_chip_erase_timeout = tmp ? (1 << tmp) : 0;
tmp = bus_read( ps, MAX_SINGLE_WRITE_TIMEOUT_OFFSET << o ) & 0xFF;
cfi->system_interface_info.max_single_write_timeout =
(tmp ? (1 << tmp) : 0) * cfi->system_interface_info.typ_single_write_timeout;
tmp = bus_read( ps, MAX_BUFFER_WRITE_TIMEOUT_OFFSET << o ) & 0xFF;
cfi->system_interface_info.max_buffer_write_timeout =
(tmp ? (1 << tmp) : 0) * cfi->system_interface_info.typ_buffer_write_timeout;
tmp = bus_read( ps, MAX_BLOCK_ERASE_TIMEOUT_OFFSET << o ) & 0xFF;
cfi->system_interface_info.max_block_erase_timeout =
(tmp ? (1 << tmp) : 0) * cfi->system_interface_info.typ_block_erase_timeout;
tmp = bus_read( ps, MAX_CHIP_ERASE_TIMEOUT_OFFSET << o ) & 0xFF;
cfi->system_interface_info.max_chip_erase_timeout =
(tmp ? (1 << tmp) : 0) * cfi->system_interface_info.typ_chip_erase_timeout;
/* Device geometry - see Table 8 in [1] */
/* TODO: Add out of range check */
cfi->device_geometry.device_size = 1 << (bus_read( ps, DEVICE_SIZE_OFFSET << o ) & 0xFF);
cfi->device_geometry.device_interface = read2( ps, FLASH_DEVICE_INTERFACE_OFFSET, o );
/* TODO: Add out of range check */
cfi->device_geometry.max_bytes_write = 1 << read2( ps, MAX_BYTES_WRITE_OFFSET, o );
tmp = bus_read( ps, NUMBER_OF_ERASE_REGIONS_OFFSET << o ) & 0xFF;
cfi->device_geometry.number_of_erase_regions = tmp;
cfi->device_geometry.erase_block_regions = malloc( tmp * sizeof (cfi_erase_block_region_t) );
if (!cfi->device_geometry.erase_block_regions) {
free( cfi );
return NULL;
}
{
int a = ERASE_BLOCK_REGION_OFFSET;
int i;
for (i = 0, a = ERASE_BLOCK_REGION_OFFSET; i < tmp; i++, a += 4) {
uint32_t y = read2( ps, a, o );
uint32_t z = read2( ps, a + 2, o ) << 8;
if (z == 0)
z = 128;
cfi->device_geometry.erase_block_regions[i].erase_block_size = z;
cfi->device_geometry.erase_block_regions[i].number_of_erase_blocks = y + 1;
}
}
/* TODO: Intel Primary Algorithm Extended Query Table - see Table 5. in [2] */
/* Read Array */
bus_write( ps, 0, (CFI_CMD_READ_ARRAY1 << 16) | CFI_CMD_READ_ARRAY1 );
return cfi;
}

@ -50,6 +50,7 @@ readmem( parts *ps )
uint8_t boot_sel;
int o = 0;
int d = 0;
cfi_query_structure_t *cfi;
#define D_SA1110 1
#define D_PXA250 2
@ -116,128 +117,126 @@ readmem( parts *ps )
part_set_instruction( p, "EXTEST" );
parts_shift_instructions( ps );
/* detect CFI capable devices */
bus_write( ps, 0x55 << o, 0x00980098 ); /* see 3.1 in [1] */
if (bus_read( ps, 0x10 << o ) != (('Q' << 16) | 'Q')) {
printf( "No CFI device detected (Q)!\n" );
return;
}
if (bus_read( ps, 0x11 << o ) != (('R' << 16) | 'R')) {
printf( "No CFI device detected (R)!\n" );
return;
}
if (bus_read( ps, 0x12 << o ) != (('Y' << 16) | 'Y')) {
printf( "No CFI device detected (Y)!\n" );
return;
}
printf( "\n2 x 16 bit CFI devices detected (QRY ok)!\n\n" );
cfi = detect_cfi( ps );
/* detect CFI capable devices */
/* TODO: Low chip only */
/* see 3.3.2 in [1] */
printf( "CFI Query Identification String:\n" );
printf( "\tPrimary Vendor Command Set and Control Interface ID Code: 0x%02X%02X ", (uint8_t) bus_read( ps, 0x14 << o ), (uint8_t) bus_read( ps, 0x13 << o ) );
{
/* see Section 1. in [4] */
uint16_t id = ((bus_read( ps, 0x14 << o ) & 0xFF) << 8) | (bus_read( ps, 0x13 << o ) & 0xFF);
switch (id) {
case CFI_VENDOR_NULL:
printf( "(null)\n" );
break;
case CFI_VENDOR_INTEL_ECS:
printf( "(Intel/Sharp Extended Command Set)\n" );
break;
case CFI_VENDOR_AMD_SCS:
printf( "(AMD/Fujitsu Standard Commanf Set)\n" );
break;
case CFI_VENDOR_INTEL_SCS:
printf( "(Intel Standard Command Set)\n" );
break;
case CFI_VENDOR_AMD_ECS:
printf( "(AMD/Fujitsu Extended Command Set)\n" );
break;
case CFI_VENDOR_MITSUBISHI_SCS:
printf( "(Mitsubishi Standard Command Set)\n" );
break;
case CFI_VENDOR_MITSUBISHI_ECS:
printf( "(Mitsubishi Extended Command Set)\n" );
break;
case CFI_VENDOR_SST_PWCS:
printf( "(Page Write Command Set)\n" );
break;
default:
printf( "(unknown!!!)\n" );
break;
}
printf( "\tPrimary Vendor Command Set and Control Interface ID Code: 0x%04X ", cfi->identification_string.pri_id_code );
/* see Section 1. in [4] */
switch (cfi->identification_string.pri_id_code) {
case CFI_VENDOR_NULL:
printf( "(null)\n" );
break;
case CFI_VENDOR_INTEL_ECS:
printf( "(Intel/Sharp Extended Command Set)\n" );
break;
case CFI_VENDOR_AMD_SCS:
printf( "(AMD/Fujitsu Standard Commanf Set)\n" );
break;
case CFI_VENDOR_INTEL_SCS:
printf( "(Intel Standard Command Set)\n" );
break;
case CFI_VENDOR_AMD_ECS:
printf( "(AMD/Fujitsu Extended Command Set)\n" );
break;
case CFI_VENDOR_MITSUBISHI_SCS:
printf( "(Mitsubishi Standard Command Set)\n" );
break;
case CFI_VENDOR_MITSUBISHI_ECS:
printf( "(Mitsubishi Extended Command Set)\n" );
break;
case CFI_VENDOR_SST_PWCS:
printf( "(Page Write Command Set)\n" );
break;
default:
printf( "(unknown!!!)\n" );
break;
}
printf( "\tAddress of Primary Algorithm extended Query table: P = 0x%02X%02X\n", (uint8_t) bus_read( ps, 0x16 << o ), (uint8_t) bus_read( ps, 0x15 << o ) );
printf( "\tAlternate Vendor Command Set and Control Interface ID Code: 0x%02X%02X (TODO)\n", (uint8_t) bus_read( ps, 0x18 << o ), (uint8_t) bus_read( ps, 0x17 << o ) );
printf( "\tAddress of Alternate Algorithm extended Query table: A = 0x%02X%02X\n", (uint8_t) bus_read( ps, 0x1A << o ), (uint8_t) bus_read( ps, 0x19 << o ) );
printf( "\tAddress of Primary Algorithm extended Query table: P = 0x????\n" );
printf( "\tAlternate Vendor Command Set and Control Interface ID Code: 0x%04X ", cfi->identification_string.alt_id_code );
switch (cfi->identification_string.alt_id_code) {
case CFI_VENDOR_NULL:
printf( "(null)\n" );
break;
case CFI_VENDOR_INTEL_ECS:
printf( "(Intel/Sharp Extended Command Set)\n" );
break;
case CFI_VENDOR_AMD_SCS:
printf( "(AMD/Fujitsu Standard Commanf Set)\n" );
break;
case CFI_VENDOR_INTEL_SCS:
printf( "(Intel Standard Command Set)\n" );
break;
case CFI_VENDOR_AMD_ECS:
printf( "(AMD/Fujitsu Extended Command Set)\n" );
break;
case CFI_VENDOR_MITSUBISHI_SCS:
printf( "(Mitsubishi Standard Command Set)\n" );
break;
case CFI_VENDOR_MITSUBISHI_ECS:
printf( "(Mitsubishi Extended Command Set)\n" );
break;
case CFI_VENDOR_SST_PWCS:
printf( "(Page Write Command Set)\n" );
break;
default:
printf( "(unknown!!!)\n" );
break;
}
printf( "\tAddress of Alternate Algorithm extended Query table: A = 0x????\n" );
/* see 3.3.3 in [1] */
printf( "CFI Query System Interface Information:\n" );
printf( "\tVcc Logic Supply Minimum Write/Erase voltage: %d.%d V\n", (bus_read( ps, 0x1B << o ) >> 4) & 0xF, bus_read( ps, 0x1B << o ) & 0xF );
printf( "\tVcc Logic Supply Maximum Write/Erase voltage: %d.%d V\n", (bus_read( ps, 0x1C << o ) >> 4) & 0xF, bus_read( ps, 0x1C << o ) & 0xF );
printf( "\tVpp [Programming] Logic Supply Minimum Write/Erase voltage: %d.%d V\n", (bus_read( ps, 0x1D << o ) >> 4) & 0xF, bus_read( ps, 0x1D << o ) & 0xF );
printf( "\tVpp [Programming] Logic Supply Maximum Write/Erase voltage: %d.%d V\n", (bus_read( ps, 0x1E << o ) >> 4) & 0xF, bus_read( ps, 0x1E << o ) & 0xF );
printf( "\tTypical timeout per single byte/word write: %d us (0x%02X)\n", 1 << (bus_read( ps, 0x1F << o ) & 0xFF), bus_read( ps, 0x1F << o ) & 0xFF );
printf( "\tTypical timeout for minimum-size buffer write: %d us (0x%02X)\n", 1 << (bus_read( ps, 0x20 << o ) & 0xFF), bus_read( ps, 0x20 << o ) & 0xFF );
printf( "\tTypical timeout per individual block erase: %d ms (0x%02X)\n", 1 << (bus_read( ps, 0x21 << o ) & 0xFF), bus_read( ps, 0x21 << o ) & 0xFF );
printf( "\tTypical timeout for full chip erase: %d ms (0x%02X)\n", 1 << (bus_read( ps, 0x22 << o ) & 0xFF), bus_read( ps, 0x22 << o ) & 0xFF );
printf( "\tMaximum timeout for byte/word write: %d us (0x%02X)\n", 1 << ((bus_read( ps, 0x23 << o ) + bus_read( ps, 0x1F << o )) & 0xFF), bus_read( ps, 0x23 << o ) & 0xFF );
printf( "\tMaximum timeout for buffer write: %d us (0x%02X)\n", 1 << ((bus_read( ps, 0x24 << o ) + bus_read( ps, 0x20 << o )) & 0xFF), bus_read( ps, 0x24 << o ) & 0xFF );
printf( "\tMaximum timeout per individual block erase: %d ms (0x%02X)\n", 1 << ((bus_read( ps, 0x25 << o ) + bus_read( ps, 0x21 << o )) & 0xFF), bus_read( ps, 0x25 << o ) & 0xFF );
printf( "\tMaximum timeout for chip erase: %d ms (0x%02X)\n", 1 << ((bus_read( ps, 0x26 << o ) + bus_read( ps, 0x22 << o )) & 0xFF), bus_read( ps, 0x26 << o ) & 0xFF );
printf( "\tVcc Logic Supply Minimum Write/Erase voltage: %d mV\n", cfi->system_interface_info.vcc_min_wev );
printf( "\tVcc Logic Supply Maximum Write/Erase voltage: %d mV\n", cfi->system_interface_info.vcc_max_wev );
printf( "\tVpp [Programming] Logic Supply Minimum Write/Erase voltage: %d mV\n", cfi->system_interface_info.vpp_min_wev );
printf( "\tVpp [Programming] Logic Supply Maximum Write/Erase voltage: %d mV\n", cfi->system_interface_info.vpp_max_wev );
printf( "\tTypical timeout per single byte/word write: %d us\n", cfi->system_interface_info.typ_single_write_timeout );
printf( "\tTypical timeout for minimum-size buffer write: %d us\n", cfi->system_interface_info.typ_buffer_write_timeout );
printf( "\tTypical timeout per individual block erase: %d ms\n", cfi->system_interface_info.typ_block_erase_timeout );
printf( "\tTypical timeout for full chip erase: %d ms\n", cfi->system_interface_info.typ_chip_erase_timeout );
printf( "\tMaximum timeout for byte/word write: %d us\n", cfi->system_interface_info.max_single_write_timeout );
printf( "\tMaximum timeout for buffer write: %d us\n", cfi->system_interface_info.max_buffer_write_timeout );
printf( "\tMaximum timeout per individual block erase: %d ms\n", cfi->system_interface_info.max_block_erase_timeout );
printf( "\tMaximum timeout for chip erase: %d ms\n", cfi->system_interface_info.max_chip_erase_timeout );
/* see 3.3.4 in [1] */
printf( "Device Geometry Definition:\n" );
printf( "\tDevice Size: %d B (0x%02X)\n", 1 << (bus_read( ps, 0x27 << o ) & 0xFF), bus_read( ps, 0x27 << o ) & 0xFF );
printf( "\tFlash Device Interface description: 0x%02X%02X ", bus_read( ps, 0x29 << o ) & 0xFF, bus_read( ps, 0x28 << o ) & 0xFF );
{
/* see Section 2. in [4] */
uint16_t id = ((bus_read( ps, 0x29 << o ) & 0xFF) << 8) | (bus_read( ps, 0x28 << o ) & 0xFF);
switch (id) {
case CFI_INTERFACE_X8:
printf( "(x8)\n" );
break;
case CFI_INTERFACE_X16:
printf( "(x16)\n" );
break;
case CFI_INTERFACE_X8_X16:
printf( "(x8/x16)\n" );
break;
case CFI_INTERFACE_X32:
printf( "(x32)\n" );
break;
case CFI_INTERFACE_X16_X32:
printf( "(x16/x32)\n" );
break;
default:
printf( "(unknown!!!)\n" );
break;
}
printf( "\tDevice Size: %d B\n", cfi->device_geometry.device_size );
printf( "\tFlash Device Interface description: 0x%04X ", cfi->device_geometry.device_interface );
/* see Section 2. in [4] */
switch (cfi->device_geometry.device_interface) {
case CFI_INTERFACE_X8:
printf( "(x8)\n" );
break;
case CFI_INTERFACE_X16:
printf( "(x16)\n" );
break;
case CFI_INTERFACE_X8_X16:
printf( "(x8/x16)\n" );
break;
case CFI_INTERFACE_X32:
printf( "(x32)\n" );
break;
case CFI_INTERFACE_X16_X32:
printf( "(x16/x32)\n" );
break;
default:
printf( "(unknown!!!)\n" );
break;
}
printf( "\tMaximum number of bytes in multi-byte write: %d\n", 1 << (((bus_read( ps, 0x2B << o ) & 0xFF) << 8) | (bus_read( ps, 0x2A << o ) & 0xFF)) );
printf( "\tNumber of Erase Block Regions within device: %d\n", bus_read( ps, 0x2C << o ) & 0xFF );
printf( "\tMaximum number of bytes in multi-byte write: %d\n", cfi->device_geometry.max_bytes_write );
printf( "\tNumber of Erase Block Regions within device: %d\n", cfi->device_geometry.number_of_erase_regions );
printf( "\tErase Block Region Information:\n" );
{
int a = 0x2D;
int c = bus_read( ps, 0x2C << o ) & 0xFF;
int i;
for (i = 0; i < c; i++, a += 4) {
uint32_t z = ((bus_read( ps, (a + 3) << o ) & 0xFF) << 16) | ((bus_read( ps, (a + 2) << o ) & 0xFF) << 8);
uint32_t y = ((bus_read( ps, (a + 1) << o ) & 0xFF) << 8) | (bus_read( ps, a << o ) & 0xFF);
for (i = 0; i < cfi->device_geometry.number_of_erase_regions; i++) {
printf( "\t\tRegion %d:\n", i );
if (z == 0)
z = 128;
printf( "\t\t\tErase Block Size: %d\n", z );
printf( "\t\t\tNumber of Erase Blocks: %d\n", y + 1 );
printf( "\t\t\tErase Block Size: %d\n", cfi->device_geometry.erase_block_regions[i].erase_block_size );
printf( "\t\t\tNumber of Erase Blocks: %d\n", cfi->device_geometry.erase_block_regions[i].number_of_erase_blocks );
}
}

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