2004-12-20 Marcel Telka <marcel@telka.sk>
* device/other/hd64461/gpio.h: New file. * device/other/hd64461/intc.h: Ditto. * device/other/hd64461/lcdc.h: Ditto. * device/other/hd64461/pcc.h: Ditto. * device/other/hd64461/stbsys.h: Ditto. * device/other/hd64461/timer.h: Ditto. * Makefile.am (nobase_openwinceinc_HEADERS): Added new files. git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@626 b68d4a1b-bc3d-0410-92ed-d4ac073336b7master
Marcel Telka
20 years ago
parent
27b8216318
commit
54356002cf
@ -0,0 +1,103 @@
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/*
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* $Id$
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*
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* Hitachi HD64461 Pin Function Controller & I/O Port Registers
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* Copyright (C) 2004 Marcel Telka
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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||||
*
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||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
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||||
* * Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and/or other materials provided
|
||||
* with the distribution.
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||||
* * Neither the name of the copyright holders nor the names of their
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Written by Marcel Telka <marcel@telka.sk>, 2004.
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*
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* Documentation:
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* [1] Hitachi, Ltd., "HD64461 Windows(R) CE Intelligent Peripheral Controller",
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* 1st Edition, July 1998, Order Number: ADE-602-076
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*
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*/
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#ifndef HD64461_GPIO_H
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#define HD64461_GPIO_H
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#include <common.h>
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#if LANGUAGE == C
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#include <stdint.h>
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#endif
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/* Pin Function Controller & I/O Port Registers */
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#if LANGUAGE == C
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typedef volatile struct GPIO_registers {
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uint16_t gpacr;
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uint16_t gpbcr;
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uint16_t gpccr;
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uint16_t gpdcr;
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uint16_t __reserved1[4];
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uint8_t gpadr;
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uint8_t __reserved2;
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uint8_t gpbdr;
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uint8_t __reserved3;
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uint8_t gpcdr;
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uint8_t __reserved4;
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uint8_t gpddr;
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uint8_t __reserved5[9];
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uint8_t gpaicr;
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uint8_t __reserved6;
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uint8_t gpbicr;
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uint8_t __reserved7;
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uint8_t gpcicr;
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uint8_t __reserved8;
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uint8_t gpdicr;
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uint8_t __reserved9[25];
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uint8_t gpaisr;
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uint8_t __reserved10;
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uint8_t gpbisr;
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uint8_t __reserved11;
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uint8_t gpcisr;
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uint8_t __reserved12;
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uint8_t gpdisr;
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} GPIO_registers_t;
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#endif /* LANGUAGE == C */
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#define GPACR_OFFSET 0x00
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#define GPBCR_OFFSET 0x02
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#define GPCCR_OFFSET 0x04
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#define GPDCR_OFFSET 0x06
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#define GPADR_OFFSET 0x10
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#define GPBDR_OFFSET 0x12
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#define GPCDR_OFFSET 0x14
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#define GPDDR_OFFSET 0x16
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#define GPAICR_OFFSET 0x20
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#define GPBICR_OFFSET 0x22
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#define GPCICR_OFFSET 0x24
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#define GPDICR_OFFSET 0x26
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#define GPAISR_OFFSET 0x40
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#define GPBISR_OFFSET 0x42
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#define GPCISR_OFFSET 0x44
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#define GPDISR_OFFSET 0x46
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#endif /* HD64461_GPIO_H */
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@ -0,0 +1,83 @@
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/*
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* $Id$
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*
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* Hitachi HD64461 Interrupt Controller Registers
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* Copyright (C) 2004 Marcel Telka
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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||||
* * Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
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||||
* * Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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||||
* * Neither the name of the copyright holders nor the names of their
|
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* contributors may be used to endorse or promote products derived
|
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* from this software without specific prior written permission.
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||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Written by Marcel Telka <marcel@telka.sk>, 2004.
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*
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* Documentation:
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* [1] Hitachi, Ltd., "HD64461 Windows(R) CE Intelligent Peripheral Controller",
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* 1st Edition, July 1998, Order Number: ADE-602-076
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*
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*/
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#ifndef HD64461_INTC_H
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#define HD64461_INTC_H
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#include <common.h>
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#if LANGUAGE == C
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#include <stdint.h>
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#endif
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/* Interrupt Controller Registers */
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#if LANGUAGE == C
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typedef volatile struct INTC_registers {
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uint16_t nirr;
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uint16_t nimr;
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} INTC_registers_t;
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#endif /* LANGUAGE == C */
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#define NIRR_OFFSET 0x00
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#define NIMR_OFFSET 0x02
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/* NIRR bits */
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#define NIRR_PCC0R bit(14)
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#define NIRR_PCC1R bit(13)
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#define NIRR_AFER bit(12)
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#define NIRR_GPIOR bit(11)
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#define NIRR_TMU0R bit(10)
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#define NIRR_TMU1R bit(9)
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#define NIRR_IRDAR bit(6)
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#define NIRR_UARTR bit(5)
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/* NIMR bits */
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#define NIMR_PCC0M bit(14)
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#define NIMR_PCC1M bit(13)
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#define NIMR_AFEM bit(12)
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#define NIMR_GPIOM bit(11)
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#define NIMR_TMU0M bit(10)
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#define NIMR_TMU1M bit(9)
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#define NIMR_IRDAM bit(6)
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#define NIMR_UARTM bit(5)
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#endif /* HD64461_INTC_H */
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@ -0,0 +1,331 @@
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/*
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* $Id$
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*
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* Hitachi HD64461 Color LCD Controller Registers
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* Copyright (C) 2004 Marcel Telka
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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||||
* * Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and/or other materials provided
|
||||
* with the distribution.
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* * Neither the name of the copyright holders nor the names of their
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* contributors may be used to endorse or promote products derived
|
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Written by Marcel Telka <marcel@telka.sk>, 2004.
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*
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* Documentation:
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* [1] Hitachi, Ltd., "HD64461 Windows(R) CE Intelligent Peripheral Controller",
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* 1st Edition, July 1998, Order Number: ADE-602-076
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*
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*/
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#ifndef HD64461_LCDC_H
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#define HD64461_LCDC_H
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#include <common.h>
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#if LANGUAGE == C
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#include <stdint.h>
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#endif
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/* Color LCD Controller Registers */
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#if LANGUAGE == C
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typedef volatile struct LCDC_registers {
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uint16_t lcdcbar;
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uint16_t lcdclor;
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uint16_t lcdccr;
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uint16_t __reserved1[5];
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uint16_t ldr1;
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uint16_t ldr2;
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uint16_t ldhncr;
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uint16_t ldhnsr;
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uint16_t ldvntr;
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uint16_t ldvndr;
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uint16_t ldvspr;
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uint16_t ldr3;
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uint16_t crtvtr;
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uint16_t crtvrsr;
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uint16_t vrtvrer;
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uint16_t __reserved2[5];
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uint16_t cptwar;
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uint16_t cptwdr;
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uint16_t cptrar;
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uint16_t cptrdr;
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uint16_t __reserved3[4];
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uint16_t grdor;
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uint16_t grscr;
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uint16_t grcfgr;
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uint16_t lnsarh;
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uint16_t lnsarl;
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uint16_t lnaxlr;
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uint16_t lndgr;
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uint16_t lnaxr;
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uint16_t lnertr;
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uint16_t lnmdr;
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uint16_t bbtssarh;
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uint16_t bbtssarl;
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uint16_t bbtdsarh;
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uint16_t bbtdsarl;
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uint16_t bbtdwr;
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uint16_t bbtdhr;
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uint16_t bbtparh;
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uint16_t bbtparl;
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uint16_t bbtmarh;
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uint16_t bbtmarl;
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uint16_t bbtropr;
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uint16_t bbtmdr;
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} LCDC_registers_t;
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#endif /* LANGUAGE == C */
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#define LCDCBAR_OFFSET 0x00
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#define LCDCLOR_OFFSET 0x02
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#define LCDCCR_OFFSET 0x04
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#define LDR1_OFFSET 0x10
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#define LDR2_OFFSET 0x12
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#define LDHNCR_OFFSET 0x14
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#define LDHNSR_OFFSET 0x16
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#define LDVNTR_OFFSET 0x18
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#define LDVNDR_OFFSET 0x1A
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#define LDVSPR_OFFSET 0x1C
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#define LDR3_OFFSET 0x1E
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#define CRTVTR_OFFSET 0x20
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#define CRTVRSR_OFFSET 0x22
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#define CRTVRER_OFFSET 0x24
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#define CPTWAR_OFFSET 0x30
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#define CPTWDR_OFFSET 0x32
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#define CPTRAR_OFFSET 0x34
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#define CPTRDR_OFFSET 0x36
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#define GRDOR_OFFSET 0x40
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#define GRSCR_OFFSET 0x42
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#define GRCFGR_OFFSET 0x44
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#define LNSARH_OFFSET 0x46
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#define LNSARL_OFFSET 0x48
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#define LNAXLR_OFFSET 0x4A
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#define LNDGR_OFFSET 0x4C
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#define LNAXR_OFFSET 0x4E
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#define LNERTR_OFFSET 0x50
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#define LNMDR_OFFSET 0x52
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#define BBTSSARH_OFFSET 0x54
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#define BBTSSARL_OFFSET 0x56
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#define BBTDSARH_OFFSET 0x58
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#define BBTDSARL_OFFSET 0x5A
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#define BBTDWR_OFFSET 0x5C
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#define BBTDHR_OFFSET 0x5E
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#define BBTPARH_OFFSET 0x60
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#define BBTPARL_OFFSET 0x62
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#define BBTMARH_OFFSET 0x64
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#define BBTMARL_OFFSET 0x66
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#define BBTROPR_OFFSET 0x68
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#define BBTMDR_OFFSET 0x6A
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/* LCDCBAR bits */
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#define LCDCBAR_BAD_MASK bits(13,0)
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#define LCDCBAR_BAD(x) bits_val(13,0,x)
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#define get_LCDCBAR_BAD(x) bits_get(13,0,x)
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/* LCDCLOR bits */
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#define LCDCLOR_LO_MASK bits(10,0)
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#define LCDCLOR_LO(x) bits_val(10,0,x)
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#define get_LCDCLOR_LO(x) bits_get(10,0,x)
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/* LCDCCR bits */
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#define LCDCCR_STBACK bit(10)
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#define LCDCCR_STREQ bit(8)
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#define LCDCCR_MOFF bit(7)
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#define LCDCCR_REFSEL bit(6)
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#define LCDCCR_EPON bit(5)
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#define LCDCCR_SPON bit(4)
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#define LCDCCR_DSPSEL_MASK bits(2,0)
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#define LCDCCR_DSPSEL(x) bits_val(2,0,x)
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#define get_LCDCCR_DSPSEL(x) bits_get(2,0,x)
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/* LDR1 bits */
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#define LDR1_DINV bit(8)
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#define LDR1_DON bit(0)
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/* LDR2 bits */
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#define LDR2_CC1 bit(7)
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#define LDR2_CC2 bit(6)
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#define LDR2_LM_MASK bits(2,0)
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#define LDR2_LM(x) bits_val(2,0,x)
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#define get_LDR2_LM(x) bits_get(2,0,x)
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/* LDHNCR bits */
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#define LDHNCR_NHD_MASK bits(15,8)
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#define LDHNCR_NHD(x) bits_val(15,8,x)
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#define get_LDHNCR_NHD(x) bits_get(15,8,x)
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#define LDHNCR_NHT_MASK bits(7,0)
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#define LDHNCR_NHT(x) bits_val(7,0,x)
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#define get_LDHNCR_NHT(x) bits_get(7,0,x)
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/* LDHNSR bits */
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#define LDHNSR_HSW_MASK bits(11,8)
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#define LDHNSR_HSW(x) bits_val(11,8,x)
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#define get_LDHNSR_HSW(x) bits_get(11,8,x)
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#define LDHNSR_HSP_MASK bits(7,0)
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#define LDHNSR_HSP(x) bits_val(7,0,x)
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#define get_LDHNSR_HSP(x) bits_get(7,0,x)
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/* LDVNTR bits */
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#define LDVNTR_VTL_MASK bits(9,0)
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#define LDVNTR_VTL(x) bits_val(9,0,x)
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#define get_LDVNTR_VTL(x) bits_get(9,0,x)
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/* LDVNDR bits */
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#define LDVNDR_VDL_MASK bits(9,0)
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#define LDVNDR_VDL(x) bits_val(9,0,x)
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#define get_LDVNDR_VDL(x) bits_get(9,0,x)
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/* LDVSPR bits */
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#define LDVSPR_VSP_MASK bits(9,0)
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#define LDVSPR_VSP(x) bits_val(9,0,x)
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#define get_LDVSPR_VSP(x) bits_get(9,0,x)
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/* LDR3 bits */
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#define LDR3_CS_MASK bits(9,5)
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#define LDR3_CS(x) bits_val(9,5,x)
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#define get_LDR3_CS(x) bits_get(9,5,x)
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#define LDR3_CG_MASK bits(3,0)
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#define LDR3_CG(x) bits_val(3,0,x)
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#define get_LDR3_CG(x) bits_get(3,0,x)
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/* CRTVTR bits */
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#define CRTVTR_CRTVTR_MASK bits(9,0)
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#define CRTVTR_CRTVTR(x) bits_val(9,0,x)
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#define get_CRTVTR_CRTVTR(x) bits_get(9,0,x)
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/* CRTVRSR bits */
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#define CRTVRSR_CRTVRSR_MASK bits(9,0)
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#define CRTVRSR_CRTVRSR(x) bits_val(9,0,x)
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#define get_CRTVRSR_CRTVRSR(x) bits_get(9,0,x)
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/* CRTVRER bits */
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#define CRTVRER_CRTVRER_MASK bits(3,0)
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#define CRTVRER_CRTVRER(x) bits_val(3,0,x)
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#define get_CRTVRER_CRTVRER(x) bits_get(3,0,x)
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/* CPTWAR bits */
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#define CPTWAR_WRITE_PALETTE_NUM_MASK bits(15,8)
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#define CPTWAR_WRITE_PALETTE_NUM(x) bits_val(15,8,x)
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#define get_CPTWAR_WRITE_PALETTE_NUM(x) bits_get(15,8,x)
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/* CPTWDR bits */
|
||||
#define CPTWDR_WRITE_PALETTE_D_MASK bits(5,0)
|
||||
#define CPTWDR_WRITE_PALETTE_D(x) bits_val(5,0,x)
|
||||
#define get_CPTWDR_WRITE_PALETTE_D(x) bits_get(5,0,x)
|
||||
|
||||
/* CPTRAR bits */
|
||||
#define CPTRAR_READ_PALETTE_NUM_MASK bits(15,8)
|
||||
#define CPTRAR_READ_PALETTE_NUM(x) bits_val(15,8,x)
|
||||
#define get_CPTRAR_READ_PALETTE_NUM(x) bits_get(15,8,x)
|
||||
|
||||
/* CPTRDR bits */
|
||||
#define CPTRDR_READ_PALETTE_D_MASK bits(5,0)
|
||||
#define CPTRDR_READ_PALETTE_D(x) bits_val(5,0,x)
|
||||
#define get_CPTRDR_READ_PALETTE_D(x) bits_get(5,0,x)
|
||||
|
||||
/* GRDOR bits */
|
||||
#define GRDOR_GRDOR_MASK bits(10,0)
|
||||
#define GRDOR_GRDOR(x) bits_val(10,0,x)
|
||||
#define get_GRDOR_GRDOR(x) bits_get(10,0,x)
|
||||
|
||||
/* GRCFGR bits */
|
||||
#define GRCFGR_ACCSTATUS bit(4)
|
||||
#define GRCFGR_ACCRESET bit(3)
|
||||
#define GRCFGR_ACCSTART_MASK bits(2,1)
|
||||
#define GRCFGR_ACCSTART(x) bits_val(2,1,x)
|
||||
#define get_GRCFGR_ACCSTART(x) bits_get(2,1,x)
|
||||
#define GRCFGR_COLORDEPTH bit(0)
|
||||
|
||||
/* LNSARH bits */
|
||||
#define LNSARH_LNSARH_MASK bits(2,0)
|
||||
#define LNSARH_LNSARH(x) bits_val(2,0,x)
|
||||
#define get_LNSARH_LNSARH(x) bits_get(2,0,x)
|
||||
|
||||
/* LNAXLR bits */
|
||||
#define LNAXLR_LNAXLR_MASK bits(10,0)
|
||||
#define LNAXLR_LNAXLR(x) bits_val(10,0,x)
|
||||
#define get_LNAXLR_LNAXLR(x) bits_get(10,0,x)
|
||||
|
||||
/* LNDGR bits */
|
||||
#define LNDGR_LNDGR_SIGN bit(15)
|
||||
#define LNDGR_LNDGR_MASK bits(10,0)
|
||||
#define LNDGR_LNDGR(x) bits_val(10,0,x)
|
||||
#define get_LNDGR_LNDGR(x) bits_get(10,0,x)
|
||||
|
||||
/* LNAXR bits */
|
||||
#define LNAXR_LNAXR_MASK bits(11,0)
|
||||
#define LNAXR_LNAXR(x) bits_val(10,0,x)
|
||||
#define get_LNAXR_LNAXR(x) bits_get(10,0,x)
|
||||
|
||||
/* LNERTR bits */
|
||||
#define LNERTR_LNERTR_SIGN bit(15)
|
||||
#define LNERTR_LNERTR_MASK bits(10,0)
|
||||
#define LNERTR_LNERTR(x) bits_val(10,0,x)
|
||||
#define get_LNERTR_LNERTR(x) bits_get(10,0,x)
|
||||
|
||||
/* LNMDR bits */
|
||||
#define LNMDR_LNMDR_MASK bits(1,0)
|
||||
#define LNMDR_LNMDR(x) bits_val(1,0,x)
|
||||
#define get_LNMDR_LNMDR(x) bits_get(1,0,x)
|
||||
|
||||
/* BBTSSARH bits */
|
||||
#define BBTSSARH_BBTSSARH_MASK bits(2,0)
|
||||
#define BBTSSARH_BBTSSARH(x) bits_val(2,0,x)
|
||||
#define get_BBTSSARH_BBTSSARH(x) bits_get(2,0,x)
|
||||
|
||||
/* BBTDSARH bits */
|
||||
#define BBTDSARH_BBTDSARH_MASK bits(2,0)
|
||||
#define BBTDSARH_BBTDSARH(x) bits_val(2,0,x)
|
||||
#define get_BBTDSARH_BBTDSARH(x) bits_get(2,0,x)
|
||||
|
||||
/* BBTDWR bits */
|
||||
#define BBTDWR_BBTDWR_MASK bits(10,0)
|
||||
#define BBTDWR_BBTDWR(x) bits_val(10,0,x)
|
||||
#define get_BBTDWR_BBTDWR(x) bits_get(10,0,x)
|
||||
|
||||
/* BBTDHR bits */
|
||||
#define BBTDHR_BBTDHR_MASK bits(10,0)
|
||||
#define BBTDHR_BBTDHR(x) bits_val(10,0,x)
|
||||
#define get_BBTDHR_BBTDHR(x) bits_get(10,0,x)
|
||||
|
||||
/* BBTPARH bits */
|
||||
#define BBTPARH_BBTPARH_MASK bits(2,0)
|
||||
#define BBTPARH_BBTPARH(x) bits_val(2,0,x)
|
||||
#define get_BBTPARH_BBTPARH(x) bits_get(2,0,x)
|
||||
|
||||
/* BBTMARH bits */
|
||||
#define BBTMARH_BBTMARH_MASK bits(2,0)
|
||||
#define BBTMARH_BBTMARH(x) bits_val(2,0,x)
|
||||
#define get_BBTMARH_BBTMARH(x) bits_get(2,0,x)
|
||||
|
||||
/* BBTMDR bits */
|
||||
#define BBTMDR_MSKENABLE bit(5)
|
||||
#define BBTMDR_PATSELECT bit(4)
|
||||
#define BBTMDR_SCREENSELECT_MASK bits(3,2)
|
||||
#define BBTMDR_SCREENSELECT(x) bits_val(3,2,x)
|
||||
#define get_BBTMDR_SCREENSELECT(x) bits_get(3,2,x)
|
||||
#define BBTMDR_SCANDRCT bit(0)
|
||||
|
||||
#endif /* HD64461_LCDC_H */
|
||||
@ -0,0 +1,191 @@
|
||||
/*
|
||||
* $Id$
|
||||
*
|
||||
* Hitachi HD64461 PC Card Controller Registers
|
||||
* Copyright (C) 2004 Marcel Telka
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and/or other materials provided
|
||||
* with the distribution.
|
||||
* * Neither the name of the copyright holders nor the names of their
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Written by Marcel Telka <marcel@telka.sk>, 2004.
|
||||
*
|
||||
* Documentation:
|
||||
* [1] Hitachi, Ltd., "HD64461 Windows(R) CE Intelligent Peripheral Controller",
|
||||
* 1st Edition, July 1998, Order Number: ADE-602-076
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef HD64461_PCC_H
|
||||
#define HD64461_PCC_H
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#if LANGUAGE == C
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
/* PC Card Controller Registers */
|
||||
|
||||
#if LANGUAGE == C
|
||||
typedef volatile struct PCC_registers {
|
||||
uint8_t pcc0isr;
|
||||
uint8_t __reserved1;
|
||||
uint8_t pcc0gcr;
|
||||
uint8_t __reserved2;
|
||||
uint8_t pcc0cscr;
|
||||
uint8_t __reserved3;
|
||||
uint8_t pcc0cscier;
|
||||
uint8_t __reserved4;
|
||||
uint8_t pcc0scr;
|
||||
uint8_t __reserved5[7];
|
||||
uint8_t pcc1isr;
|
||||
uint8_t __reserved6;
|
||||
uint8_t pcc1gcr;
|
||||
uint8_t __reserved7;
|
||||
uint8_t pcc1cscr;
|
||||
uint8_t __reserved8;
|
||||
uint8_t pcc1cscier;
|
||||
uint8_t __reserved9;
|
||||
uint8_t pcc1scr;
|
||||
uint8_t __reserved10[17];
|
||||
uint8_t p0ocr;
|
||||
uint8_t __reserved11;
|
||||
uint8_t p1ocr;
|
||||
uint8_t __reserved12;
|
||||
uint8_t pgcr;
|
||||
} PCC_registers_t;
|
||||
#endif /* LANGUAGE == C */
|
||||
|
||||
#define PCC0ISR_OFFSET 0x00
|
||||
#define PCC0GCR_OFFSET 0x02
|
||||
#define PCC0CSCR_OFFSET 0x04
|
||||
#define PCC0CSCIER_OFFSET 0x06
|
||||
#define PCC0SCR_OFFSET 0x08
|
||||
#define PCC1ISR_OFFSET 0x10
|
||||
#define PCC1GCR_OFFSET 0x12
|
||||
#define PCC1CSCR_OFFSET 0x14
|
||||
#define PCC1CSCIER_OFFSET 0x16
|
||||
#define PCC1SCR_OFFSET 0x18
|
||||
#define P0OCR_OFFSET 0x2A
|
||||
#define P1OCR_OFFSET 0x2C
|
||||
#define PGCR_OFFSET 0x2E
|
||||
|
||||
/* PCC0ISR bits */
|
||||
#define PCC0ISR_P0READY bit(7)
|
||||
#define PCC0ISR_P0MWP bit(6)
|
||||
#define PCC0ISR_P0VS2 bit(5)
|
||||
#define PCC0ISR_P0VS1 bit(4)
|
||||
#define PCC0ISR_P0CD2 bit(3)
|
||||
#define PCC0ISR_P0CD1 bit(2)
|
||||
#define PCC0ISR_P0BVD2 bit(1)
|
||||
#define PCC0ISR_P0BVD1 bit(0)
|
||||
|
||||
/* PCC0GCR bits */
|
||||
#define PCC0GCR_P0DRVE bit(7)
|
||||
#define PCC0GCR_P0PCCR bit(6)
|
||||
#define PCC0GCR_P0PCCT bit(5)
|
||||
#define PCC0GCR_P0VCC0 bit(4)
|
||||
#define PCC0GCR_P0MMOD bit(3)
|
||||
#define PCC0GCR_P0PA25 ` bit(2)
|
||||
#define PCC0GCR_P0PA24 bit(1)
|
||||
#define PCC0GCR_P0REG bit(0)
|
||||
|
||||
/* PCC0CSCR bits */
|
||||
#define PCC0CSCR_P0SCDI bit(7)
|
||||
#define PCC0CSCR_P0IREQ bit(5)
|
||||
#define PCC0CSCR_P0SC bit(4)
|
||||
#define PCC0CSCR_P0CDC bit(3)
|
||||
#define PCC0CSCR_P0RC bit(2)
|
||||
#define PCC0CSCR_P0BW bit(1)
|
||||
#define PCC0CSCR_P0BD bit(0)
|
||||
|
||||
/* PCC0CSCIER bits */
|
||||
#define PCC0CSCIER_P0CRE bit(7)
|
||||
#define PCC0CSCIER_P0IREQE1 bit(6)
|
||||
#define PCC0CSCIER_P0IREQE0 bit(5)
|
||||
#define PCC0CSCIER_P0SCE bit(4)
|
||||
#define PCC0CSCIER_P0CDE bit(3)
|
||||
#define PCC0CSCIER_P0RE bit(2)
|
||||
#define PCC0CSCIER_P0BWE bit(1)
|
||||
#define PCC0CSCIER_P0BDE bit(0)
|
||||
|
||||
/* PCC0SCR bits */
|
||||
#define PCC0SCR_P0VCC1 bit(1)
|
||||
#define PCC0SCR_P0SWP bit(0)
|
||||
|
||||
/* PCC1ISR bits */
|
||||
#define PCC1ISR_P1READY bit(7)
|
||||
#define PCC1ISR_P1MWP bit(6)
|
||||
#define PCC1ISR_P1VS2 bit(5)
|
||||
#define PCC1ISR_P1VS1 bit(4)
|
||||
#define PCC1ISR_P1CD2 bit(3)
|
||||
#define PCC1ISR_P1CD1 bit(2)
|
||||
#define PCC1ISR_P1BVD2 bit(1)
|
||||
#define PCC1ISR_P1BVD1 bit(0)
|
||||
|
||||
/* PCC1GCR bits */
|
||||
#define PCC1GCR_P1DRVE bit(7)
|
||||
#define PCC1GCR_P1PCCR bit(6)
|
||||
#define PCC1GCR_P1VCC0 bit(4)
|
||||
#define PCC1GCR_P1MMOD bit(3)
|
||||
#define PCC1GCR_P1PA25 ` bit(2)
|
||||
#define PCC1GCR_P1PA24 bit(1)
|
||||
#define PCC1GCR_P1REG bit(0)
|
||||
|
||||
/* PCC1CSCR bits */
|
||||
#define PCC1CSCR_P1SCDI bit(7)
|
||||
#define PCC1CSCR_P1CDC bit(3)
|
||||
#define PCC1CSCR_P1RC bit(2)
|
||||
#define PCC1CSCR_P1BW bit(1)
|
||||
#define PCC1CSCR_P1BD bit(0)
|
||||
|
||||
/* PCC1CSCIER bits */
|
||||
#define PCC1CSCIER_P1CRE bit(7)
|
||||
#define PCC1CSCIER_P1CDE bit(3)
|
||||
#define PCC1CSCIER_P1RE bit(2)
|
||||
#define PCC1CSCIER_P1BWE bit(1)
|
||||
#define PCC1CSCIER_P1BDE bit(0)
|
||||
|
||||
/* PCC1SCR bits */
|
||||
#define PCC1SCR_P1VCC1 bit(1)
|
||||
#define PCC1SCR_P1SWP bit(0)
|
||||
|
||||
/* P0OCR bits */
|
||||
#define P0OCR_P0DEPLUP bit(7)
|
||||
#define P0OCR_P0AEPLUP bit(4)
|
||||
|
||||
/* P1OCR bits */
|
||||
#define P1OCR_P1RST8MA bit(3)
|
||||
#define P1OCR_P1RST4MA bit(2)
|
||||
#define P1OCR_P1RAS8MA bit(1)
|
||||
#define P1OCR_P1RAS4MA bit(0)
|
||||
|
||||
/* PGCR bits */
|
||||
#define PGCR_PSSDIR bit(1)
|
||||
#define PGCR_PSSRDWR bit(0)
|
||||
|
||||
#endif /* HD64461_PCC_H */
|
||||
@ -0,0 +1,106 @@
|
||||
/*
|
||||
* $Id$
|
||||
*
|
||||
* Hitachi HD64461 Standby Mode and System Configuration Registers
|
||||
* Copyright (C) 2004 Marcel Telka
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and/or other materials provided
|
||||
* with the distribution.
|
||||
* * Neither the name of the copyright holders nor the names of their
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Written by Marcel Telka <marcel@telka.sk>, 2004.
|
||||
*
|
||||
* Documentation:
|
||||
* [1] Hitachi, Ltd., "HD64461 Windows(R) CE Intelligent Peripheral Controller",
|
||||
* 1st Edition, July 1998, Order Number: ADE-602-076
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef HD64461_STBSYS_H
|
||||
#define HD64461_STBSYS_H
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#if LANGUAGE == C
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
/* Standby Mode and System Configuration Registers */
|
||||
|
||||
#if LANGUAGE == C
|
||||
typedef volatile struct STBSYS_registers {
|
||||
uint16_t stbcr;
|
||||
uint16_t syscr;
|
||||
uint16_t scpucr;
|
||||
} STBSYS_registers_t;
|
||||
#endif /* LANGUAGE == C */
|
||||
|
||||
#define STBCR_OFFSET 0x00
|
||||
#define SYSCR_OFFSET 0x02
|
||||
#define SCPUCR_OFFSET 0x04
|
||||
|
||||
/* STBCR bits */
|
||||
#define STBCR_CKIO_STBY bit(13)
|
||||
#define STBCR_SAFECKE_IST bit(12)
|
||||
#define STBCR_SLCKE_IST bit(11)
|
||||
#define STBCR_SAFECKE_OST bit(10)
|
||||
#define STBCR_SLCKE_OST bit(9)
|
||||
#define STBCR_SMIAST bit(8)
|
||||
#define STBCR_SLCDST bit(7)
|
||||
#define STBCR_SPC0ST bit(6)
|
||||
#define STBCR_SPC1ST bit(5)
|
||||
#define STBCR_SAFEST bit(4)
|
||||
#define STBCR_STM0ST bit(3)
|
||||
#define STBCR_STM1ST bit(2)
|
||||
#define STBCR_SIRST bit(1)
|
||||
#define STBCR_SURTSD bit(0)
|
||||
|
||||
/* SYSCR bits */
|
||||
#define SYSCR_SCPU_BUS_IGAT bit(13)
|
||||
#define SYSCR_SPTA_IR bit(7)
|
||||
#define SYSCR_SPTA_TM bit(6)
|
||||
#define SYSCR_SPTB_UR bit(5)
|
||||
#define SYSCR_WAIT_CTL_SEL bit(4)
|
||||
#define SYSCR_SMODE1 bit(1)
|
||||
#define SYSCR_SMODE0 bit(0)
|
||||
|
||||
/* SCPUCR bits */
|
||||
#define SCPUCR_SPDSTOF bit(15)
|
||||
#define SCPUCR_SPDSTIG bit(14)
|
||||
#define SCPUCR_SPCSTOF bit(13)
|
||||
#define SCPUCR_SPCSTIG bit(12)
|
||||
#define SCPUCR_SPBSTOF bit(11)
|
||||
#define SCPUCR_SPBSTIG bit(10)
|
||||
#define SCPUCR_SPASTOF bit(9)
|
||||
#define SCPUCR_SPASTIG bit(8)
|
||||
#define SCPUCR_SLCDSTIG bit(7)
|
||||
#define SCPUCR_SCPU_CS56_EP bit(6)
|
||||
#define SCPUCR_SCPU_CMD_EP bit(5)
|
||||
#define SCPUCR_SCPU_ADDR_EP bit(4)
|
||||
#define SCPUCR_SCPDPU bit(3)
|
||||
#define SCPUCR_SCPU_A2319_EP bit(0)
|
||||
|
||||
#endif /* HD64461_STBSYS_H */
|
||||
@ -0,0 +1,97 @@
|
||||
/*
|
||||
* $Id$
|
||||
*
|
||||
* Hitachi HD64461 Timer Registers
|
||||
* Copyright (C) 2004 Marcel Telka
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and/or other materials provided
|
||||
* with the distribution.
|
||||
* * Neither the name of the copyright holders nor the names of their
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Written by Marcel Telka <marcel@telka.sk>, 2004.
|
||||
*
|
||||
* Documentation:
|
||||
* [1] Hitachi, Ltd., "HD64461 Windows(R) CE Intelligent Peripheral Controller",
|
||||
* 1st Edition, July 1998, Order Number: ADE-602-076
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef HD64461_TIMER_H
|
||||
#define HD64461_TIMER_H
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#if LANGUAGE == C
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
/* Timer Registers */
|
||||
|
||||
#if LANGUAGE == C
|
||||
typedef volatile struct TIMER_registers {
|
||||
uint16_t tcvr1;
|
||||
uint16_t tcvr0;
|
||||
uint16_t trvr1;
|
||||
uint16_t trvr0;
|
||||
uint16_t tcr1;
|
||||
uint16_t tcr0;
|
||||
uint16_t tirr;
|
||||
uint16_t ter;
|
||||
} TIMER_registers_t;
|
||||
#endif /* LANGUAGE == C */
|
||||
|
||||
#define TCVR1_OFFSET 0x00
|
||||
#define TCVR0_OFFSET 0x02
|
||||
#define TRVR1_OFFSET 0x04
|
||||
#define TRVR0_OFFSET 0x06
|
||||
#define TCR1_OFFSET 0x08
|
||||
#define TCR0_OFFSET 0x0A
|
||||
#define TIRR_OFFSET 0x0C
|
||||
#define TER_OFFSET 0x0E
|
||||
|
||||
/* TCR1 bits */
|
||||
#define TCR1_ETMO1 bit(3)
|
||||
#define TCR1_PST1_MASK bits(2,1)
|
||||
#define TCR1_PST1(x) bits_val(2,1,x)
|
||||
#define get_TCR1_PST1(x) bits_get(2,1,x)
|
||||
#define TCR1_T1STP bit(0)
|
||||
|
||||
/* TCR0 bits */
|
||||
#define TCR0_ETMO0 bit(3)
|
||||
#define TCR0_PST0_MASK bits(2,1)
|
||||
#define TCR0_PST0(x) bits_val(2,1,x)
|
||||
#define get_TCR0_PST0(x) bits_get(2,1,x)
|
||||
#define TCR0_T0STP bit(0)
|
||||
|
||||
/* TIRR bits */
|
||||
#define TIRR_TMU1R bit(1)
|
||||
#define TIRR_TMU0R bit(0)
|
||||
|
||||
/* TER bits */
|
||||
#define TER_TMU1E bit(1)
|
||||
#define TER_TMU0E bit(0)
|
||||
|
||||
#endif /* HD64461_TIMER_H */
|
||||
Loading…
Reference in New Issue