Added register offsets and bits.

git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@96 b68d4a1b-bc3d-0410-92ed-d4ac073336b7

include/arm/pxa2x0/cm.h

@@ -24,34 +24,68 @@
  * Documentation:
  * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
  *     Developer's Manual", February 2002, Order Number: 278522-001
- * [2] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
- *     Specification Update", May 2002, Order Number: 278534-005
  *
  */
 
 #ifndef	PXA2X0_CM_H
 #define	PXA2X0_CM_H
 
-#ifndef uint32_t
-typedef	unsigned int	uint32_t;
+#include <common.h>
+
+#if LANGUAGE == C
+#include <stdint.h>
 #endif
 
 /* Clocks Manager Registers */
 
 #define	CM_BASE		0x41300000
 
+#if LANGUAGE == C
 typedef volatile struct CM_registers {
 	uint32_t cccr;
 	uint32_t cken;
 	uint32_t oscc;
 } CM_registers;
 
-#ifndef CM_pointer
+#ifdef PXA2X0_UNMAPPED
 #define	CM_pointer	((CM_registers*) CM_BASE)
 #endif
 
 #define	CCCR		CM_pointer->cccr
 #define	CKEN		CM_pointer->cken
 #define	OSCC		CM_pointer->oscc
+#endif /* LANGUAGE == C */
+
+#define	CCCR_OFFSET	0x00
+#define	CKEN_OFFSET	0x04
+#define	OSCC_OFFSET	0x08
+
+/* CCCR bits - see Table 3-20 in [1] */
+
+#define	CCCR_N_MASK	0x380
+#define	CCCR_N(x)	((x << 7) & CCCR_N_MASK)
+#define	CCCR_M_MASK	0x060
+#define	CCCR_M(x)	((x << 5) & CCCR_M_MASK)
+#define	CCCR_L_MASK	0x01F
+#define	CCCR_L(x)	(x & CCCR_L_MASK)
+
+#define	CCCR_N_1_0	CCCR_N(0x2)
+#define	CCCR_N_1_5	CCCR_N(0x3)
+#define	CCCR_N_2_0	CCCR_N(0x4)
+#define	CCCR_N_3_0	CCCR_N(0x6)
+
+#define	CCCR_M_1	CCCR_M(0x1)
+#define	CCCR_M_2	CCCR_M(0x2)
+
+#define	CCCR_L_27	CCCR_L(0x01)
+#define	CCCR_L_32	CCCR_L(0x02)
+#define	CCCR_L_36	CCCR_L(0x03)
+#define	CCCR_L_40	CCCR_L(0x04)
+#define	CCCR_L_45	CCCR_L(0x05)
+
+/* OSCC bits - see Table 3-22 in [1] */
+
+#define	OSCC_OON	bit(1)
+#define	OSCC_OOK	bit(0)
 
-#endif	/* PXA2X0_CM_H */
+#endif /* PXA2X0_CM_H */