diff --git a/include/arm/pxa2x0/pwm.h b/include/arm/pxa2x0/pwm.h
index f14bf7d1..94163ac5 100644
--- a/include/arm/pxa2x0/pwm.h
+++ b/include/arm/pxa2x0/pwm.h
@@ -82,18 +82,18 @@ typedef volatile struct PWM_registers {
 /* PWM_CTRL bits - see Table 4-49 in [1] */
 
 #define	PWM_CTRL_PWM_SD		bit(6)
-#define	PWM_CTRL_PRESCALE_MASK	0x3F
-#define	PWM_CTRL_PRESCALE(x)	(x & PWM_CTRL_PRESCALE_MASK)
+#define	PWM_CTRL_PRESCALE_MASK	bits(5,0)
+#define	PWM_CTRL_PRESCALE(x)	bits_val(5,0,x)
 
 /* PWM_PWDUTY bits - see Table 4-50 in [1] */
 
 #define	PWM_PWDUTY_FDCYCLE	bit(10)
-#define	PWM_PWDUTY_DCYCLE_MASK	0x3FF
-#define	PWM_PWDUTY_DCYCLE(x)	(x & PWM_PWDUTY_DCYCLE_MASK)
+#define	PWM_PWDUTY_DCYCLE_MASK	bits(9,0)
+#define	PWM_PWDUTY_DCYCLE(x)	bits_val(9,0,x)
 
 /* PWM_PERVAL bits - see Table 4-51 in [1] */
 
-#define	PWM_PERVAL_PV_MASK	0x3FF
-#define	PWM_PERVAL_PV(x)	(x & PWM_PERVAL_PV_MASK)
+#define	PWM_PERVAL_PV_MASK	bits(9,0)
+#define	PWM_PERVAL_PV(x)	bits_val(9,0,x)
 
 #endif /* PXA2X0_PWM_H */
diff --git a/include/arm/pxa2x0/rtc.h b/include/arm/pxa2x0/rtc.h
index ed4c4365..be1fb1d6 100644
--- a/include/arm/pxa2x0/rtc.h
+++ b/include/arm/pxa2x0/rtc.h
@@ -75,10 +75,10 @@ typedef volatile struct RTC_registers {
 /* RCNR bits - see Table 4-39 in [1] */
 
 #define	RCNR_LCK		bit(31)
-#define	RCNR_DEL_MASK		0x03FF0000
-#define	RCNR_DEL(x)		((x << 16) & RCNR_DEL_MASK)
-#define	RCNR_CK_DIV_MASK	0x0000FFFF
-#define	RCNR_CK_DIV(x)		(x & RCNR_CK_DIV_MASK)
+#define	RCNR_DEL_MASK		bits(25,16)
+#define	RCNR_DEL(x)		bits_val(25,16,x)
+#define	RCNR_CK_DIV_MASK	bits(15,0)
+#define	RCNR_CK_DIV(x)		bits_val(15,0,x)
 
 /* RTSR bits - see Table 4-42 in [1] */
 
diff --git a/include/arm/pxa2x0/ssp.h b/include/arm/pxa2x0/ssp.h
index 39131f4a..be15d876 100644
--- a/include/arm/pxa2x0/ssp.h
+++ b/include/arm/pxa2x0/ssp.h
@@ -77,20 +77,20 @@ typedef volatile struct SSP_registers {
 /* SSCR0 bits - see Table 8-2 in [1] */
 
 #define	SSCR0_SCR_MASK	bits(15,8)
-#define	SSCR0_SCR(x)	((x << 8) & SSCR0_SCR_MASK)
+#define	SSCR0_SCR(x)	bits_val(15,8,x)
 #define	SSCR0_SSE	bit(7)
 #define	SSCR0_ECS	bit(6)
 #define	SSCR0_FRF_MASK	bits(5,4)
-#define	SSCR0_FRF(x)	((x << 4) & SSCR0_FRF_MASK)
+#define	SSCR0_FRF(x)	bits_val(5,4,x)
 #define	SSCR0_DSS_MASK	bits(3,0)
-#define	SSCR0_DSS(x)	(x & SSCR0_DSS_MASK)
+#define	SSCR0_DSS(x)	bits_val(3,0,x)
 
 /* SSCR1 bits - see Table 8-3 in [1] */
 
 #define	SSCR1_RFT_MASK	bits(13,10)
-#define	SSCR1_RFT(x)	((x << 10) & SSCR1_RFT_MASK)
+#define	SSCR1_RFT(x)	bits_val(13,10,x)
 #define	SSCR1_TFT_MASK	bits(9,6)
-#define	SSCR1_TFT(x)	((x << 6) & SSCR1_TFT_MASK)
+#define	SSCR1_TFT(x)	bits_val(9,6,x)
 #define	SSCR1_MWDS	bit(5)
 #define	SSCR1_SPH	bit(4)
 #define	SSCR1_SPO	bit(3)
@@ -101,9 +101,9 @@ typedef volatile struct SSP_registers {
 /* SSSR bits - see Table 8-6 in [1] */
 
 #define	SSSR_RFL_MASK	bits(15,12)
-#define	SSSR_RFL(x)	((x << 12) & SSSR_RFL_MASK)
+#define	SSSR_RFL(x)	bits_val(15,12,x)
 #define	SSSR_TFL_MASK	bits(11,8)
-#define	SSSR_TFL(x)	((x << 8) & SSSR_TFL_MASK)
+#define	SSSR_TFL(x)	bits_val(11,8,x)
 #define	SSSR_ROR	bit(7)
 #define	SSSR_RFS	bit(6)
 #define	SSSR_TFS	bit(5)