Add support for Atmel's AT32AP7000 (by Gabor Juhos)
git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@1252 b68d4a1b-bc3d-0410-92ed-d4ac073336b7master
Kolja Waschk
17 years ago
parent
c42a892561
commit
8de5a92176
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#
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# $Id$
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#
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# Copyright (c) 2008 Gabor Juhos <juhosg@openwrt.org>
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; either version 2
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# of the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
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# 02111-1307, USA.
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#
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# Documentation:
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# [1] Atmel Corporation, "AT32AP7000 - High Performance, Low Power
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# AVR(R)32 32-Bit Microcontroller", Rev. 32003K-AVR32-10/07
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#
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# bits 31-28 of the Device Identification Register
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# see Table 38-11 in [1]
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0000 at32ap7000 A
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0001 at32ap7000 B
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0010 at32ap7000 C
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@ -0,0 +1,724 @@
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#
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# $Id$
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#
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# Copyright (c) 2008 Gabor Juhos <juhosg@openwrt.org>
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; either version 2
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# of the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
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# 02111-1307, USA.
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#
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# Documentation:
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# [1] Atmel Corporation, "AT32AP7000 - High Performance, Low Power
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# AVR(R)32 32-Bit Microcontroller", Rev. 32003K-AVR32-10/07
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#
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# mandatory data registers
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register BSR 388 # Boundary Scan Register
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register BR 1 # Bypass Register
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# optional data registers
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register DIR 32 # Device Identification Register
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# user-defined registers
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register ARR 5 # AVR Reset Register
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register NAR 34 # Nexus Access Register
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register MWAR 35 # Memory Word Access Register
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register MBAR 34 # Memory Block Access Register
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register CAR 1 # Cancel Access Register
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register SYR 16 # Sync Register
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# see page 909 in [1]
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instruction length 5
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# mandatory instructions
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instruction EXTEST 00000 BSR # see page 914 in [1]
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instruction IDCODE 00001 DIR # see page 914 in [1]
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instruction SAMPLE/PRELOAD 00010 BSR # see page 914 in [1]
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instruction BYPASS 01111 BR # see page 914 in [1]
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# optional instructions
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instruction INTEST 00100 BSR # see page 914 in [1]
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instruction CLAMP 00110 BR # see page 915 in [1]
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# user-defined instructions
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instruction AVR_RESET 01100 ARR # see page 919 in [1]
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instruction NEXUS_ACCESS 10000 NAR # see page 916 in [1]
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instruction MEMORY_WORD_ACCESS 10001 MWAR # see page 917 in [1]
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instruction MEMORY_BLOCK_ACCESS 10011 MBAR # see page 917 in [1]
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instruction CANCEL_ACCESS 10011 CAR # see page 918 in [1]
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instruction SYNC 10111 SYR # see page 919 in [1]
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signal AGNDOSC
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signal AGNDPLL
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signal AGNDUSB
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signal AVDDOSC
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signal AVDDPLL
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signal AVDDUSB
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signal EVTI_N
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signal FSDM
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signal FSDP
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signal GNDCORE_0
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signal GNDCORE_1
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signal GNDCORE_2
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signal GNDCORE_3
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signal GNDCORE_4
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signal GNDCORE_5
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signal GNDIOP_CBL
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signal GNDIOP_CBR
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signal GNDIOP_CUL
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signal GNDIOP_CUR
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signal GNDIOP_0
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signal GNDIOP_1
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signal GNDIOP_2
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signal GNDIOP_3
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signal GNDIOP_4a
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signal GNDIOP_4b
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signal GNDIOP_6a
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signal GNDIOP_6b
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signal GNDIOP_7
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signal GNDIOP_8a
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signal GNDIOP_8b
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signal GNDIOP_9a
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signal GNDIOP_9b
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signal GNDIOP_10
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signal HSDM
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signal HSDP
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signal OSCEN_N
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signal PA00
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signal PA01
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signal PA02
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signal PA03
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signal PA04
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signal PA05
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signal PA06
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signal PA07
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signal PA08
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signal PA09
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signal PA10
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signal PA11
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signal PA12
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signal PA13
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signal PA14
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signal PA15
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signal PA16
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signal PA17
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signal PA18
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signal PA19
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signal PA20
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signal PA21
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signal PA22
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signal PA23
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signal PA24
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signal PA25
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signal PA26
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signal PA27
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signal PA28
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signal PA29
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signal PA30
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signal PA31
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signal PB00
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signal PB01
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signal PB02
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signal PB03
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signal PB04
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signal PB05
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signal PB06
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signal PB07
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signal PB08
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signal PB09
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signal PB10
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signal PB11
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signal PB12
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signal PB13
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signal PB14
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signal PB15
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signal PB16
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signal PB17
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signal PB18
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signal PB19
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signal PB20
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signal PB21
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signal PB22
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signal PB23
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signal PB24
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signal PB25
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signal PB26
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signal PB27
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signal PB28
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signal PB29
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signal PB30
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signal PC00
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signal PC01
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signal PC02
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signal PC03
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signal PC04
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signal PC05
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signal PC06
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signal PC07
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signal PC08
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signal PC09
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signal PC10
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signal PC11
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signal PC12
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signal PC13
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signal PC14
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signal PC15
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signal PC16
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signal PC17
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signal PC18
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signal PC19
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signal PC20
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signal PC21
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signal PC22
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signal PC23
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signal PC24
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signal PC25
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signal PC26
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signal PC27
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signal PC28
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signal PC29
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signal PC30
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signal PC31
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signal PD00
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signal PD01
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signal PD02
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signal PD03
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signal PD04
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signal PD05
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signal PD06
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signal PD07
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signal PD08
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signal PD09
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signal PD10
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signal PD11
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signal PD12
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signal PD13
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signal PD14
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signal PD15
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signal PD16
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signal PD17
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signal PE00
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signal PE01
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signal PE02
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signal PE03
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signal PE04
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signal PE05
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signal PE06
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signal PE07
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signal PE08
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signal PE09
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signal PE10
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signal PE11
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signal PE12
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signal PE13
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signal PE14
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signal PE15
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signal PE16
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signal PE17
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signal PE18
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signal PE19
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signal PE20
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signal PE21
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signal PE22
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signal PE23
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signal PE24
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signal PE25
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signal PE26
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signal PLL0
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signal PLL1
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signal PX00
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signal PX01
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signal PX02
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signal PX03
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signal PX04
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signal PX05
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signal PX06
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signal PX07
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signal PX08
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signal PX09
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signal PX10
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signal PX11
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signal PX12
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signal PX13
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signal PX14
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signal PX15
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signal PX16
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signal PX17
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signal PX18
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signal PX19
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signal PX20
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signal PX21
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signal PX22
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signal PX23
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signal PX24
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signal PX25
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signal PX26
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signal PX27
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signal PX28
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signal PX29
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signal PX30
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signal PX31
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signal PX32
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signal PX33
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signal PX34
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signal PX35
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signal PX36
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signal PX37
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signal PX38
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signal PX39
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signal PX40
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signal PX41
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signal PX42
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signal PX43
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signal PX44
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signal PX45
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signal PX46
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signal PX47
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signal PX48
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signal PX49
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signal PX50
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signal PX51
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signal PX52
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signal PX53
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signal RESET_N
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signal TCK
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signal TDI
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signal TDO
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signal TMS
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signal TRST_N
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signal VBG
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signal VDDCORE_0
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signal VDDCORE_1
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signal VDDCORE_2
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signal VDDCORE_3
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signal VDDCORE_4
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signal VDDIOP_CBL
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signal VDDIOP_CBR
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signal VDDIOP_CUL
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signal VDDIOP_CUR
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signal VDDIOP_0a
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signal VDDIOP_0b
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signal VDDIOP_1
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signal VDDIOP_2a
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signal VDDIOP_2b
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signal VDDIOP_3
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signal VDDIOP_4a
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signal VDDIOP_4b
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signal VDDIOP_6a
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signal VDDIOP_6b
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signal VDDIOP_7
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signal VDDIOP_8a
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signal VDDIOP_8b
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signal VDDIOP_9a
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signal VDDIOP_9b
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signal VDDIOP_10a
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signal VDDIOP_10b
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signal VDDIOP_11
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signal WAKE_N
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signal XIN0
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signal XIN1
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signal XIN32
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signal XOUT0
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signal XOUT1
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# Boundary Scan Register bits
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bit 387 C 1 *
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bit 386 B 1 PD00 387 1 Z
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bit 385 C 1 *
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bit 384 B 1 PD01 385 1 Z
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bit 383 C 1 *
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bit 382 B 1 PD02 383 1 Z
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bit 381 C 1 *
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bit 380 B 1 PE17 381 1 Z
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bit 379 C 1 *
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bit 378 B 1 PE18 379 1 Z
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bit 377 C 1 *
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bit 376 B 1 PX47 377 1 Z
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bit 375 C 1 *
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bit 374 B 1 PX48 375 1 Z
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bit 373 C 1 *
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bit 372 B 1 PX49 373 1 Z
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bit 371 C 1 *
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bit 370 B 1 PX50 371 1 Z
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bit 369 C 1 *
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bit 368 B 1 PX51 369 1 Z
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bit 367 C 1 *
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bit 366 B 1 PX32 367 1 Z
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bit 365 C 1 *
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bit 364 B 1 PX33 365 1 Z
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bit 363 C 1 *
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bit 362 B 1 PX00 363 1 Z
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bit 361 C 1 *
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bit 360 B 1 PX01 361 1 Z
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bit 359 C 1 *
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bit 358 B 1 PX02 359 1 Z
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bit 357 C 1 *
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bit 356 B 1 PX03 357 1 Z
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bit 355 C 1 *
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bit 354 B 1 PX04 355 1 Z
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bit 353 C 1 *
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bit 352 B 1 PX05 353 1 Z
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bit 351 C 1 *
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bit 350 B 1 PD03 351 1 Z
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bit 349 C 1 *
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bit 348 B 1 PD04 349 1 Z
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bit 347 C 1 *
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bit 346 B 1 PD05 347 1 Z
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bit 345 C 1 *
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bit 344 B 1 PD06 345 1 Z
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bit 343 C 1 *
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bit 342 B 1 PD07 343 1 Z
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bit 341 C 1 *
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bit 340 B 1 PD08 341 1 Z
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bit 339 C 1 *
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bit 338 B 1 PD09 339 1 Z
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bit 337 C 1 *
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bit 336 B 1 PA00 337 1 Z
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bit 335 C 1 *
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bit 334 B 1 PA01 335 1 Z
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bit 333 C 1 *
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bit 332 B 1 PA02 333 1 Z
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bit 331 C 1 *
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bit 330 B 1 PA03 331 1 Z
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bit 329 C 1 *
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bit 328 B 1 PA04 329 1 Z
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bit 327 C 1 *
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bit 326 B 1 PA05 327 1 Z
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bit 325 C 1 *
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bit 324 B 1 PB24 325 1 Z
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bit 323 C 1 *
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bit 322 B 1 PB25 323 1 Z
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bit 321 C 1 *
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bit 320 B 1 PA08 321 1 Z
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bit 319 C 1 *
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bit 318 B 1 PA09 319 1 Z
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bit 317 C 1 *
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bit 316 B 1 PA10 317 1 Z
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bit 315 C 1 *
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bit 314 B 1 PA11 315 1 Z
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bit 313 C 1 *
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bit 312 B 1 PA12 313 1 Z
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bit 311 C 1 *
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bit 310 B 1 PA13 311 1 Z
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bit 309 C 1 *
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bit 308 B 1 PA14 309 1 Z
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bit 307 C 1 *
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bit 306 B 1 PA15 307 1 Z
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bit 305 C 1 *
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bit 304 B 1 PA16 305 1 Z
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bit 303 C 1 *
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bit 302 B 1 PA17 303 1 Z
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bit 301 C 1 *
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bit 300 B 1 PA18 301 1 Z
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bit 299 C 1 *
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bit 298 B 1 PA19 299 1 Z
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bit 297 C 1 *
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bit 296 B 1 PA20 297 1 Z
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bit 295 C 1 *
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bit 294 B 1 PA21 295 1 Z
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bit 293 C 1 *
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bit 292 B 1 PA22 293 1 Z
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bit 291 C 1 *
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bit 290 B 1 PD10 291 1 Z
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bit 289 C 1 *
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bit 288 B 1 PA23 289 1 Z
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bit 287 C 1 *
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bit 286 B 1 PA24 287 1 Z
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bit 285 C 1 *
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bit 284 B 1 PD11 285 1 Z
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bit 283 C 1 *
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bit 282 B 1 PD12 283 1 Z
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bit 281 C 1 *
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bit 280 B 1 PD13 281 1 Z
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bit 279 C 1 *
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bit 278 B 1 PD14 279 1 Z
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bit 277 C 1 *
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bit 276 B 1 PD15 277 1 Z
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bit 275 C 1 *
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bit 274 B 1 PD16 275 1 Z
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bit 273 C 1 *
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bit 272 B 1 PD17 273 1 Z
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bit 271 C 1 *
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bit 270 B 1 PA25 271 1 Z
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bit 269 C 1 *
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bit 268 B 1 PA26 269 1 Z
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bit 267 C 1 *
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bit 266 B 1 PA27 267 1 Z
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bit 265 C 1 *
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bit 264 B 1 PA28 265 1 Z
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bit 263 C 1 *
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bit 262 B 1 PA29 263 1 Z
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bit 261 C 1 *
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bit 260 B 1 PA30 261 1 Z
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bit 259 C 1 *
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bit 258 B 1 PA31 259 1 Z
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bit 257 C 1 *
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bit 256 B 1 PB26 257 1 Z
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bit 255 C 1 *
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bit 254 B 1 PB27 255 1 Z
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bit 253 C 1 *
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bit 252 B 1 PB28 253 1 Z
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bit 251 C 1 *
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bit 250 B 1 PX53 251 1 Z
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bit 249 C 1 *
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bit 248 B 1 PX52 249 1 Z
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bit 247 C 1 *
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bit 246 B 1 PX41 247 1 Z
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bit 245 C 1 *
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bit 244 B 1 PE25 245 1 Z
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bit 243 C 1 *
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bit 242 B 1 PE24 243 1 Z
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bit 241 C 1 *
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bit 240 B 1 PE23 241 1 Z
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bit 239 C 1 *
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bit 238 B 1 PE22 239 1 Z
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bit 237 C 1 *
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bit 236 B 1 PE21 237 1 Z
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bit 235 C 1 *
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bit 234 B 1 PE20 235 1 Z
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bit 233 C 1 *
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bit 232 B 1 PE19 233 1 Z
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bit 231 C 1 *
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bit 230 B 1 PX06 231 1 Z
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bit 229 C 1 *
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bit 228 B 1 PX07 229 1 Z
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bit 227 C 1 *
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bit 226 B 1 PX08 227 1 Z
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bit 225 C 1 *
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bit 224 B 1 PX09 225 1 Z
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bit 223 C 1 *
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bit 222 B 1 PX10 223 1 Z
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bit 221 C 1 *
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bit 220 B 1 PX11 221 1 Z
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bit 219 C 1 *
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bit 218 B 1 PB29 219 1 Z
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bit 217 C 1 *
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bit 216 B 1 PB30 217 1 Z
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bit 215 C 1 *
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bit 214 B 1 PX12 215 1 Z
|
||||
bit 213 C 1 *
|
||||
bit 212 B 1 PX13 213 1 Z
|
||||
bit 211 C 1 *
|
||||
bit 210 B 1 PC01 211 1 Z
|
||||
bit 209 C 1 *
|
||||
bit 208 B 1 PC02 209 1 Z
|
||||
bit 207 C 1 *
|
||||
bit 206 B 1 PC03 207 1 Z
|
||||
bit 205 C 1 *
|
||||
bit 204 B 1 PC04 205 1 Z
|
||||
bit 203 C 1 *
|
||||
bit 202 B 1 PC00 203 1 Z
|
||||
bit 201 C 1 *
|
||||
bit 200 B 1 PX14 201 1 Z
|
||||
bit 199 C 1 *
|
||||
bit 198 B 1 PX15 199 1 Z
|
||||
bit 197 C 1 *
|
||||
bit 196 B 1 PX16 197 1 Z
|
||||
bit 195 C 1 *
|
||||
bit 194 B 1 PX17 195 1 Z
|
||||
bit 193 C 1 *
|
||||
bit 192 B 1 PX34 193 1 Z
|
||||
bit 191 C 1 *
|
||||
bit 190 B 1 PX35 191 1 Z
|
||||
bit 189 C 1 *
|
||||
bit 188 B 1 PX36 189 1 Z
|
||||
bit 187 C 1 *
|
||||
bit 186 B 1 PX37 187 1 Z
|
||||
bit 185 C 1 *
|
||||
bit 184 B 1 PX38 185 1 Z
|
||||
bit 183 C 1 *
|
||||
bit 182 B 1 PX18 183 1 Z
|
||||
bit 181 C 1 *
|
||||
bit 180 B 1 PX19 181 1 Z
|
||||
bit 179 C 1 *
|
||||
bit 178 B 1 PX20 179 1 Z
|
||||
bit 177 C 1 *
|
||||
bit 176 B 1 PX21 177 1 Z
|
||||
bit 175 C 1 *
|
||||
bit 174 B 1 PX22 175 1 Z
|
||||
bit 173 C 1 *
|
||||
bit 172 B 1 PX23 173 1 Z
|
||||
bit 171 C 1 *
|
||||
bit 170 B 1 PX24 171 1 Z
|
||||
bit 169 C 1 *
|
||||
bit 168 B 1 PX25 169 1 Z
|
||||
bit 167 C 1 *
|
||||
bit 166 B 1 PX26 167 1 Z
|
||||
bit 165 C 1 *
|
||||
bit 164 B 1 PX27 165 1 Z
|
||||
bit 163 C 1 *
|
||||
bit 162 B 1 PX28 163 1 Z
|
||||
bit 161 C 1 *
|
||||
bit 160 B 1 PX29 161 1 Z
|
||||
bit 159 C 1 *
|
||||
bit 158 B 1 PX30 159 1 Z
|
||||
bit 157 C 1 *
|
||||
bit 156 B 1 PX31 157 1 Z
|
||||
bit 155 C 1 *
|
||||
bit 154 B 1 PC05 155 1 Z
|
||||
bit 153 C 1 *
|
||||
bit 152 B 1 PC06 153 1 Z
|
||||
bit 151 C 1 *
|
||||
bit 150 B 1 PE26 151 1 Z
|
||||
bit 149 C 1 *
|
||||
bit 148 B 1 PX39 149 1 Z
|
||||
bit 147 C 1 *
|
||||
bit 146 B 1 PC07 147 1 Z
|
||||
bit 145 C 1 *
|
||||
bit 144 B 1 PC08 145 1 Z
|
||||
bit 143 C 1 *
|
||||
bit 142 B 1 PC09 143 1 Z
|
||||
bit 141 C 1 *
|
||||
bit 140 B 1 PC10 141 1 Z
|
||||
bit 139 C 1 *
|
||||
bit 138 B 1 PC11 139 1 Z
|
||||
bit 137 C 1 *
|
||||
bit 136 B 1 PC12 137 1 Z
|
||||
bit 135 C 1 *
|
||||
bit 134 B 1 PC13 135 1 Z
|
||||
bit 133 C 1 *
|
||||
bit 132 B 1 PC14 133 1 Z
|
||||
bit 131 C 1 *
|
||||
bit 130 B 1 PC15 131 1 Z
|
||||
bit 129 C 1 *
|
||||
bit 128 B 1 PX40 129 1 Z
|
||||
bit 127 C 1 *
|
||||
bit 126 B 1 PX42 127 1 Z
|
||||
bit 125 C 1 *
|
||||
bit 124 B 1 PX43 125 1 Z
|
||||
bit 123 C 1 *
|
||||
bit 122 B 1 PX44 123 1 Z
|
||||
bit 121 C 1 *
|
||||
bit 120 B 1 PX45 121 1 Z
|
||||
bit 119 C 1 *
|
||||
bit 118 B 1 PX46 119 1 Z
|
||||
bit 117 C 1 *
|
||||
bit 116 B 1 PB00 117 1 Z
|
||||
bit 115 C 1 *
|
||||
bit 114 B 1 PB01 115 1 Z
|
||||
bit 113 C 1 *
|
||||
bit 112 B 1 PB02 113 1 Z
|
||||
bit 111 C 1 *
|
||||
bit 110 B 1 PB03 111 1 Z
|
||||
bit 109 C 1 *
|
||||
bit 108 B 1 PB04 109 1 Z
|
||||
bit 107 C 1 *
|
||||
bit 106 B 1 PB05 107 1 Z
|
||||
bit 105 C 1 *
|
||||
bit 104 B 1 PB06 105 1 Z
|
||||
bit 103 C 1 *
|
||||
bit 102 B 1 PB07 103 1 Z
|
||||
bit 101 C 1 *
|
||||
bit 100 B 1 PB08 101 1 Z
|
||||
bit 99 C 1 *
|
||||
bit 98 B 1 PB09 99 1 Z
|
||||
bit 97 C 1 *
|
||||
bit 96 B 1 PC16 97 1 Z
|
||||
bit 95 C 1 *
|
||||
bit 94 B 1 PC17 95 1 Z
|
||||
bit 93 C 1 *
|
||||
bit 92 B 1 PB10 93 1 Z
|
||||
bit 91 C 1 *
|
||||
bit 90 B 1 PB11 91 1 Z
|
||||
bit 89 C 1 *
|
||||
bit 88 B 1 PB12 89 1 Z
|
||||
bit 87 C 1 *
|
||||
bit 86 B 1 PB13 87 1 Z
|
||||
bit 85 C 1 *
|
||||
bit 84 B 1 PB14 85 1 Z
|
||||
bit 83 C 1 *
|
||||
bit 82 B 1 PB15 83 1 Z
|
||||
bit 81 C 1 *
|
||||
bit 80 B 1 PB16 81 1 Z
|
||||
bit 79 C 1 *
|
||||
bit 78 B 1 PB17 79 1 Z
|
||||
bit 77 C 1 *
|
||||
bit 76 B 1 PB18 77 1 Z
|
||||
bit 75 C 1 *
|
||||
bit 74 B 1 PB19 75 1 Z
|
||||
bit 73 C 1 *
|
||||
bit 72 B 1 PB20 73 1 Z
|
||||
bit 71 C 1 *
|
||||
bit 70 B 1 PB21 71 1 Z
|
||||
bit 69 C 1 *
|
||||
bit 68 B 1 PB22 69 1 Z
|
||||
bit 67 C 1 *
|
||||
bit 66 B 1 PB23 67 1 Z
|
||||
bit 65 C 1 *
|
||||
bit 64 B 1 PC18 65 1 Z
|
||||
bit 63 C 1 *
|
||||
bit 62 B 1 PA06 63 1 Z
|
||||
bit 61 C 1 *
|
||||
bit 60 B 1 PA07 61 1 Z
|
||||
bit 59 C 1 *
|
||||
bit 58 B 1 PC19 59 1 Z
|
||||
bit 57 C 1 *
|
||||
bit 56 B 1 PC20 57 1 Z
|
||||
bit 55 C 1 *
|
||||
bit 54 B 1 PC21 55 1 Z
|
||||
bit 53 C 1 *
|
||||
bit 52 B 1 PC22 53 1 Z
|
||||
bit 51 C 1 *
|
||||
bit 50 B 1 PC23 51 1 Z
|
||||
bit 49 C 1 *
|
||||
bit 48 B 1 PC24 49 1 Z
|
||||
bit 47 C 1 *
|
||||
bit 46 B 1 PC25 47 1 Z
|
||||
bit 45 C 1 *
|
||||
bit 44 B 1 PC26 45 1 Z
|
||||
bit 43 C 1 *
|
||||
bit 42 B 1 PC27 43 1 Z
|
||||
bit 41 C 1 *
|
||||
bit 40 B 1 PC28 41 1 Z
|
||||
bit 39 C 1 *
|
||||
bit 38 B 1 PC29 39 1 Z
|
||||
bit 37 C 1 *
|
||||
bit 36 B 1 PC30 37 1 Z
|
||||
bit 35 C 1 *
|
||||
bit 34 B 1 PC31 35 1 Z
|
||||
bit 33 C 1 *
|
||||
bit 32 B 1 PE00 33 1 Z
|
||||
bit 31 C 1 *
|
||||
bit 30 B 1 PE01 31 1 Z
|
||||
bit 29 C 1 *
|
||||
bit 28 B 1 PE02 29 1 Z
|
||||
bit 27 C 1 *
|
||||
bit 26 B 1 PE03 27 1 Z
|
||||
bit 25 C 1 *
|
||||
bit 24 B 1 PE04 25 1 Z
|
||||
bit 23 C 1 *
|
||||
bit 22 B 1 PE05 23 1 Z
|
||||
bit 21 C 1 *
|
||||
bit 20 B 1 PE06 21 1 Z
|
||||
bit 19 C 1 *
|
||||
bit 18 B 1 PE07 19 1 Z
|
||||
bit 17 C 1 *
|
||||
bit 16 B 1 PE08 17 1 Z
|
||||
bit 15 C 1 *
|
||||
bit 14 B 1 PE09 15 1 Z
|
||||
bit 13 C 1 *
|
||||
bit 12 B 1 PE10 13 1 Z
|
||||
bit 11 C 1 *
|
||||
bit 10 B 1 PE11 11 1 Z
|
||||
bit 9 C 1 *
|
||||
bit 8 B 1 PE12 9 1 Z
|
||||
bit 7 C 1 *
|
||||
bit 6 B 1 PE13 7 1 Z
|
||||
bit 5 C 1 *
|
||||
bit 4 B 1 PE14 5 1 Z
|
||||
bit 3 C 1 *
|
||||
bit 2 B 1 PE15 3 1 Z
|
||||
bit 1 C 1 *
|
||||
bit 0 B 1 PE16 1 1 Z
|
||||
|
||||
endian big
|
||||
@ -0,0 +1,771 @@
|
||||
/*
|
||||
* $Id$
|
||||
*
|
||||
* AVR32 multi-mode bus driver
|
||||
*
|
||||
* Copyright (c) 2008 Gabor Juhos <juhosg@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
|
||||
* 02111-1307, USA.
|
||||
*
|
||||
* Documentation:
|
||||
* [1] Atmel Corporation, "AT32AP7000 - High Performance, Low Power
|
||||
* AVR(R)32 32-Bit Microcontroller", Rev. 32003K-AVR32-10/07
|
||||
*/
|
||||
|
||||
#include "sysdep.h"
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "part.h"
|
||||
#include "bus.h"
|
||||
#include "chain.h"
|
||||
#include "bssignal.h"
|
||||
#include "jtag.h"
|
||||
#include "buses.h"
|
||||
#include "data_register.h"
|
||||
|
||||
void jtag_reset (chain_t * chain);
|
||||
|
||||
typedef struct
|
||||
{
|
||||
chain_t *chain;
|
||||
part_t *part;
|
||||
unsigned int mode;
|
||||
|
||||
unsigned int slave;
|
||||
uint32_t addr_mask;
|
||||
|
||||
uint32_t rwcs_rd;
|
||||
uint32_t rwcs_wr;
|
||||
} bus_params_t;
|
||||
|
||||
#define BUS_MODE_OCD 0
|
||||
#define BUS_MODE_HSBC 1
|
||||
#define BUS_MODE_HSBU 2
|
||||
#define BUS_MODE_x8 3
|
||||
#define BUS_MODE_x16 4
|
||||
#define BUS_MODE_x32 5
|
||||
|
||||
#define BP (( bus_params_t *) bus->params)
|
||||
#define CHAIN (BP->chain)
|
||||
#define PART (BP->part)
|
||||
#define SLAVE (BP->slave)
|
||||
#define MODE (BP->mode)
|
||||
#define ADDR_MASK (BP->addr_mask)
|
||||
#define RWCS_RD (BP->rwcs_rd)
|
||||
#define RWCS_WR (BP->rwcs_wr)
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
#define SAB_SLAVE_OCD 1
|
||||
#define SAB_SLAVE_HSB_CACHED 4
|
||||
#define SAB_SLAVE_HSB_UNCACHED 5
|
||||
|
||||
#define ACCESS_MODE_WRITE 0
|
||||
#define ACCESS_MODE_READ 1
|
||||
|
||||
#define ACCESS_STATUS_OK 0
|
||||
#define ACCESS_STATUS_ERR -1
|
||||
|
||||
#define SAB_OCD_AREA_SIZE UINT64_C(0x1000)
|
||||
#define SAB_OCD_ADDR_MASK 0xfff
|
||||
#define SAB_HSB_AREA_SIZE UINT64_C(0x100000000)
|
||||
#define SAB_HSB_ADDR_MASK 0xffffffff
|
||||
|
||||
/* OCD register addresses */
|
||||
#define OCD_REG_RWCS 0x1c
|
||||
#define OCD_REG_RWA 0x24
|
||||
#define OCD_REG_RWD 0x28
|
||||
|
||||
/* OCD RWCS register definitions */
|
||||
#define OCD_RWCS_AC 0x80000000 /* start access */
|
||||
#define OCD_RWCS_SZ32 0x10000000 /* word access */
|
||||
#define OCD_RWCS_SZ16 0x08000000 /* half-word access */
|
||||
#define OCD_RWCS_SZ8 0x00000000 /* byte access */
|
||||
#define OCD_RWCS_RW 0x40000000 /* access mode 0:read, 1: write */
|
||||
#define OCD_RWCS_CNT_S 2
|
||||
#define OCD_RWCS_ERR 0x00000002 /* last access generated and error */
|
||||
#define OCD_RWCS_DV 0x00000001 /* data is valid */
|
||||
|
||||
/* shorthands */
|
||||
#define OCD_RWCS_READONE (OCD_RWCS_AC | (1 << OCD_RWCS_CNT_S))
|
||||
#define OCD_RWCS_WRITEONE (OCD_RWCS_READONE | OCD_RWCS_RW)
|
||||
#define OCD_RWCS_READ8 (OCD_RWCS_READONE | OCD_RWCS_SZ8)
|
||||
#define OCD_RWCS_WRITE8 (OCD_RWCS_WRITEONE | OCD_RWCS_SZ8)
|
||||
#define OCD_RWCS_READ16 (OCD_RWCS_READONE | OCD_RWCS_SZ16)
|
||||
#define OCD_RWCS_WRITE16 (OCD_RWCS_WRITEONE | OCD_RWCS_SZ16)
|
||||
#define OCD_RWCS_READ32 (OCD_RWCS_READONE | OCD_RWCS_SZ32)
|
||||
#define OCD_RWCS_WRITE32 (OCD_RWCS_WRITEONE | OCD_RWCS_SZ32)
|
||||
|
||||
#define DBG_BASIC 0x0001
|
||||
#define DBG_SHIFT 0x0002
|
||||
#define DBG_TRACE 0x8000
|
||||
|
||||
#define DBG_ALL 0xffff
|
||||
|
||||
#define DBG_LEVEL 0
|
||||
|
||||
#define DBG(t, f, ...) \
|
||||
do { \
|
||||
if (DBG_LEVEL & (t)) \
|
||||
printf( f, ## __VA_ARGS__ ); \
|
||||
} while (0)
|
||||
|
||||
#define TRACE_ENTER() DBG(DBG_TRACE, ">>> %s", __FUNCTION__ )
|
||||
#define TRACE_EXIT() DBG(DBG_TRACE, "<<< %s", __FUNCTION__ )
|
||||
|
||||
#define ERR(f, ...) \
|
||||
printf( _("%s(%d): error, " f), __FILE__, __LINE__, ## __VA_ARGS__ )
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
static inline void
|
||||
register_set_bit (tap_register * tr, unsigned int bitno, unsigned int val)
|
||||
{
|
||||
tr->data[bitno] = (val) ? 1 : 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
register_get_bit (tap_register * tr, unsigned int bitno)
|
||||
{
|
||||
return (tr->data[bitno] & 1) ? 1 : 0;
|
||||
}
|
||||
|
||||
static inline void
|
||||
shift_instr (bus_t * bus, unsigned int bit)
|
||||
{
|
||||
tap_register *r = PART->active_instruction->out;
|
||||
|
||||
do
|
||||
{
|
||||
DBG (DBG_SHIFT, _("%s: instr=%s\n"), __FUNCTION__,
|
||||
register_get_string (PART->active_instruction->value));
|
||||
chain_shift_instructions_mode (CHAIN, 1, 1, EXITMODE_IDLE);
|
||||
DBG (DBG_SHIFT, _("%s: ret=%s\n"), __FUNCTION__, register_get_string (r));
|
||||
/* TODO: add timeout checking */
|
||||
}
|
||||
while (register_get_bit (r, bit));
|
||||
}
|
||||
|
||||
static inline void
|
||||
shift_data (bus_t * bus, unsigned int bit)
|
||||
{
|
||||
data_register *dr = PART->active_instruction->data_register;
|
||||
|
||||
do
|
||||
{
|
||||
DBG (DBG_SHIFT, _("%s: data=%s\n"), __FUNCTION__,
|
||||
register_get_string (dr->in));
|
||||
chain_shift_data_registers (CHAIN, 1);
|
||||
DBG (DBG_SHIFT, _("%s: data out=%s\n"), __FUNCTION__,
|
||||
register_get_string (dr->out));
|
||||
/* TODO: add timeout checking */
|
||||
}
|
||||
while (register_get_bit (dr->out, bit));
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
static void
|
||||
mwa_scan_in_instr (bus_t * bus)
|
||||
{
|
||||
shift_instr (bus, 2);
|
||||
}
|
||||
|
||||
static void
|
||||
mwa_scan_in_addr (bus_t * bus, unsigned int slave, uint32_t addr, int mode)
|
||||
{
|
||||
tap_register *r = PART->active_instruction->data_register->in;
|
||||
int i;
|
||||
|
||||
DBG (DBG_BASIC, _("%s: slave=%01x, addr=%08x, %s\n"),
|
||||
__FUNCTION__, slave, addr,
|
||||
(mode == ACCESS_MODE_READ) ? "READ" : "WRITE");
|
||||
|
||||
/* set slave bits */
|
||||
for (i = 0; i < 4; i++)
|
||||
register_set_bit (r, 31 + i, slave & (1 << i));
|
||||
|
||||
/* set address bits */
|
||||
addr >>= 2;
|
||||
for (i = 0; i < 30; i++)
|
||||
register_set_bit (r, 1 + i, addr & (1 << i));
|
||||
|
||||
/* set access mode */
|
||||
register_set_bit (r, 0, mode);
|
||||
|
||||
shift_data (bus, 32);
|
||||
}
|
||||
|
||||
static void
|
||||
mwa_scan_in_data (bus_t * bus, uint32_t data)
|
||||
{
|
||||
tap_register *r = PART->active_instruction->data_register->in;
|
||||
int i;
|
||||
|
||||
DBG (DBG_BASIC, _("%s: data=%08x\n"), __FUNCTION__, data);
|
||||
|
||||
register_set_bit (r, 0, 0);
|
||||
register_set_bit (r, 1, 0);
|
||||
register_set_bit (r, 2, 0);
|
||||
|
||||
for (i = 0; i < 32; i++)
|
||||
register_set_bit (r, 3 + i, data & (1 << i));
|
||||
|
||||
shift_data (bus, 0);
|
||||
}
|
||||
|
||||
static void
|
||||
mwa_scan_out_data (bus_t * bus, uint32_t * pdata)
|
||||
{
|
||||
tap_register *r = PART->active_instruction->data_register->out;
|
||||
uint32_t data;
|
||||
int i;
|
||||
|
||||
shift_data (bus, 32);
|
||||
|
||||
data = 0;
|
||||
for (i = 0; i < 32; i++)
|
||||
data |= register_get_bit (r, i) << i;
|
||||
|
||||
DBG (DBG_BASIC, _("%s: data=%08x\n"), __FUNCTION__, data);
|
||||
|
||||
*pdata = data;
|
||||
}
|
||||
|
||||
static inline void
|
||||
mwa_read_word (bus_t * bus, unsigned int slave, uint32_t addr,
|
||||
uint32_t * data)
|
||||
{
|
||||
mwa_scan_in_instr (bus);
|
||||
mwa_scan_in_addr (bus, slave, addr, ACCESS_MODE_READ);
|
||||
mwa_scan_out_data (bus, data);
|
||||
}
|
||||
|
||||
static inline void
|
||||
mwa_write_word (bus_t * bus, unsigned int slave, uint32_t addr, uint32_t data)
|
||||
{
|
||||
mwa_scan_in_instr (bus);
|
||||
mwa_scan_in_addr (bus, slave, addr, ACCESS_MODE_WRITE);
|
||||
mwa_scan_in_data (bus, data);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
static void
|
||||
nexus_access_start (bus_t * bus)
|
||||
{
|
||||
shift_instr (bus, 2);
|
||||
}
|
||||
|
||||
static void
|
||||
nexus_access_end (bus_t * bus)
|
||||
{
|
||||
jtag_reset (CHAIN);
|
||||
}
|
||||
|
||||
static void
|
||||
nexus_access_set_addr (bus_t * bus, uint32_t addr, int mode)
|
||||
{
|
||||
tap_register *r = PART->active_instruction->data_register->in;
|
||||
int i;
|
||||
|
||||
DBG (DBG_BASIC, _("%s: addr=%08x, mode=%s\n"), __FUNCTION__, addr,
|
||||
(mode == ACCESS_MODE_READ) ? "READ" : "WRITE");
|
||||
|
||||
register_fill (r, 0);
|
||||
|
||||
/* set address bits */
|
||||
addr >>= 2;
|
||||
for (i = 0; i < 7; i++)
|
||||
register_set_bit (r, 27 + i, addr & (1 << i));
|
||||
|
||||
/* set access mode */
|
||||
register_set_bit (r, 26, mode);
|
||||
|
||||
shift_data (bus, 32);
|
||||
}
|
||||
|
||||
static void
|
||||
nexus_access_read_data (bus_t * bus, uint32_t * pdata)
|
||||
{
|
||||
tap_register *r = PART->active_instruction->data_register->out;
|
||||
uint32_t data;
|
||||
int i;
|
||||
|
||||
shift_data (bus, 32);
|
||||
|
||||
data = 0;
|
||||
for (i = 0; i < 32; i++)
|
||||
data |= register_get_bit (r, i) << i;
|
||||
|
||||
DBG (DBG_BASIC, _("%s: data=%08x\n"), __FUNCTION__, data);
|
||||
|
||||
*pdata = data;
|
||||
}
|
||||
|
||||
static void
|
||||
nexus_access_write_data (bus_t * bus, uint32_t data)
|
||||
{
|
||||
tap_register *r = PART->active_instruction->data_register->in;
|
||||
int i;
|
||||
|
||||
DBG (DBG_BASIC, _("%s: data=%08x\n"), __FUNCTION__, data);
|
||||
|
||||
register_set_bit (r, 0, 0);
|
||||
register_set_bit (r, 1, 0);
|
||||
|
||||
for (i = 0; i < 32; i++)
|
||||
register_set_bit (r, 2 + i, data & (1 << i));
|
||||
|
||||
shift_data (bus, 0);
|
||||
}
|
||||
|
||||
static inline void
|
||||
nexus_reg_read (bus_t * bus, uint32_t reg, uint32_t * data)
|
||||
{
|
||||
nexus_access_set_addr (bus, reg, ACCESS_MODE_READ);
|
||||
nexus_access_read_data (bus, data);
|
||||
}
|
||||
|
||||
static inline void
|
||||
nexus_reg_write (bus_t * bus, uint32_t reg, uint32_t data)
|
||||
{
|
||||
nexus_access_set_addr (bus, reg, ACCESS_MODE_WRITE);
|
||||
nexus_access_write_data (bus, data);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
static void
|
||||
nexus_memacc_set_addr (bus_t * bus, uint32_t addr, uint32_t rwcs)
|
||||
{
|
||||
nexus_reg_write (bus, OCD_REG_RWA, addr);
|
||||
nexus_reg_write (bus, OCD_REG_RWCS, rwcs);
|
||||
}
|
||||
|
||||
static int
|
||||
nexus_memacc_read (bus_t * bus, uint32_t * data)
|
||||
{
|
||||
uint32_t status;
|
||||
int ret;
|
||||
|
||||
do
|
||||
{
|
||||
nexus_reg_read (bus, OCD_REG_RWCS, &status);
|
||||
status &= (OCD_RWCS_ERR | OCD_RWCS_DV);
|
||||
/* TODO: add timeout checking */
|
||||
}
|
||||
while (status == 0);
|
||||
|
||||
DBG (DBG_BASIC, _("%s: read status %08x\n"), __FUNCTION__, status);
|
||||
|
||||
ret = ACCESS_STATUS_OK;
|
||||
switch (status)
|
||||
{
|
||||
case 1:
|
||||
nexus_reg_read (bus, OCD_REG_RWD, data);
|
||||
break;
|
||||
default:
|
||||
ERR ("read failed, status=%d\n", status);
|
||||
*data = 0xffffffff;
|
||||
ret = ACCESS_STATUS_ERR;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
nexus_memacc_write (bus_t * bus, uint32_t addr, uint32_t data, uint32_t rwcs)
|
||||
{
|
||||
uint32_t status;
|
||||
int ret;
|
||||
|
||||
nexus_reg_write (bus, OCD_REG_RWA, addr);
|
||||
nexus_reg_write (bus, OCD_REG_RWCS, rwcs);
|
||||
nexus_reg_write (bus, OCD_REG_RWD, data);
|
||||
|
||||
nexus_reg_read (bus, OCD_REG_RWCS, &status);
|
||||
status &= (OCD_RWCS_ERR | OCD_RWCS_DV);
|
||||
|
||||
DBG (DBG_BASIC, _("%s: status=%08x\n"), __FUNCTION__, status);
|
||||
|
||||
ret = ACCESS_STATUS_OK;
|
||||
if (status)
|
||||
{
|
||||
ERR ("write failed, status=%d\n", status);
|
||||
ret = ACCESS_STATUS_ERR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
static void
|
||||
avr32_bus_printinfo (bus_t * bus)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < CHAIN->parts->len; i++)
|
||||
if (PART == CHAIN->parts->parts[i])
|
||||
break;
|
||||
|
||||
printf (_("AVR32 multi-mode bus driver (JTAG part No. %d)\n"), i);
|
||||
}
|
||||
|
||||
static void
|
||||
avr32_bus_prepare (bus_t * bus)
|
||||
{
|
||||
}
|
||||
|
||||
static void
|
||||
avr32_bus_read_start (bus_t * bus, uint32_t addr)
|
||||
{
|
||||
addr &= ADDR_MASK;
|
||||
|
||||
DBG (DBG_BASIC, _("%s:addr=%08x\n"), __FUNCTION__, addr);
|
||||
|
||||
switch (MODE)
|
||||
{
|
||||
case BUS_MODE_OCD:
|
||||
case BUS_MODE_HSBC:
|
||||
case BUS_MODE_HSBU:
|
||||
part_set_instruction (PART, "MEMORY_WORD_ACCESS");
|
||||
mwa_scan_in_instr (bus);
|
||||
mwa_scan_in_addr (bus, SLAVE, addr, ACCESS_MODE_READ);
|
||||
break;
|
||||
|
||||
case BUS_MODE_x8:
|
||||
case BUS_MODE_x16:
|
||||
case BUS_MODE_x32:
|
||||
part_set_instruction (PART, "NEXUS_ACCESS");
|
||||
nexus_access_start (bus);
|
||||
nexus_memacc_set_addr (bus, addr, RWCS_RD);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
avr32_bus_read_end (bus_t * bus)
|
||||
{
|
||||
uint32_t data;
|
||||
|
||||
switch (MODE)
|
||||
{
|
||||
case BUS_MODE_OCD:
|
||||
case BUS_MODE_HSBC:
|
||||
case BUS_MODE_HSBU:
|
||||
mwa_scan_out_data (bus, &data);
|
||||
break;
|
||||
case BUS_MODE_x8:
|
||||
case BUS_MODE_x16:
|
||||
case BUS_MODE_x32:
|
||||
nexus_memacc_read (bus, &data);
|
||||
nexus_access_end (bus);
|
||||
break;
|
||||
}
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
avr32_bus_read_next (bus_t * bus, uint32_t addr)
|
||||
{
|
||||
uint32_t data;
|
||||
|
||||
addr &= ADDR_MASK;
|
||||
|
||||
switch (MODE)
|
||||
{
|
||||
case BUS_MODE_OCD:
|
||||
case BUS_MODE_HSBC:
|
||||
case BUS_MODE_HSBU:
|
||||
data = avr32_bus_read_end (bus);
|
||||
avr32_bus_read_start (bus, addr);
|
||||
break;
|
||||
case BUS_MODE_x8:
|
||||
case BUS_MODE_x16:
|
||||
case BUS_MODE_x32:
|
||||
nexus_memacc_read (bus, &data);
|
||||
nexus_memacc_set_addr (bus, addr, RWCS_RD);
|
||||
break;
|
||||
}
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
avr32_bus_read (bus_t * bus, uint32_t addr)
|
||||
{
|
||||
uint32_t ret;
|
||||
|
||||
avr32_bus_read_start (bus, addr);
|
||||
ret = avr32_bus_read_end (bus);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void
|
||||
avr32_bus_write (bus_t * bus, uint32_t addr, uint32_t data)
|
||||
{
|
||||
addr &= ADDR_MASK;
|
||||
|
||||
switch (MODE)
|
||||
{
|
||||
case BUS_MODE_OCD:
|
||||
case BUS_MODE_HSBC:
|
||||
case BUS_MODE_HSBU:
|
||||
part_set_instruction (PART, "MEMORY_WORD_ACCESS");
|
||||
mwa_write_word (bus, SLAVE, addr, data);
|
||||
break;
|
||||
case BUS_MODE_x8:
|
||||
case BUS_MODE_x16:
|
||||
case BUS_MODE_x32:
|
||||
part_set_instruction (PART, "NEXUS_ACCESS");
|
||||
nexus_access_start (bus);
|
||||
nexus_memacc_write (bus, addr, data, RWCS_WR);
|
||||
nexus_access_end (bus);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
avr32_bus_area (bus_t * bus, uint32_t addr, bus_area_t * area)
|
||||
{
|
||||
switch (MODE)
|
||||
{
|
||||
case BUS_MODE_HSBC:
|
||||
area->description = "HSB memory space, cached";
|
||||
area->start = UINT32_C (0x00000000);
|
||||
area->length = SAB_HSB_AREA_SIZE;
|
||||
area->width = 32;
|
||||
break;
|
||||
case BUS_MODE_HSBU:
|
||||
area->description = "HSB memory space, uncached";
|
||||
area->start = UINT32_C (0x00000000);
|
||||
area->length = SAB_HSB_AREA_SIZE;
|
||||
area->width = 32;
|
||||
break;
|
||||
case BUS_MODE_x8:
|
||||
area->description = "HSB memory space, uncached";
|
||||
area->start = UINT32_C (0x00000000);
|
||||
area->length = SAB_HSB_AREA_SIZE;
|
||||
area->width = 8;
|
||||
break;
|
||||
case BUS_MODE_x16:
|
||||
area->description = "HSB memory space, uncached";
|
||||
area->start = UINT32_C (0x00000000);
|
||||
area->length = SAB_HSB_AREA_SIZE;
|
||||
area->width = 16;
|
||||
break;
|
||||
case BUS_MODE_x32:
|
||||
area->description = "HSB memory space, uncached";
|
||||
area->start = UINT32_C (0x00000000);
|
||||
area->length = SAB_HSB_AREA_SIZE;
|
||||
area->width = 32;
|
||||
break;
|
||||
case BUS_MODE_OCD:
|
||||
if (addr < SAB_OCD_AREA_SIZE)
|
||||
{
|
||||
area->description = "OCD registers";
|
||||
area->start = UINT32_C (0x00000000);
|
||||
area->length = SAB_OCD_AREA_SIZE;
|
||||
area->width = 32;
|
||||
break;
|
||||
}
|
||||
/* fallthrough */
|
||||
default:
|
||||
area->description = NULL;
|
||||
area->length = UINT64_C (0x100000000);
|
||||
area->width = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
avr32_bus_free (bus_t * bus)
|
||||
{
|
||||
free (bus->params);
|
||||
free (bus);
|
||||
}
|
||||
|
||||
static void
|
||||
avr32_bus_setup (bus_t * bus, chain_t * chain, part_t * part,
|
||||
unsigned int mode)
|
||||
{
|
||||
CHAIN = chain;
|
||||
PART = part;
|
||||
MODE = mode;
|
||||
|
||||
switch (mode)
|
||||
{
|
||||
case BUS_MODE_OCD:
|
||||
SLAVE = SAB_SLAVE_OCD;
|
||||
ADDR_MASK = SAB_OCD_ADDR_MASK & ~(3);
|
||||
break;
|
||||
|
||||
case BUS_MODE_HSBC:
|
||||
SLAVE = SAB_SLAVE_HSB_CACHED;
|
||||
ADDR_MASK = SAB_HSB_ADDR_MASK & ~(3);
|
||||
break;
|
||||
|
||||
case BUS_MODE_HSBU:
|
||||
SLAVE = SAB_SLAVE_HSB_UNCACHED;
|
||||
ADDR_MASK = SAB_HSB_ADDR_MASK & ~(3);
|
||||
break;
|
||||
|
||||
case BUS_MODE_x8:
|
||||
ADDR_MASK = SAB_HSB_ADDR_MASK;
|
||||
RWCS_RD = OCD_RWCS_READ8;
|
||||
RWCS_WR = OCD_RWCS_WRITE8;
|
||||
break;
|
||||
|
||||
case BUS_MODE_x16:
|
||||
ADDR_MASK = SAB_HSB_ADDR_MASK & ~(1);
|
||||
RWCS_RD = OCD_RWCS_READ16;
|
||||
RWCS_WR = OCD_RWCS_WRITE16;
|
||||
break;
|
||||
|
||||
case BUS_MODE_x32:
|
||||
ADDR_MASK = SAB_HSB_ADDR_MASK & ~(3);
|
||||
RWCS_RD = OCD_RWCS_READ32;
|
||||
RWCS_WR = OCD_RWCS_WRITE32;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
check_instruction (part_t * part, const char *instr)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = (part_find_instruction (part, instr) == NULL);
|
||||
if (ret)
|
||||
ERR ("instruction %s not found\n", instr);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static bus_t *
|
||||
avr32_bus_new (chain_t * chain, char *cmd_params[])
|
||||
{
|
||||
bus_t *bus;
|
||||
part_t *part;
|
||||
char *param;
|
||||
unsigned int mode;
|
||||
|
||||
if (!chain || !chain->parts ||
|
||||
chain->parts->len <= chain->active_part || chain->active_part < 0)
|
||||
return NULL;
|
||||
|
||||
part = chain->parts->parts[chain->active_part];
|
||||
|
||||
param = cmd_params[2];
|
||||
if (!param)
|
||||
{
|
||||
ERR ("no bus mode specified\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (!strcasecmp ("OCD", param))
|
||||
{
|
||||
mode = BUS_MODE_OCD;
|
||||
}
|
||||
else if (!strcasecmp ("HSBC", param))
|
||||
{
|
||||
mode = BUS_MODE_HSBC;
|
||||
}
|
||||
else if (!strcasecmp ("HSBU", param))
|
||||
{
|
||||
mode = BUS_MODE_HSBU;
|
||||
}
|
||||
else if (!strcasecmp ("x8", param))
|
||||
{
|
||||
mode = BUS_MODE_x8;
|
||||
}
|
||||
else if (!strcasecmp ("x16", param))
|
||||
{
|
||||
mode = BUS_MODE_x16;
|
||||
}
|
||||
else if (!strcasecmp ("x32", param))
|
||||
{
|
||||
mode = BUS_MODE_x32;
|
||||
}
|
||||
else
|
||||
{
|
||||
ERR ("invalid bus mode: %s\n", param);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
switch (mode)
|
||||
{
|
||||
case BUS_MODE_OCD:
|
||||
case BUS_MODE_HSBC:
|
||||
case BUS_MODE_HSBU:
|
||||
if (check_instruction (part, "MEMORY_WORD_ACCESS"))
|
||||
return NULL;
|
||||
break;
|
||||
case BUS_MODE_x8:
|
||||
case BUS_MODE_x16:
|
||||
case BUS_MODE_x32:
|
||||
if (check_instruction (part, "NEXUS_ACCESS"))
|
||||
return NULL;
|
||||
break;
|
||||
}
|
||||
|
||||
bus = malloc (sizeof (bus_t));
|
||||
if (!bus)
|
||||
return NULL;
|
||||
|
||||
bus->driver = &avr32_bus_driver;
|
||||
bus->params = malloc (sizeof (bus_params_t));
|
||||
if (!bus->params)
|
||||
{
|
||||
free (bus);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
avr32_bus_setup (bus, chain, part, mode);
|
||||
|
||||
return bus;
|
||||
}
|
||||
|
||||
const bus_driver_t avr32_bus_driver = {
|
||||
"avr32",
|
||||
N_("Atmel AVR32 multi-mode bus driver, requires <mode> parameter\n"
|
||||
" valid <mode> parameters:\n"
|
||||
" x8: 8 bit bus for the uncached HSB area, via OCD registers\n"
|
||||
" x16: 16 bit bus for the uncached HSB area, via OCD registers\n"
|
||||
" x32: 32 bit bus for the uncached HSB area, via OCD registers\n"
|
||||
" OCD : 32 bit bus for the OCD registers\n"
|
||||
" HSBC: 32 bit bus for the cached HSB area, via SAB\n"
|
||||
" HSBU: 32 bit bus for the uncached HSB area, via SAB"),
|
||||
avr32_bus_new,
|
||||
avr32_bus_free,
|
||||
avr32_bus_printinfo,
|
||||
avr32_bus_prepare,
|
||||
avr32_bus_area,
|
||||
avr32_bus_read_start,
|
||||
avr32_bus_read_next,
|
||||
avr32_bus_read_end,
|
||||
avr32_bus_read,
|
||||
avr32_bus_write
|
||||
};
|
||||
Loading…
Reference in New Issue