unify all Blackfin registers/instructions in one place

git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@1883 b68d4a1b-bc3d-0410-92ed-d4ac073336b7
master
Mike Frysinger 14 years ago
parent 612f8c86c6
commit 938c7f2971

@ -9,7 +9,7 @@
* configure.ac: Check for getline().
* src/global/parse.c (urj_parse_stream): Get rid of line length limitations
by using getline when it is available.
by using getline when it is available.
* src/part/part.c: Fix indentation style.
@ -19,6 +19,12 @@
* src/cmd/cmd_shell.c: Clean up help output.
* data/analog/bfin/bfin: Unify all common Blackfin registers/instructions.
* data/analog/bf506/bf506, data/analog/bf518/bf518, data/analog/bf527/bf527,
data/analog/bf533/bf533, data/analog/bf537/bf537, data/analog/bf538/bf538,
data/analog/bf548/bf548, data/analog/bf561/bf561, data/analog/bf592/bf592:
Drop duplicated Blackfin settings and include analog/bfin/bfin.
2011-02-17 Mike Frysinger <vapier@gentoo.org>
* data/analog/bf548/STEPPINGS: Add bf54x-0.4 support.

@ -80,29 +80,7 @@ signal VDDINT4
signal VDDINT5
register BSR 119
register BR 1
register DIR 32
register DBGSTAT 16
register DBGCTL 16
register EMUIR 32
register EMUIR64 64
register EMUDAT 32
register EMUDAT40 40
register EMUPC 32
instruction length 5
instruction BYPASS 11111 BR
instruction EXTEST 00000 BSR
instruction SAMPLE/PRELOAD 10000 BSR
instruction IDCODE 00010 DIR
instruction DBGSTAT_SCAN 01100 DBGSTAT
instruction DBGCTL_SCAN 00100 DBGCTL
instruction EMUIR_SCAN 01000 EMUIR
instruction EMUIR64_SCAN 01000 EMUIR64
instruction EMUDAT_SCAN 10100 EMUDAT
instruction EMUDAT40_SCAN 10100 EMUDAT40
instruction EMUPC_SCAN 11110 EMUPC
include analog/bfin/bfin
bit 118 O 1 *
bit 117 O 1 SCL 117 1 Z

@ -177,29 +177,7 @@ signal VDDMEM6
signal VDDMEM7
register BSR 200
register BR 1
register DIR 32
register DBGSTAT 16
register DBGCTL 16
register EMUIR 32
register EMUIR64 64
register EMUDAT 32
register EMUDAT40 40
register EMUPC 32
instruction length 5
instruction BYPASS 11111 BR
instruction EXTEST 00000 BSR
instruction SAMPLE/PRELOAD 10000 BSR
instruction IDCODE 00010 DIR
instruction DBGSTAT_SCAN 01100 DBGSTAT
instruction DBGCTL_SCAN 00100 DBGCTL
instruction EMUIR_SCAN 01000 EMUIR
instruction EMUIR64_SCAN 01000 EMUIR64
instruction EMUDAT_SCAN 10100 EMUDAT
instruction EMUDAT40_SCAN 10100 EMUDAT40
instruction EMUPC_SCAN 11110 EMUPC
include analog/bfin/bfin
bit 199 C 0 *
bit 198 O 1 ADDR13 7 0 Z

@ -288,29 +288,7 @@ signal AGND0
signal AGND1
register BSR 233
register BR 1
register DIR 32
register DBGSTAT 16
register DBGCTL 16
register EMUIR 32
register EMUIR64 64
register EMUDAT 32
register EMUDAT40 40
register EMUPC 32
instruction length 5
instruction EXTEST 00000 BSR
instruction SAMPLE/PRELOAD 10000 BSR
instruction IDCODE 00010 DIR
instruction BYPASS 11111 BR
instruction DBGSTAT_SCAN 01100 DBGSTAT
instruction DBGCTL_SCAN 00100 DBGCTL
instruction EMUIR_SCAN 01000 EMUIR
instruction EMUIR64_SCAN 01000 EMUIR64
instruction EMUDAT_SCAN 10100 EMUDAT
instruction EMUDAT40_SCAN 10100 EMUDAT40
instruction EMUPC_SCAN 11110 EMUPC
include analog/bfin/bfin
bit 232 C 0 *
bit 231 O 1 ADDR14 8 0 Z

@ -159,29 +159,7 @@ signal XTAL
signal VROUT0
register BSR 197
register BR 1
register DIR 32
register DBGSTAT 16
register DBGCTL 16
register EMUIR 32
register EMUIR64 64
register EMUDAT 32
register EMUDAT40 40
register EMUPC 32
instruction length 5
instruction EXTEST 00000 BSR
instruction SAMPLE/PRELOAD 10000 BSR
instruction IDCODE 00010 DIR
instruction BYPASS 11111 BR
instruction DBGSTAT_SCAN 01100 DBGSTAT
instruction DBGCTL_SCAN 00100 DBGCTL
instruction EMUIR_SCAN 01000 EMUIR
instruction EMUIR64_SCAN 01000 EMUIR64
instruction EMUDAT_SCAN 10100 EMUDAT
instruction EMUDAT40_SCAN 10100 EMUDAT40
instruction EMUPC_SCAN 11110 EMUPC
include analog/bfin/bfin
bit 196 C 0 *
bit 195 O 1 DATA0 196 0 Z

@ -181,29 +181,7 @@ signal CLKBUF
signal VROUT0
register BSR 261
register BR 1
register DIR 32
register DBGSTAT 16
register DBGCTL 16
register EMUIR 32
register EMUIR64 64
register EMUDAT 32
register EMUDAT40 40
register EMUPC 32
instruction length 5
instruction BYPASS 11111 BR
instruction EXTEST 00000 BSR
instruction SAMPLE/PRELOAD 10000 BSR
instruction IDCODE 00010 DIR
instruction DBGSTAT_SCAN 01100 DBGSTAT
instruction DBGCTL_SCAN 00100 DBGCTL
instruction EMUIR_SCAN 01000 EMUIR
instruction EMUIR64_SCAN 01000 EMUIR64
instruction EMUDAT_SCAN 10100 EMUDAT
instruction EMUDAT40_SCAN 10100 EMUDAT40
instruction EMUPC_SCAN 11110 EMUPC
include analog/bfin/bfin
bit 260 C 0 *
bit 259 O 1 DATA0 260 0 Z

@ -314,29 +314,7 @@ signal VROUT0
signal VROUT1
register BSR 325
register BR 1
register DIR 32
register DBGSTAT 16
register DBGCTL 16
register EMUIR 32
register EMUIR64 64
register EMUDAT 32
register EMUDAT40 40
register EMUPC 32
instruction length 5
instruction BYPASS 11111 BR
instruction EXTEST 00000 BSR
instruction SAMPLE/PRELOAD 10000 BSR
instruction IDCODE 00010 DIR
instruction DBGSTAT_SCAN 01100 DBGSTAT
instruction DBGCTL_SCAN 00100 DBGCTL
instruction EMUIR_SCAN 01000 EMUIR
instruction EMUIR64_SCAN 01000 EMUIR64
instruction EMUDAT_SCAN 10100 EMUDAT
instruction EMUDAT40_SCAN 10100 EMUDAT40
instruction EMUPC_SCAN 11110 EMUPC
include analog/bfin/bfin
bit 324 C 0 *
bit 323 O 1 DATA0 324 0 Z

@ -420,29 +420,7 @@ signal USB_VREF
signal USB_XI
register BSR 636
register BR 1
register DIR 32
register DBGSTAT 16
register DBGCTL 16
register EMUIR 32
register EMUIR64 64
register EMUDAT 32
register EMUDAT40 40
register EMUPC 32
instruction length 5
instruction EXTEST 00000 BSR
instruction SAMPLE/PRELOAD 10000 BSR
instruction IDCODE 00010 DIR
instruction BYPASS 11111 BR
instruction DBGSTAT_SCAN 01100 DBGSTAT
instruction DBGCTL_SCAN 00100 DBGCTL
instruction EMUIR_SCAN 01000 EMUIR
instruction EMUIR64_SCAN 01000 EMUIR64
instruction EMUDAT_SCAN 10100 EMUDAT
instruction EMUDAT40_SCAN 10100 EMUDAT40
instruction EMUPC_SCAN 11110 EMUPC
include analog/bfin/bfin
bit 635 C 0 *
bit 634 O 1 PA10 635 0 Z

@ -233,29 +233,7 @@ signal GND_EXT17
signal GND_EXT18
register BSR 355
register BR 1
register DIR 32
register DBGSTAT 16
register DBGCTL 16
register EMUIR 32
register EMUIR64 64
register EMUDAT 32
register EMUDAT40 40
register EMUPC 32
instruction length 5
instruction BYPASS 11111 BR
instruction EXTEST 00000 BSR
instruction SAMPLE/PRELOAD 10000 BSR
instruction IDCODE 00010 DIR
instruction DBGSTAT_SCAN 01100 DBGSTAT
instruction DBGCTL_SCAN 00100 DBGCTL
instruction EMUIR_SCAN 01000 EMUIR
instruction EMUIR64_SCAN 01000 EMUIR64
instruction EMUDAT_SCAN 10100 EMUDAT
instruction EMUDAT40_SCAN 10100 EMUDAT40
instruction EMUPC_SCAN 11110 EMUPC
include analog/bfin/bfin
bit 354 I 1 TEST
bit 353 I 1 BMODE1

@ -64,29 +64,7 @@ signal PF3
signal PF2
register BSR 126
register BR 1
register DIR 32
register DBGSTAT 16
register DBGCTL 16
register EMUIR 32
register EMUIR64 64
register EMUDAT 32
register EMUDAT40 40
register EMUPC 32
instruction length 5
instruction BYPASS 11111 BR
instruction EXTEST 00000 BSR
instruction SAMPLE/PRELOAD 10000 BSR
instruction IDCODE 00010 DIR
instruction DBGSTAT_SCAN 01100 DBGSTAT
instruction DBGCTL_SCAN 00100 DBGCTL
instruction EMUIR_SCAN 01000 EMUIR
instruction EMUIR64_SCAN 01000 EMUIR64
instruction EMUDAT_SCAN 10100 EMUDAT
instruction EMUDAT40_SCAN 10100 EMUDAT40
instruction EMUPC_SCAN 11110 EMUPC
include analog/bfin/bfin
bit 0 I ? BMODE2
bit 1 O ? *

@ -0,0 +1,25 @@
# Common Blackfin registers/instructions
register BR 1
register DIR 32
register DBGSTAT 16
register DBGCTL 16
register EMUIR 32
register EMUIR64 64
register EMUDAT 32
register EMUDAT40 40
register EMUPC 32
instruction length 5
instruction BYPASS 11111 BR
instruction EXTEST 00000 BSR
instruction SAMPLE/PRELOAD 10000 BSR
instruction IDCODE 00010 DIR
instruction DBGSTAT_SCAN 01100 DBGSTAT
instruction DBGCTL_SCAN 00100 DBGCTL
instruction EMUIR_SCAN 01000 EMUIR
instruction EMUIR64_SCAN 01000 EMUIR64
instruction EMUDAT_SCAN 10100 EMUDAT
instruction EMUDAT40_SCAN 10100 EMUDAT40
instruction EMUPC_SCAN 11110 EMUPC
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