From 9aec74699f5e9fc5571a7b76637dddc48f4eebc5 Mon Sep 17 00:00:00 2001 From: Marcel Telka Date: Fri, 11 Oct 2002 06:26:02 +0000 Subject: [PATCH] Added register offsets and bits, removed SSITR register. git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@161 b68d4a1b-bc3d-0410-92ed-d4ac073336b7 --- include/arm/pxa2x0/ssp.h | 58 +++++++++++++++++++++++++++++++++++----- 1 file changed, 52 insertions(+), 6 deletions(-) diff --git a/include/arm/pxa2x0/ssp.h b/include/arm/pxa2x0/ssp.h index 041c2349..39131f4a 100644 --- a/include/arm/pxa2x0/ssp.h +++ b/include/arm/pxa2x0/ssp.h @@ -39,30 +39,76 @@ #ifndef PXA2X0_SSP_H #define PXA2X0_SSP_H -#ifndef uint32_t -typedef unsigned int uint32_t; +#include + +#if LANGUAGE == C +#include #endif /* SSP Registers */ #define SSP_BASE 0x41000000 +#if LANGUAGE == C +/* see Table 8-7 in [1] */ typedef volatile struct SSP_registers { uint32_t sscr0; uint32_t sscr1; uint32_t sssr; - uint32_t ssitr; + uint32_t __reserved; uint32_t ssdr; } SSP_registers; -#ifndef SSP_pointer +#ifdef PXA2X0_UNMAPPED #define SSP_pointer ((SSP_registers*) SSP_BASE) #endif #define SSCR0 SSP_pointer->sscr0 #define SSCR1 SSP_pointer->sscr1 #define SSSR SSP_pointer->sssr -#define SSITR SSP_pointer->ssitr #define SSDR SSP_pointer->ssdr +#endif /* LANGUAGE == C */ + +#define SSCR0_OFFSET 0x00 +#define SSCR1_OFFSET 0x04 +#define SSSR_OFFSET 0x08 +#define SSDR_OFFSET 0x10 + +/* SSCR0 bits - see Table 8-2 in [1] */ + +#define SSCR0_SCR_MASK bits(15,8) +#define SSCR0_SCR(x) ((x << 8) & SSCR0_SCR_MASK) +#define SSCR0_SSE bit(7) +#define SSCR0_ECS bit(6) +#define SSCR0_FRF_MASK bits(5,4) +#define SSCR0_FRF(x) ((x << 4) & SSCR0_FRF_MASK) +#define SSCR0_DSS_MASK bits(3,0) +#define SSCR0_DSS(x) (x & SSCR0_DSS_MASK) + +/* SSCR1 bits - see Table 8-3 in [1] */ + +#define SSCR1_RFT_MASK bits(13,10) +#define SSCR1_RFT(x) ((x << 10) & SSCR1_RFT_MASK) +#define SSCR1_TFT_MASK bits(9,6) +#define SSCR1_TFT(x) ((x << 6) & SSCR1_TFT_MASK) +#define SSCR1_MWDS bit(5) +#define SSCR1_SPH bit(4) +#define SSCR1_SPO bit(3) +#define SSCR1_LBM bit(2) +#define SSCR1_TIE bit(1) +#define SSCR1_RIE bit(0) + +/* SSSR bits - see Table 8-6 in [1] */ + +#define SSSR_RFL_MASK bits(15,12) +#define SSSR_RFL(x) ((x << 12) & SSSR_RFL_MASK) +#define SSSR_TFL_MASK bits(11,8) +#define SSSR_TFL(x) ((x << 8) & SSSR_TFL_MASK) +#define SSSR_ROR bit(7) +#define SSSR_RFS bit(6) +#define SSSR_TFS bit(5) +#define SSSR_BSY bit(4) +#define SSSR_RNE bit(3) +#define SSSR_TNF bit(2) -#endif /* PXA2X0_SSP_H */ +#endif /* PXA2X0_SSP_H */