[ 1873220 ] Merge libbrux into src, and inclow into include. Doesn't compile yet!
git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@925 b68d4a1b-bc3d-0410-92ed-d4ac073336b7master
Kolja Waschk
17 years ago
parent
9395544be5
commit
a3547df4c0
@ -0,0 +1,63 @@
|
||||
/*
|
||||
* $Id$
|
||||
*
|
||||
* Common header file
|
||||
* Copyright (C) 2002 ETC s.r.o.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the ETC s.r.o. nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Written by Marcel Telka <marcel@telka.sk>, 2002.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef COMMON_H
|
||||
#define COMMON_H
|
||||
|
||||
#ifndef LANGUAGE
|
||||
# ifdef __ASSEMBLY__
|
||||
# define LANGUAGE ASM
|
||||
# else
|
||||
# define LANGUAGE C
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifndef ASM
|
||||
#define ASM 0
|
||||
#endif
|
||||
|
||||
#ifndef C
|
||||
#define C 1
|
||||
#endif
|
||||
|
||||
#define MAX_BITS_ABS_VAL 1024
|
||||
#define BITS_ABS(a) (((((a) + MAX_BITS_ABS_VAL) / MAX_BITS_ABS_VAL) * 2 - 1) * (a))
|
||||
#define BITS_MIN(a,b) (((a) + (b) - BITS_ABS((a) - (b))) / 2)
|
||||
|
||||
#define bit(b) (1 << (b))
|
||||
#define bits(b1,b2) (((2 << BITS_ABS((b1) - (b2))) - 1) << BITS_MIN(b1,b2))
|
||||
#define bits_val(b1,b2,v) (((v) << BITS_MIN(b1,b2)) & bits(b1,b2))
|
||||
#define bits_get(b1,b2,v) (((v) & bits(b1,b2)) >> BITS_MIN(b1,b2))
|
||||
|
||||
#endif /* COMMON_H */
|
||||
@ -0,0 +1,83 @@
|
||||
/*
|
||||
* $Id$
|
||||
*
|
||||
* Bus driver interface
|
||||
* Copyright (C) 2002, 2003 ETC s.r.o.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the ETC s.r.o. nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef BRUX_BUS_H
|
||||
#define BRUX_BUS_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
const char *description;
|
||||
uint32_t start;
|
||||
uint64_t length;
|
||||
unsigned int width;
|
||||
} bus_area_t;
|
||||
|
||||
typedef struct bus bus_t;
|
||||
|
||||
typedef struct bus_driver {
|
||||
const char *name;
|
||||
const char *description;
|
||||
bus_t *(*new_bus)( char *cmd_params[] );
|
||||
void (*free_bus)( bus_t *bus );
|
||||
void (*printinfo)( bus_t *bus );
|
||||
void (*prepare)( bus_t *bus );
|
||||
int (*area)( bus_t *bus, uint32_t adr, bus_area_t *area );
|
||||
void (*read_start)( bus_t *bus, uint32_t adr );
|
||||
uint32_t (*read_next)( bus_t *bus, uint32_t adr );
|
||||
uint32_t (*read_end)( bus_t *bus );
|
||||
uint32_t (*read)( bus_t *bus, uint32_t adr );
|
||||
void (*write)( bus_t *bus, uint32_t adr, uint32_t data );
|
||||
int (*init) (bus_t *bus);
|
||||
} bus_driver_t;
|
||||
|
||||
struct bus {
|
||||
void *params;
|
||||
const bus_driver_t *driver;
|
||||
};
|
||||
|
||||
extern bus_t *bus;
|
||||
|
||||
#define bus_printinfo(bus) bus->driver->printinfo(bus)
|
||||
#define bus_prepare(bus) bus->driver->prepare(bus)
|
||||
#define bus_area(bus,adr,a) bus->driver->area(bus,adr,a)
|
||||
#define bus_read_start(bus,adr) bus->driver->read_start(bus,adr)
|
||||
#define bus_read_next(bus,adr) bus->driver->read_next(bus,adr)
|
||||
#define bus_read_end(bus) bus->driver->read_end(bus)
|
||||
#define bus_read(bus,adr) bus->driver->read(bus,adr)
|
||||
#define bus_write(bus,adr,data) bus->driver->write(bus,adr,data)
|
||||
#define bus_free(bus) bus->driver->free_bus(bus)
|
||||
#define bus_init(bus) bus->driver->init(bus)
|
||||
|
||||
#endif /* BRUX_BUS_H */
|
||||
@ -0,0 +1,435 @@
|
||||
/*
|
||||
* $Id$
|
||||
*
|
||||
* XScale PXA26x/PXA255/PXA250/PXA210 Memory Controller Registers
|
||||
* Copyright (C) 2002, 2003 ETC s.r.o.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the ETC s.r.o. nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
|
||||
*
|
||||
* Documentation:
|
||||
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
|
||||
* Developer's Manual", February 2002, Order Number: 278522-001
|
||||
* [2] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
|
||||
* Specification Update", February 2003, Order Number: 278534-012
|
||||
* [3] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
|
||||
* March 2003, Order Number: 278638-002
|
||||
* [4] Intel Corporation, "Intel PXA255 Processor Developer's Manual"
|
||||
* March 2003, Order Number: 278693-001
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PXA2X0_MC_H
|
||||
#define PXA2X0_MC_H
|
||||
|
||||
#include <openwince.h>
|
||||
|
||||
#if LANGUAGE == C
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255)
|
||||
#define PXA2X0_NOPXA255
|
||||
#endif
|
||||
|
||||
#if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260)
|
||||
#define PXA2X0_NOPXA260
|
||||
#endif
|
||||
|
||||
/* Memory Controller Registers */
|
||||
|
||||
#define MC_BASE 0x48000000
|
||||
|
||||
#if LANGUAGE == C
|
||||
typedef volatile struct MC_registers {
|
||||
uint32_t mdcnfg;
|
||||
uint32_t mdrefr;
|
||||
uint32_t msc0;
|
||||
uint32_t msc1;
|
||||
uint32_t msc2;
|
||||
uint32_t mecr;
|
||||
uint32_t __reserved1;
|
||||
uint32_t sxcnfg;
|
||||
uint32_t __reserved2;
|
||||
uint32_t sxmrs;
|
||||
uint32_t mcmem0;
|
||||
uint32_t mcmem1;
|
||||
uint32_t mcatt0;
|
||||
uint32_t mcatt1;
|
||||
uint32_t mcio0;
|
||||
uint32_t mcio1;
|
||||
uint32_t mdmrs;
|
||||
uint32_t boot_def;
|
||||
#if !defined(PXA2X0_NOPXA255)
|
||||
uint32_t __reserved3[4];
|
||||
uint32_t mdmrslp;
|
||||
#endif /* PXA255 and above only */
|
||||
#if !defined(PXA2X0_NOPXA260)
|
||||
uint32_t __reserved4[2];
|
||||
uint32_t sa1111cr;
|
||||
#endif /* PXA260 and above only */
|
||||
} MC_registers_t;
|
||||
|
||||
#ifdef PXA2X0_UNMAPPED
|
||||
#define MC_pointer ((MC_registers_t*) MC_BASE)
|
||||
#endif
|
||||
|
||||
#define MDCNFG MC_pointer->mdcnfg
|
||||
#define MDREFR MC_pointer->mdrefr
|
||||
#define MSC0 MC_pointer->msc0
|
||||
#define MSC1 MC_pointer->msc1
|
||||
#define MSC2 MC_pointer->msc2
|
||||
#define MECR MC_pointer->mecr
|
||||
#define SXCNFG MC_pointer->sxcnfg
|
||||
#define SXMRS MC_pointer->sxmrs
|
||||
#define MCMEM0 MC_pointer->mcmem0
|
||||
#define MCMEM1 MC_pointer->mcmem1
|
||||
#define MCATT0 MC_pointer->mcatt0
|
||||
#define MCATT1 MC_pointer->mcatt1
|
||||
#define MCIO0 MC_pointer->mcio0
|
||||
#define MCIO1 MC_pointer->mcio1
|
||||
#define MDMRS MC_pointer->mdmrs
|
||||
#define BOOT_DEF MC_pointer->boot_def
|
||||
#if !defined(PXA2X0_NOPXA255)
|
||||
#define MDMRSLP MC_pointer->mdmrslp
|
||||
#endif /* PXA255 and above only */
|
||||
#if !defined(PXA2X0_NOPXA260)
|
||||
#define SA1111CR MC_pointer->sa1111cr
|
||||
#endif /* PXA260 and above only */
|
||||
#endif /* LANGUAGE == C */
|
||||
|
||||
#define MDCNFG_OFFSET 0x00
|
||||
#define MDREFR_OFFSET 0x04
|
||||
#define MSC0_OFFSET 0x08
|
||||
#define MSC1_OFFSET 0x0C
|
||||
#define MSC2_OFFSET 0x10
|
||||
#define MECR_OFFSET 0x14
|
||||
#define SXCNFG_OFFSET 0x1C
|
||||
#define SXMRS_OFFSET 0x24
|
||||
#define MCMEM0_OFFSET 0x28
|
||||
#define MCMEM1_OFFSET 0x2C
|
||||
#define MCATT0_OFFSET 0x30
|
||||
#define MCATT1_OFFSET 0x34
|
||||
#define MCIO0_OFFSET 0x38
|
||||
#define MCIO1_OFFSET 0x3C
|
||||
#define MDMRS_OFFSET 0x40
|
||||
#define BOOT_DEF_OFFSET 0x44
|
||||
#if !defined(PXA2X0_NOPXA255)
|
||||
#define MDMRSLP_OFFSET 0x58
|
||||
#endif /* PXA255 and above only */
|
||||
#if !defined(PXA2X0_NOPXA260)
|
||||
#define SA1111CR_OFFSET 0x64
|
||||
#endif /* PXA260 and above only */
|
||||
|
||||
/* MDCNFG bits - see Table 6-3 in [1] and D25 in [2], Table 6-3 in [3], Table 6-2 in [4] */
|
||||
|
||||
#define MDCNFG_DSA1111_2 bit(28)
|
||||
#define MDCNFG_DLATCH2 bit(27)
|
||||
#define MDCNFG_DTC2_MASK bits(25,24)
|
||||
#define MDCNFG_DTC2(x) bits_val(25,24,x)
|
||||
#define get_MDCNFG_DTC2(x) bits_get(25,24,x)
|
||||
#define MDCNFG_DNB2 bit(23)
|
||||
#define MDCNFG_DRAC2_MASK bits(22,21)
|
||||
#define MDCNFG_DRAC2(x) bits_val(22,21,x)
|
||||
#define get_MDCNFG_DRAC2(x) bits_get(22,21,x)
|
||||
#define MDCNFG_DCAC2_MASK bits(20,19)
|
||||
#define MDCNFG_DCAC2(x) bits_val(20,19,x)
|
||||
#define get_MDCNFG_DCAC2(x) bits_get(20,19,x)
|
||||
#define MDCNFG_DWID2 bit(18)
|
||||
#define MDCNFG_DE3 bit(17)
|
||||
#define MDCNFG_DE2 bit(16)
|
||||
#define MDCNFG_DSA1111_0 bit(12)
|
||||
#define MDCNFG_DLATCH0 bit(11)
|
||||
#define MDCNFG_DTC0_MASK bits(9,8)
|
||||
#define MDCNFG_DTC0(x) bits_val(9,8,x)
|
||||
#define get_MDCNFG_DTC0(x) bits_get(9,8,x)
|
||||
#define MDCNFG_DNB0 bit(7)
|
||||
#define MDCNFG_DRAC0_MASK bits(6,5)
|
||||
#define MDCNFG_DRAC0(x) bits_val(6,5,x)
|
||||
#define get_MDCNFG_DRAC0(x) bits_get(6,5,x)
|
||||
#define MDCNFG_DCAC0_MASK bits(4,3)
|
||||
#define MDCNFG_DCAC0(x) bits_val(4,3,x)
|
||||
#define get_MDCNFG_DCAC0(x) bits_get(4,3,x)
|
||||
#define MDCNFG_DWID0 bit(2)
|
||||
#define MDCNFG_DE1 bit(1)
|
||||
#define MDCNFG_DE0 bit(0)
|
||||
|
||||
/* MDREFR bits - see Table 6-5 in [1], Table 6-6 in [3], Table 6-5 in [4] */
|
||||
|
||||
#define MDREFR_K2FREE bit(25)
|
||||
#define MDREFR_K1FREE bit(24)
|
||||
#define MDREFR_K0FREE bit(23)
|
||||
#define MDREFR_SLFRSH bit(22)
|
||||
#define MDREFR_APD bit(20)
|
||||
#define MDREFR_K2DB2 bit(19)
|
||||
#define MDREFR_K2RUN bit(18)
|
||||
#define MDREFR_K1DB2 bit(17)
|
||||
#define MDREFR_K1RUN bit(16)
|
||||
#define MDREFR_E1PIN bit(15)
|
||||
#define MDREFR_K0DB2 bit(14)
|
||||
#define MDREFR_K0RUN bit(13)
|
||||
#define MDREFR_E0PIN bit(12)
|
||||
#define MDREFR_DRI_MASK bits(11,0)
|
||||
#define MDREFR_DRI(x) bits_val(11,0,x)
|
||||
#define get_MDREFR_DRI(x) bits_get(11,0,x)
|
||||
|
||||
/* MSC0 bits - see Table 6-21 in [1], Table 6-25 in [3], Table 6-21 in [4] */
|
||||
|
||||
#define MSC0_RBUFF1 bit(31)
|
||||
#define MSC0_RRR1_MASK bits(30,28)
|
||||
#define MSC0_RRR1(x) bits_val(30,28,x)
|
||||
#define get_MSC0_RRR1(x) bits_get(30,28,x)
|
||||
#define MSC0_RDN1_MASK bits(27,24)
|
||||
#define MSC0_RDN1(x) bits_val(27,24,x)
|
||||
#define get_MSC0_RDN1(x) bits_get(27,24,x)
|
||||
#define MSC0_RDF1_MASK bits(23,20)
|
||||
#define MSC0_RDF1(x) bits_val(23,20,x)
|
||||
#define get_MSC0_RDF1(x) bits_get(23,20,x)
|
||||
#define MSC0_RBW1 bit(19)
|
||||
#define MSC0_RT1_MASK bits(18,16)
|
||||
#define MSC0_RT1(x) bits_val(18,16,x)
|
||||
#define get_MSC0_RT1(x) bits_get(18,16,x)
|
||||
#define MSC0_RBUFF0 bit(15)
|
||||
#define MSC0_RRR0_MASK bits(14,12)
|
||||
#define MSC0_RRR0(x) bits_val(14,12,x)
|
||||
#define get_MSC0_RRR0(x) bits_get(14,12,x)
|
||||
#define MSC0_RDN0_MASK bits(11,9)
|
||||
#define MSC0_RDN0(x) bits_val(11,8,x)
|
||||
#define get_MSC0_RDN0(x) bits_get(11,8,x)
|
||||
#define MSC0_RDF0_MASK bits(7,4)
|
||||
#define MSC0_RDF0(x) bits_val(7,4,x)
|
||||
#define get_MSC0_RDF0(x) bits_get(7,4,x)
|
||||
#define MSC0_RBW0 bit(3)
|
||||
#define MSC0_RT0_MASK bits(2,0)
|
||||
#define MSC0_RT0(x) bits_val(2,0,x)
|
||||
#define get_MSC0_RT0(x) bits_get(2,0,x)
|
||||
|
||||
/* MSC1 bits - see Table 6-21 in [1], Table 6-25 in [3], Table 6-21 in [4] */
|
||||
|
||||
#define MSC1_RBUFF3 bit(31)
|
||||
#define MSC1_RRR3_MASK bits(30,28)
|
||||
#define MSC1_RRR3(x) bits_val(30,28,x)
|
||||
#define get_MSC1_RRR3(x) bits_get(30,28,x)
|
||||
#define MSC1_RDN3_MASK bits(27,24)
|
||||
#define MSC1_RDN3(x) bits_val(27,24,x)
|
||||
#define get_MSC1_RDN3(x) bits_get(27,24,x)
|
||||
#define MSC1_RDF3_MASK bits(23,20)
|
||||
#define MSC1_RDF3(x) bits_val(23,20,x)
|
||||
#define get_MSC1_RDF3(x) bits_get(23,20,x)
|
||||
#define MSC1_RBW3 bit(19)
|
||||
#define MSC1_RT3_MASK bits(18,16)
|
||||
#define MSC1_RT3(x) bits_val(18,16,x)
|
||||
#define get_MSC1_RT3(x) bits_get(18,16,x)
|
||||
#define MSC1_RBUFF2 bit(15)
|
||||
#define MSC1_RRR2_MASK bits(14,12)
|
||||
#define MSC1_RRR2(x) bits_val(14,12,x)
|
||||
#define get_MSC1_RRR2(x) bits_get(14,12,x)
|
||||
#define MSC1_RDN2_MASK bits(11,9)
|
||||
#define MSC1_RDN2(x) bits_val(11,8,x)
|
||||
#define get_MSC1_RDN2(x) bits_get(11,8,x)
|
||||
#define MSC1_RDF2_MASK bits(7,4)
|
||||
#define MSC1_RDF2(x) bits_val(7,4,x)
|
||||
#define get_MSC1_RDF2(x) bits_get(7,4,x)
|
||||
#define MSC1_RBW2 bit(3)
|
||||
#define MSC1_RT2_MASK bits(2,0)
|
||||
#define MSC1_RT2(x) bits_val(2,0,x)
|
||||
#define get_MSC1_RT2(x) bits_get(2,0,x)
|
||||
|
||||
/* MSC2 bits - see Table 6-21 in [1], Table 6-25 in [3], Table 6-21 in [4] */
|
||||
|
||||
#define MSC2_RBUFF5 bit(31)
|
||||
#define MSC2_RRR5_MASK bits(30,28)
|
||||
#define MSC2_RRR5(x) bits_val(30,28,x)
|
||||
#define get_MSC2_RRR5(x) bits_get(30,28,x)
|
||||
#define MSC2_RDN5_MASK bits(27,24)
|
||||
#define MSC2_RDN5(x) bits_val(27,24,x)
|
||||
#define get_MSC2_RDN5(x) bits_get(27,24,x)
|
||||
#define MSC2_RDF5_MASK bits(23,20)
|
||||
#define MSC2_RDF5(x) bits_val(23,20,x)
|
||||
#define get_MSC2_RDF5(x) bits_get(23,20,x)
|
||||
#define MSC2_RBW5 bit(19)
|
||||
#define MSC2_RT5_MASK bits(18,16)
|
||||
#define MSC2_RT5(x) bits_val(18,16,x)
|
||||
#define get_MSC2_RT5(x) bits_get(18,16,x)
|
||||
#define MSC2_RBUFF4 bit(15)
|
||||
#define MSC2_RRR4_MASK bits(14,12)
|
||||
#define MSC2_RRR4(x) bits_val(14,12,x)
|
||||
#define get_MSC2_RRR4(x) bits_get(14,12,x)
|
||||
#define MSC2_RDN4_MASK bits(11,9)
|
||||
#define MSC2_RDN4(x) bits_val(11,8,x)
|
||||
#define get_MSC2_RDN4(x) bits_get(11,8,x)
|
||||
#define MSC2_RDF4_MASK bits(7,4)
|
||||
#define MSC2_RDF4(x) bits_val(7,4,x)
|
||||
#define get_MSC2_RDF4(x) bits_get(7,4,x)
|
||||
#define MSC2_RBW4 bit(3)
|
||||
#define MSC2_RT4_MASK bits(2,0)
|
||||
#define MSC2_RT4(x) bits_val(2,0,x)
|
||||
#define get_MSC2_RT4(x) bits_get(2,0,x)
|
||||
|
||||
/* MECR bits - see Table 6-27 in [1], Table 6-31 in [3], Table 6-27 in [4] */
|
||||
|
||||
#define MECR_CIT bit(1)
|
||||
#define MECR_NOS bit(0)
|
||||
|
||||
/* SXCNFG bits - see Table 6-13 in [1], Table 6-14 in [3], Table 6-13 in [4] */
|
||||
|
||||
#define SXCNFG_SXLATCH2 bit(30)
|
||||
#define SXCNFG_SXTP2_MASK bits(29,28)
|
||||
#define SXCNFG_SXTP2(x) bits_val(29,28,x)
|
||||
#define get_SXCNFG_SXTP2(x) bits_get(29,28,x)
|
||||
#define SXCNFG_SXCA2_MASK bits(27,26)
|
||||
#define SXCNFG_SXCA2(x) bits_val(27,26,x)
|
||||
#define get_SXCNFG_SXCA2(x) bits_get(27,26,x)
|
||||
#define SXCNFG_SXRA2_MASK bits(25,24)
|
||||
#define SXCNFG_SXRA2(x) bits_val(25,24,x)
|
||||
#define get_SXCNFG_SXRA2(x) bits_get(25,24,x)
|
||||
#define SXCNFG_SXRL2_MASK bits(23,21)
|
||||
#define SXCNFG_SXRL2(x) bits(23,21,x)
|
||||
#define SXCNFG_SXCL2_MASK bits(20,18)
|
||||
#define SXCNFG_SXCL2(x) bits_val(20,18,x)
|
||||
#define get_SXCNFG_SXCL2(x) bits_get(20,18,x)
|
||||
#define SXCNFG_SXEN2_MASK bits(17,16)
|
||||
#define SXCNFG_SXEN2(x) bits_val(17,16,x)
|
||||
#define get_SXCNFG_SXEN2(x) bits_get(17,16,x)
|
||||
#define SXCNFG_SXLATCH0 bit(14)
|
||||
#define SXCNFG_SXTP0_MASK bits(13,12)
|
||||
#define SXCNFG_SXTP0(x) bits_val(13,12,x)
|
||||
#define get_SXCNFG_SXTP0(x) bits_get(13,12,x)
|
||||
#define SXCNFG_SXCA0_MASK bits(11,10)
|
||||
#define SXCNFG_SXCA0(x) bits_val(11,10,x)
|
||||
#define get_SXCNFG_SXCA0(x) bits_get(11,10,x)
|
||||
#define SXCNFG_SXRA0_MASK bits(9,8)
|
||||
#define SXCNFG_SXRA0(x) bits_val(9,8,x)
|
||||
#define get_SXCNFG_SXRA0(x) bits_get(9,8,x)
|
||||
#define SXCNFG_SXRL0_MASK bits(7,5)
|
||||
#define SXCNFG_SXRL0(x) bits(7,5,x)
|
||||
#define SXCNFG_SXCL0_MASK bits(4,2)
|
||||
#define SXCNFG_SXCL0(x) bits_val(4,2,x)
|
||||
#define get_SXCNFG_SXCL0(x) bits_get(4,2,x)
|
||||
#define SXCNFG_SXEN0_MASK bits(1,0)
|
||||
#define SXCNFG_SXEN0(x) bits_val(1,0,x)
|
||||
#define get_SXCNFG_SXEN0(x) bits_get(1,0,x)
|
||||
|
||||
/* SXMRS bits - see Table 6-16 in [1], Table 6-17 in [3], Table 6-16 in [4] */
|
||||
|
||||
#define SXMRS_SXMRS2_MASK bits(30,16)
|
||||
#define SXMRS_SXMRS2(x) bits_val(30,16,x)
|
||||
#define get_SXMRS_SXMRS2(x) bits_get(30,16,x)
|
||||
#define SXMRS_SXMRS0_MASK bits(14,0)
|
||||
#define SXMRS_SXMRS0(x) bits_val(14,0,x)
|
||||
#define get_SXMRS_SXMRS0(x) bits_get(14,0,x)
|
||||
|
||||
/* MCMEMx bits - see Table 6-23 in [1], Table 6-27 in [3], Table 6-23 in [4] */
|
||||
|
||||
#define MCMEM_HOLD_MASK bits(19,14)
|
||||
#define MCMEM_HOLD(x) bits_val(19,14,x)
|
||||
#define get_MCMEM_HOLD(x) bits_get(19,14,x)
|
||||
#define MCMEM_ASST_MASK bits(11,7)
|
||||
#define MCMEM_ASST(x) bits_val(11,7,x)
|
||||
#define get_MCMEM_ASST(x) bits_get(11,7,x)
|
||||
#define MCMEM_SET_MASK bits(6,0)
|
||||
#define MCMEM_SET(x) bits_val(6,0,x)
|
||||
#define get_MCMEM_SET(x) bits_get(6,0,x)
|
||||
|
||||
/* MCATTx bits - see Table 6-24 in [1], Table 6-28 in [3], Table 6-24 in [4] */
|
||||
|
||||
#define MCATT_HOLD_MASK bits(19,14)
|
||||
#define MCATT_HOLD(x) bits_val(19,14,x)
|
||||
#define get_MCATT_HOLD(x) bits_get(19,14,x)
|
||||
#define MCATT_ASST_MASK bits(11,7)
|
||||
#define MCATT_ASST(x) bits_val(11,7,x)
|
||||
#define get_MCATT_ASST(x) bits_get(11,7,x)
|
||||
#define MCATT_SET_MASK bits(6,0)
|
||||
#define MCATT_SET(x) bits_val(6,0,x)
|
||||
#define get_MCATT_SET(x) bits_get(6,0,x)
|
||||
|
||||
/* MCIOx bits - see Table 6-25 in [1], Table 6-29 in [3], Table 6-25 in [4] */
|
||||
|
||||
#define MCIO_HOLD_MASK bits(19,14)
|
||||
#define MCIO_HOLD(x) bits_val(19,14,x)
|
||||
#define get_MCIO_HOLD(x) bits_get(19,14,x)
|
||||
#define MCIO_ASST_MASK bits(11,7)
|
||||
#define MCIO_ASST(x) bits_val(11,7,x)
|
||||
#define get_MCIO_ASST(x) bits_get(11,7,x)
|
||||
#define MCIO_SET_MASK bits(6,0)
|
||||
#define MCIO_SET(x) bits_val(6,0,x)
|
||||
#define get_MCIO_SET(x) bits_get(6,0,x)
|
||||
|
||||
/* MDMRS bits - see Table 6-4 in [1], Table 6-4 in [3], Table 6-3 in [4] */
|
||||
|
||||
#define MDMRS_MDMRS2_MASK bits(30,23)
|
||||
#define MDMRS_MDMRS2(x) bits_val(30,23,x)
|
||||
#define get_MDMRS_MDMRS2(x) bits_get(30,23,x)
|
||||
#define MDMRS_MDCL2_MASK bits(22,20)
|
||||
#define MDMRS_MDCL2(x) bits_val(22,20,x)
|
||||
#define get_MDMRS_MDCL2(x) bits_get(22,20,x)
|
||||
#define MDMRS_MDADD2 bit(19)
|
||||
#define MDMRS_MDBL2_MASK bits(18,16)
|
||||
#define MDMRS_MDBL2(x) bits_val(18,16,x)
|
||||
#define get_MDMRS_MDBL2(x) bits_get(18,16,x)
|
||||
#define MDMRS_MDMRS0_MASK bits(14,7)
|
||||
#define MDMRS_MDMRS0(x) bits_val(14,7,x)
|
||||
#define get_MDMRS_MDMRS0(x) bits_get(14,7,x)
|
||||
#define MDMRS_MDCL0_MASK bits(6,4)
|
||||
#define MDMRS_MDCL0(x) bits_val(6,4,x)
|
||||
#define get_MDMRS_MDCL0(x) bits_get(6,4,x)
|
||||
#define MDMRS_MDADD0 bit(3)
|
||||
#define MDMRS_MDBL0_MASK bits(2,0)
|
||||
#define MDMRS_MDBL0(x) bits_val(2,0,x)
|
||||
#define get_MDMRS_MDBL0(x) bits_get(2,0,x)
|
||||
|
||||
/* BOOT_DEF bits - see Table 6-37 in [1], Table 6-40 in [3], Table 6-37 in [4] */
|
||||
|
||||
#define BOOT_DEF_PKG_TYPE bit(3)
|
||||
#define BOOT_DEF_BOOT_SEL_MASK bits(2,0)
|
||||
#define BOOT_DEF_BOOT_SEL(x) bits_val(2,0,x)
|
||||
#define get_BOOT_DEF_BOOT_SEL(x) bits_get(2,0,x)
|
||||
|
||||
#if !defined(PXA2X0_NOPXA255)
|
||||
/* MDMRSLP bits - see Table 6-5 in [3], Table 6-4 in [4] */
|
||||
|
||||
#define MDMRSLP_MDLPEN2 bit(31)
|
||||
#define MDMRSLP_MDMRSLP2_MASK bits(30,16)
|
||||
#define MDMRSLP_MDMRSLP2(x) bits_val(30,16,x)
|
||||
#define get_MDMRSLP_MDMRSLP2(x) bits_get(30,16,x)
|
||||
#define MDMRSLP_MDLPEN0 bit(15)
|
||||
#define MDMRSLP_MDMRSLP0_MASK bits(14,0)
|
||||
#define MDMRSLP_MDMRSLP0(x) bits_val(14,0,x)
|
||||
#define get_MDMRSLP_MDMRSLP0(x) bits_get(14,0,x)
|
||||
#endif /* PXA255 and above only */
|
||||
|
||||
#if !defined(PXA2X0_NOPXA260)
|
||||
/* SA1111CR bits - see Table 6-24 in [3] */
|
||||
|
||||
#define SA1111CR_SA1111_5 bit(5)
|
||||
#define SA1111CR_SA1111_4 bit(4)
|
||||
#define SA1111CR_SA1111_3 bit(3)
|
||||
#define SA1111CR_SA1111_2 bit(2)
|
||||
#define SA1111CR_SA1111_1 bit(1)
|
||||
#define SA1111CR_SA1111_0 bit(0)
|
||||
#endif /* PXA260 and above only */
|
||||
|
||||
#endif /* PXA2X0_MC_H */
|
||||
@ -1,33 +1,93 @@
|
||||
/*
|
||||
* $Id$
|
||||
*
|
||||
* Flash Memory interface
|
||||
* Copyright (C) 2003 AH
|
||||
* Copyright (C) 2003 ETC s.r.o.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the ETC s.r.o. nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
|
||||
* 02111-1307, USA.
|
||||
*
|
||||
* Written by August Hörandl <august.hoerandl@gmx.at>
|
||||
* Written by Marcel Telka <marcel@telka.sk>, 2003.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef FLASH_H
|
||||
#define FLASH_H
|
||||
#define FLASH_H
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <bus/driver.h>
|
||||
|
||||
/* Following moved here from brux/cfi.h */
|
||||
|
||||
#include <flash/cfi.h>
|
||||
|
||||
#include <brux/bus.h>
|
||||
|
||||
typedef struct {
|
||||
int width; /* 1 for 8 bits, 2 for 16 bits, 4 for 32 bits, etc. */
|
||||
cfi_query_structure_t cfi;
|
||||
} cfi_chip_t;
|
||||
|
||||
typedef struct {
|
||||
bus_t *bus;
|
||||
uint32_t address;
|
||||
int bus_width; /* in cfi_chips, e.g. 4 for 32 bits */
|
||||
cfi_chip_t **cfi_chips;
|
||||
} cfi_array_t;
|
||||
|
||||
#include <brux/flash.h>
|
||||
void cfi_array_free( cfi_array_t *cfi_array );
|
||||
int cfi_detect( bus_t *bus, uint32_t adr, cfi_array_t **cfi_array );
|
||||
|
||||
/* End of brux/cfi.h */
|
||||
|
||||
typedef struct {
|
||||
unsigned int bus_width; /* 1 for 8 bits, 2 for 16 bits, 4 for 32 bits, etc. */
|
||||
const char *name;
|
||||
const char *description;
|
||||
int (*autodetect)( cfi_array_t *cfi_array );
|
||||
void (*print_info)( cfi_array_t *cfi_array );
|
||||
int (*erase_block)( cfi_array_t *cfi_array, uint32_t adr );
|
||||
int (*unlock_block)( cfi_array_t *cfi_array, uint32_t adr );
|
||||
int (*program)( cfi_array_t *cfi_array, uint32_t adr, uint32_t data );
|
||||
void (*readarray)( cfi_array_t *cfi_array );
|
||||
} flash_driver_t;
|
||||
|
||||
#define FLASH_ERROR_NOERROR 0
|
||||
#define FLASH_ERROR_INVALID_COMMAND_SEQUENCE 1
|
||||
#define FLASH_ERROR_LOW_VPEN 2
|
||||
#define FLASH_ERROR_BLOCK_LOCKED 3
|
||||
#define FLASH_ERROR_UNKNOWN 99
|
||||
|
||||
void detectflash( bus_t *bus, uint32_t adr );
|
||||
|
||||
void flashmem( bus_t *bus, FILE *f, uint32_t addr );
|
||||
void flashmsbin( bus_t *bus, FILE *f );
|
||||
|
||||
/* end of original brux/flash.h */
|
||||
|
||||
extern flash_driver_t *flash_drivers[];
|
||||
|
||||
#endif /* FLASH_H */
|
||||
|
||||
|
||||
@ -0,0 +1,160 @@
|
||||
/*
|
||||
* $Id$
|
||||
*
|
||||
* Common Flash Memory Interface (CFI) Declarations
|
||||
* Copyright (C) 2002 ETC s.r.o.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the ETC s.r.o. nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Written by Marcel Telka <marcel@telka.sk>, 2002.
|
||||
*
|
||||
* Documentation:
|
||||
* [1] JEDEC Solid State Technology Association, "Common Flash Interface (CFI)",
|
||||
* September 1999, Order Number: JESD68
|
||||
* [2] JEDEC Solid State Technology Association, "Common Flash Interface (CFI) ID Codes",
|
||||
* September 2001, Order Number: JEP137-A
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef FLASH_CFI_H
|
||||
#define FLASH_CFI_H
|
||||
|
||||
#include <openwince.h>
|
||||
|
||||
#if LANGUAGE == C
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
/* CFI commands - see Table 1 in [1] */
|
||||
|
||||
#define CFI_CMD_READ_ARRAY1 0xFF
|
||||
#define CFI_CMD_READ_ARRAY2 0xF0
|
||||
#define CFI_CMD_QUERY 0x98
|
||||
#define CFI_CMD_QUERY_OFFSET 0x55
|
||||
|
||||
/* Query identification string - see 4.3.2 in [1] */
|
||||
|
||||
#define CFI_QUERY_ID_OFFSET 0x10
|
||||
#define PRI_VENDOR_ID_OFFSET 0x13
|
||||
#define PRI_VENDOR_TABLE_ADR_OFFSET 0x15
|
||||
#define ALT_VENDOR_ID_OFFSET 0x17
|
||||
#define ALT_VENDOR_TABLE_ADR_OFFSET 0x19
|
||||
|
||||
#if LANGUAGE == C
|
||||
typedef struct cfi_query_identification_string {
|
||||
uint16_t pri_id_code;
|
||||
void *pri_vendor_tbl;
|
||||
uint16_t alt_id_code;
|
||||
void *alt_vendor_tbl;
|
||||
} cfi_query_identification_string_t;
|
||||
#endif /* LANGUAGE == C */
|
||||
|
||||
/* Algorithm command set & control interface ID codes - see Table 1 in [2] */
|
||||
|
||||
#define CFI_VENDOR_NULL 0x0000
|
||||
#define CFI_VENDOR_INTEL_ECS 0x0001
|
||||
#define CFI_VENDOR_AMD_SCS 0x0002
|
||||
#define CFI_VENDOR_INTEL_SCS 0x0003
|
||||
#define CFI_VENDOR_AMD_ECS 0x0004
|
||||
#define CFI_VENDOR_MITSUBISHI_SCS 0x0100
|
||||
#define CFI_VENDOR_MITSUBISHI_ECS 0x0101
|
||||
#define CFI_VENDOR_SST_PWCS 0x0102
|
||||
|
||||
/* Query system interface information - see 4.3.3 in [1] */
|
||||
|
||||
#define VCC_MIN_WEV_OFFSET 0x1B /* Vcc Logic Supply Minimum Write/Erase voltage */
|
||||
#define VCC_MAX_WEV_OFFSET 0x1C /* Vcc Logic Supply Maximum Write/Erase voltage */
|
||||
#define VPP_MIN_WEV_OFFSET 0x1D /* Vpp [Programming] Supply Minimum Write/Erase voltage */
|
||||
#define VPP_MAX_WEV_OFFSET 0x1E /* Vpp [Programming] Supply Maximum Write/Erase voltage */
|
||||
#define TYP_SINGLE_WRITE_TIMEOUT_OFFSET 0x1F /* Typical timeout per single byte/word write */
|
||||
#define TYP_BUFFER_WRITE_TIMEOUT_OFFSET 0x20 /* Typical timeout for minimum-size buffer write */
|
||||
#define TYP_BLOCK_ERASE_TIMEOUT_OFFSET 0x21 /* Typical timeout per individual block erase */
|
||||
#define TYP_CHIP_ERASE_TIMEOUT_OFFSET 0x22 /* Typical timeout for full chip erase */
|
||||
#define MAX_SINGLE_WRITE_TIMEOUT_OFFSET 0x23 /* Maximum timeout for byte/word write */
|
||||
#define MAX_BUFFER_WRITE_TIMEOUT_OFFSET 0x24 /* Maximum timeout for buffer write */
|
||||
#define MAX_BLOCK_ERASE_TIMEOUT_OFFSET 0x25 /* Maximum timeout per individual block erase */
|
||||
#define MAX_CHIP_ERASE_TIMEOUT_OFFSET 0x26 /* Maximum timeout for chip erase */
|
||||
|
||||
#if LANGUAGE == C
|
||||
typedef struct cfi_query_system_interface_information {
|
||||
uint16_t vcc_min_wev; /* in mV */
|
||||
uint16_t vcc_max_wev; /* in mV */
|
||||
uint16_t vpp_min_wev; /* in mV, 0 - no Vpp pin is present */
|
||||
uint16_t vpp_max_wev; /* in mV, 0 - no Vpp pin is present */
|
||||
uint32_t typ_single_write_timeout; /* in us, 0 - not supported */
|
||||
uint32_t typ_buffer_write_timeout; /* in us, 0 - not supported */
|
||||
uint32_t typ_block_erase_timeout; /* in ms, 0 - not supported */
|
||||
uint32_t typ_chip_erase_timeout; /* in ms, 0 - not supported */
|
||||
uint32_t max_single_write_timeout; /* in us, 0 - not supported */
|
||||
uint32_t max_buffer_write_timeout; /* in us, 0 - not supported */
|
||||
uint32_t max_block_erase_timeout; /* in ms, 0 - not supported */
|
||||
uint32_t max_chip_erase_timeout; /* in ms, 0 - not supported */
|
||||
} cfi_query_system_interface_information_t;
|
||||
#endif /* LANGUAGE == C */
|
||||
|
||||
/* Device geometry definition - see 4.3.4 in [1] */
|
||||
|
||||
#define DEVICE_SIZE_OFFSET 0x27 /* Device Size */
|
||||
#define FLASH_DEVICE_INTERFACE_OFFSET 0x28 /* Flash Device Interface description */
|
||||
#define MAX_BYTES_WRITE_OFFSET 0x2A /* Maximum number of bytes in multi-byte write */
|
||||
#define NUMBER_OF_ERASE_REGIONS_OFFSET 0x2C /* Number of Erase Block Regions */
|
||||
#define ERASE_BLOCK_REGION_OFFSET 0x2D /* Erase Block Region Information */
|
||||
|
||||
#if LANGUAGE == C
|
||||
typedef struct cfi_erase_block_region cfi_erase_block_region_t;
|
||||
|
||||
typedef struct cfi_device_geometry {
|
||||
uint32_t device_size; /* in B */
|
||||
uint16_t device_interface; /* see Table 2 in [2] */
|
||||
uint32_t max_bytes_write; /* in B */
|
||||
uint8_t number_of_erase_regions;
|
||||
cfi_erase_block_region_t *erase_block_regions;
|
||||
} cfi_device_geometry_t;
|
||||
|
||||
struct cfi_erase_block_region {
|
||||
uint32_t erase_block_size; /* in B */
|
||||
uint32_t number_of_erase_blocks;
|
||||
};
|
||||
#endif /* LANGUAGE == C */
|
||||
|
||||
/* Device interface code assignments (for cfi_device_geometry.device_interface) - see Table 2 in [2] */
|
||||
|
||||
#define CFI_INTERFACE_X8 0
|
||||
#define CFI_INTERFACE_X16 1
|
||||
#define CFI_INTERFACE_X8_X16 2
|
||||
#define CFI_INTERFACE_X32 3
|
||||
#define CFI_INTERFACE_X16_X32 4
|
||||
|
||||
/* CFI Query structure - see 4.3.1 in [1] */
|
||||
|
||||
#if LANGUAGE == C
|
||||
typedef struct cfi_query_structure {
|
||||
cfi_query_identification_string_t identification_string;
|
||||
cfi_query_system_interface_information_t system_interface_info;
|
||||
cfi_device_geometry_t device_geometry;
|
||||
} cfi_query_structure_t;
|
||||
#endif /* LANGUAGE == C */
|
||||
|
||||
#endif /* FLASH_CFI_H */
|
||||
@ -0,0 +1,99 @@
|
||||
/*
|
||||
* $Id$
|
||||
*
|
||||
* Copyright (C) 2002 ETC s.r.o.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the ETC s.r.o. nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Written by Marcel Telka <marcel@telka.sk>, 2002.
|
||||
*
|
||||
* Documentation:
|
||||
* [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
|
||||
* 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
|
||||
* [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
|
||||
* 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef FLASH_INTEL_H
|
||||
#define FLASH_INTEL_H
|
||||
|
||||
#include <openwince.h>
|
||||
|
||||
/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
|
||||
|
||||
#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */
|
||||
|
||||
/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
|
||||
|
||||
#define CFI_INTEL_SR_READY bit(7) /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_ERASE_SUSPEND bit(6) /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_ERASE_ERROR bit(5) /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_PROGRAM_ERROR bit(4) /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_VPEN_ERROR bit(3) /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_PROGRAM_SUSPEND bit(2) /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_BLOCK_LOCKED bit(1) /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
|
||||
#define CFI_INTEL_SR_BEFP bit(0) /* 28FxxxK3, 28FxxxK18 */
|
||||
|
||||
/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
|
||||
|
||||
#define CFI_CHIP_INTEL_28F320J3A 0x0016
|
||||
#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A"
|
||||
#define CFI_CHIP_INTEL_28F640J3A 0x0017
|
||||
#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A"
|
||||
#define CFI_CHIP_INTEL_28F128J3A 0x0018
|
||||
#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A"
|
||||
|
||||
/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
|
||||
|
||||
#define CFI_CHIP_INTEL_28F640K3 0x8801
|
||||
#define CFI_CHIPN_INTEL_28F640K3 "28F640K3"
|
||||
#define CFI_CHIP_INTEL_28F128K3 0x8802
|
||||
#define CFI_CHIPN_INTEL_28F128K3 "28F128K3"
|
||||
#define CFI_CHIP_INTEL_28F256K3 0x8803
|
||||
#define CFI_CHIPN_INTEL_28F256K3 "28F256K3"
|
||||
#define CFI_CHIP_INTEL_28F640K18 0x8805
|
||||
#define CFI_CHIPN_INTEL_28F640K18 "28F640K18"
|
||||
#define CFI_CHIP_INTEL_28F128K18 0x8806
|
||||
#define CFI_CHIPN_INTEL_28F128K18 "28F128K18"
|
||||
#define CFI_CHIP_INTEL_28F256K18 0x8807
|
||||
#define CFI_CHIPN_INTEL_28F256K18 "28F256K18"
|
||||
|
||||
#endif /* FLASH_INTEL_H */
|
||||
@ -0,0 +1,186 @@
|
||||
/*
|
||||
* $Id$
|
||||
*
|
||||
* Manufacturer's Identification Code declarations
|
||||
* Copyright (C) 2002 ETC s.r.o.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the ETC s.r.o. nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Written by Marcel Telka <marcel@telka.sk>, 2002.
|
||||
*
|
||||
* Documentation:
|
||||
* [1] JEDEC Solid State Technology Association, "Standard Manufacturer's
|
||||
* Identification Code", May 2003, Order Number: JEP106M
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef STD_MIC_H
|
||||
#define STD_MIC_H
|
||||
|
||||
/* Manufacturer's Identification Code - see Table 1 in [1] */
|
||||
|
||||
#define STD_MIC_AMD 0x01
|
||||
#define STD_MICN_AMD "AMD"
|
||||
#define STD_MIC_AMI 0x02
|
||||
#define STD_MICN_AMI "AMI"
|
||||
#define STD_MIC_FAIRCHILD 0x83
|
||||
#define STD_MICN_FAIRCHILD "Fairchild"
|
||||
#define STD_MIC_FUJITSU 0x04
|
||||
#define STD_MICN_FUJITSU "Fujitsu"
|
||||
#define STD_MIC_GTE 0x85
|
||||
#define STD_MICN_GTE "GTE"
|
||||
#define STD_MIC_HARRIS 0x86
|
||||
#define STD_MICN_HARRIS "Harris"
|
||||
#define STD_MIC_HITACHI 0x07
|
||||
#define STD_MICN_HITACHI "Hitachi"
|
||||
#define STD_MIC_INMOS 0x08
|
||||
#define STD_MICN_INMOS "Inmos"
|
||||
#define STD_MIC_INTEL 0x89
|
||||
#define STD_MICN_INTEL "Intel"
|
||||
#define STD_MIC_ITT 0x8A
|
||||
#define STD_MICN_ITT "I.T.T."
|
||||
#define STD_MIC_INTERSIL 0x0B
|
||||
#define STD_MICN_INTERSIL "Intersil"
|
||||
#define STD_MIC_MONOLITHIC_MEMORIES 0x8C
|
||||
#define STD_MICN_MONOLITHIC_MEMORIES "Monolithic Memories"
|
||||
#define STD_MIC_MOSTEK 0x0D
|
||||
#define STD_MICN_MOSTEK "Mostek"
|
||||
#define STD_MIC_MOTOROLA 0x0E
|
||||
#define STD_MICN_MOTOROLA "Motorola"
|
||||
#define STD_MIC_NATIONAL 0x8F
|
||||
#define STD_MICN_NATIONAL "National"
|
||||
#define STD_MIC_NEC 0x10
|
||||
#define STD_MICN_NEC "NEC"
|
||||
#define STD_MIC_RCA 0x91
|
||||
#define STC_MICN_RCA "RCA"
|
||||
#define STD_MIC_RAYTHEON 0x92
|
||||
#define STD_MICN_RAYTHEON "Raytheon"
|
||||
#define STD_MIC_CONEXANT 0x13
|
||||
#define STD_MICN_CONEXANT "Conexant (Rockwell)"
|
||||
#define STD_MIC_SEEQ 0x94
|
||||
#define STD_MICN_SEEQ "Seeq"
|
||||
#define STD_MIC_PHILIPS 0x15
|
||||
#define STD_MICN_PHILIPS "Philips Semi. (Signetics)"
|
||||
#define STD_MIC_SYNERTEK 0x16
|
||||
#define STD_MICN_SYNERTEK "Synertek"
|
||||
#define STD_MIC_TEXAS_INSTRUMENTS 0x97
|
||||
#define STD_MICN_TEXAS_INSTRUMENTS "Texas Instruments"
|
||||
#define STD_MIC_TOSHIBA 0x98
|
||||
#define STD_MICN_TOSHIBA "Toshiba"
|
||||
#define STD_MIC_XICOR 0x19
|
||||
#define STD_MICN_XICOR "Xicor"
|
||||
#define STD_MIC_ZILOG 0x1A
|
||||
#define STD_MICN_ZILOG "Zilog"
|
||||
#define STD_MIC_EUROTECHNIQUE 0x9B
|
||||
#define STD_MICN_EUROTECHNIQUE "Eurotechnique"
|
||||
#define STD_MIC_MITSUBISHI 0x1C
|
||||
#define STD_MICN_MITSUBISHI "Mitsubishi"
|
||||
#define STD_MIC_LUCENT 0x9D
|
||||
#define STD_MICN_LUCENT "Lucent (AT&T)"
|
||||
#define STD_MIC_EXEL 0x9E
|
||||
#define STD_MICN_EXEL "Exel"
|
||||
#define STD_MIC_ATMEL 0x1F
|
||||
#define STD_MICN_ATMEL "Atmel"
|
||||
#define STD_MIC_SGS_THOMSON 0x20
|
||||
#define STD_MICN_SGS_THOMSON "SGS/Thomson"
|
||||
#define STD_MIC_LATTICE 0xA1
|
||||
#define STD_MICN_LATTICE "Lattice Semi."
|
||||
#define STD_MIC_NCR 0xA2
|
||||
#define STD_MICN_NCR "NCR"
|
||||
#define STD_MIC_WAFER_SCALE_INTEGRATION 0x23
|
||||
#define STD_MICN_WAFER_SCALE_INTEGRATION "Wafer Scale Integration"
|
||||
#define STD_MIC_IBM 0xA4
|
||||
#define STD_MICN_IBM "IBM"
|
||||
#define STD_MIC_TRISTAR 0x25
|
||||
#define STD_MICN_TRISTAR "Tristar"
|
||||
#define STD_MIC_VISIC 0x26
|
||||
#define STD_MICN_VISIC "Visic"
|
||||
#define STD_MIC_INTL_CMOS_TECHNOLOGY 0xA7
|
||||
#define STD_MICN_INTL_CMOS_TECHNOLOGY "Intl. CMOS Technology"
|
||||
#define STD_MIC_SSSI 0xA8
|
||||
#define STD_MICN_SSSI "SSSI"
|
||||
#define STD_MIC_MICROCHIP_TECHNOLOGY 0x29
|
||||
#define STD_MICN_MICROCHIP_TECHNOLOGY "MicrochipTechnology"
|
||||
#define STD_MIC_RICOH 0x2A
|
||||
#define STD_MICN_RICOH "Ricoh Ltd."
|
||||
#define STD_MIC_VLSI 0xAB
|
||||
#define STD_MICN_VLSI "VLSI"
|
||||
#define STD_MIC_MICRON_TECHNOLOGY 0x2C
|
||||
#define STD_MICN_MICRON_TECHNOLOGY "Micron Technology"
|
||||
#define STD_MIC_HYUNDAI_ELECTRONICS 0xAD
|
||||
#define STD_MICN_HYUNDAI_ELECTRONICS "Hyundai Electronics"
|
||||
#define STD_MIC_OKI_SEMICONDUCTOR 0xAE
|
||||
#define STD_MICN_OKI_SEMICONDUCTOR "OKI Semiconductor"
|
||||
#define STD_MIC_ACTEL 0x2F
|
||||
#define STD_MICN_ACTEL "ACTEL"
|
||||
#define STD_MIC_SHARP 0xB0
|
||||
#define STD_MICN_SHARP "Sharp"
|
||||
#define STD_MIC_CATALYST 0x31
|
||||
#define STD_MICN_CATALYST "Catalyst"
|
||||
#define STD_MIC_PANASONIC 0x32
|
||||
#define STD_MICN_PANASONIC "Panasonic"
|
||||
#define STD_MIC_IDT 0xB3
|
||||
#define STD_MICN_IDT "IDT"
|
||||
#define STD_MIC_CYPRESS 0x34
|
||||
#define STD_MICN_CYPRESS "Cypress"
|
||||
#define STD_MIC_DEC 0xB5
|
||||
#define STD_MICN_DEC "DEC"
|
||||
#define STD_MIC_LSI_LOGIC 0xB6
|
||||
#define STD_MICN_LSI_LOGIC "LSI Logic"
|
||||
#define STD_MIC_ZARLINK 0x37
|
||||
#define STD_MICN_ZARLINK "Zarlink (formerly Plessey)"
|
||||
#define STD_MIC_UTMC 0x38
|
||||
#define STD_MICN_UTMC "UTMC"
|
||||
#define STD_MIC_THINKING_MACHINE 0xB9
|
||||
#define STD_MICN_THINKING_MACHINE "Thinking Machine"
|
||||
#define STD_MIC_THOMSON_CSF 0xBA
|
||||
#define STD_MICN_THOMSON_CSF "Thomson CSF"
|
||||
#define STD_MIC_INTEGRATED_CMOS 0x3B
|
||||
#define STD_MICN_INTEGRATED_CMOS "Integrated CMOS(Vertex)"
|
||||
#define STD_MIC_HONEYWELL 0xBC
|
||||
#define STD_MICN_HONEYWELL "Honeywell"
|
||||
#define STD_MIC_TEKTRONIX 0x3D
|
||||
#define STD_MICN_TEKTRONIX "Tektronix"
|
||||
#define STD_MIC_SUN_MICROSYSTEMS 0x3E
|
||||
#define STD_MICN_SUN_MICROSYSTEMS "Sun Microsystems"
|
||||
#define STD_MIC_SST 0xBF
|
||||
#define STD_MICN_SST "SST"
|
||||
#define STD_MIC_MOSEL 0x40
|
||||
#define STD_MICN_MOSEL "MOSEL"
|
||||
#define STD_MIC_INFINEON 0xC1
|
||||
#define STD_MICN_INFINEON "Infineon (formerly Siemens)"
|
||||
#define STD_MIC_MACRONIX 0xC2
|
||||
#define STD_MICN_MACRONIX "Macronix"
|
||||
#define STD_MIC_XEROX 0x43
|
||||
#define STD_MICN_XEROX "Xerox"
|
||||
#define STD_MIC_PLUS_LOGIC 0xC4
|
||||
#define STD_MICN_PLUS_LOGIC "Plus Logic"
|
||||
#define STD_MIC_SUNDISK 0x45
|
||||
#define STD_MICN_SUNDISK "SunDisk"
|
||||
#define STD_MIC_ELAN_CIRCUIT 0x46
|
||||
#define STD_MICN_ELAN_CIRCUIT "Elan Circuit Tech."
|
||||
/* TODO */
|
||||
|
||||
#endif /* STD_MIC_H */
|
||||
Loading…
Reference in New Issue