buses: add class types and more hooks in preparation for other types of buses (SPI/I2C) by Jonathan Stroud

git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@1966 b68d4a1b-bc3d-0410-92ed-d4ac073336b7
master
Mike Frysinger 14 years ago
parent da894d0249
commit afc51a142e

@ -1,3 +1,21 @@
2011-07-07 Mike Frysinger <vapier@gentoo.org>
* include/urjtag/bus_driver.h, src/bus/generic_bus.c, src/bus/generic_bus.h:
Add bus type classification and new enable/disable/write_start hooks (in
preparation for other bus types) by Jonathan Stroud.
* src/bus/fjmem.c, src/bus/ppc405ep.c, src/bus/sh7727.c, src/bus/bscoach.c,
src/bus/prototype.c, src/bus/sa1110.c, src/bus/mpc837x.c,
src/bus/ppc440gx_ebc8.c, src/bus/ejtag_dma.c, src/bus/sh7750r.c,
src/bus/tx4925.c, src/bus/pxa2x0.c, src/bus/arm9tdmi.c, src/bus/ixp425.c,
src/bus/avr32.c, src/bus/ixp465.c, src/bus/zefant-xs3.c, src/bus/h7202.c,
src/bus/mpc824x.c, src/bus/bcm1250.c, src/bus/sharc21065l.c,
src/bus/sharc21369_ezkit.c, src/bus/au1500.c, src/bus/blackfin.h,
src/bus/lh7a400.c, src/bus/sh7751r.c, src/bus/mpc5200.c, src/bus/jopcyc.c,
src/bus/slsup3.c, src/bus/ejtag.c, src/bus/s3c4510x.c, src/bus/ixp435.c:
Fill out new hook points and declare all as parallel bus drivers.
* src/flash/amd_flash.c, src/flash/cfi.c, src/flash/jedec.c,
src/flash/jedec_exp.c: Only work with parallel buses.
2011-07-06 Mike Frysinger <vapier@gentoo.org>
* src/flash/intel.c: Add support for 28F256P33 flashes by Jonathan Stroud.

@ -84,6 +84,14 @@ typedef enum URJ_BUS_PARAM_KEY
}
urj_bus_param_key_t;
typedef enum URJ_BUS_TYPE
{
URJ_BUS_TYPE_PARALLEL,
URJ_BUS_TYPE_SPI,
URJ_BUS_TYPE_I2C,
}
urj_bus_type_t;
struct URJ_BUS_DRIVER
{
const char *name;
@ -105,8 +113,12 @@ struct URJ_BUS_DRIVER
/* @@@@ RFHH need to return status */
uint32_t (*read) (urj_bus_t *bus, uint32_t adr);
/* @@@@ RFHH need to return status */
int (*write_start) (urj_bus_t *bus, uint32_t adr);
void (*write) (urj_bus_t *bus, uint32_t adr, uint32_t data);
int (*init) (urj_bus_t *bus);
int (*enable) (urj_bus_t *bus);
int (*disable) (urj_bus_t *bus);
urj_bus_type_t bus_type;
};
struct URJ_BUS
@ -115,6 +127,7 @@ struct URJ_BUS
urj_part_t *part;
void *params;
int initialized;
int enabled;
const urj_bus_driver_t *driver;
};
@ -126,9 +139,13 @@ struct URJ_BUS
#define URJ_BUS_READ_NEXT(bus,adr) (bus)->driver->read_next(bus,adr)
#define URJ_BUS_READ_END(bus) (bus)->driver->read_end(bus)
#define URJ_BUS_READ(bus,adr) (bus)->driver->read(bus,adr)
#define URJ_BUS_WRITE_START(bus,adr) (bus)->driver->write_start(bus,adr)
#define URJ_BUS_WRITE(bus,adr,data) (bus)->driver->write(bus,adr,data)
#define URJ_BUS_FREE(bus) (bus)->driver->free_bus(bus)
#define URJ_BUS_INIT(bus) (bus)->driver->init(bus)
#define URJ_BUS_ENABLE(bus) (bus)->driver->enable(bus)
#define URJ_BUS_DISABLE(bus) (bus)->driver->disable(bus)
#define URJ_BUS_TYPE(bus) (bus)->driver->bus_type
/**
* API function to init a bus

@ -562,7 +562,10 @@ const urj_bus_driver_t urj_bus_arm9tdmi_bus = {
arm9tdmi_bus_read_next,
arm9tdmi_bus_read_end,
arm9tdmi_bus_read,
urj_bus_generic_write_start,
arm9tdmi_bus_write,
arm9tdmi_bus_init
arm9tdmi_bus_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -308,6 +308,10 @@ const urj_bus_driver_t urj_bus_au1500_bus = {
au1500_bus_read_next,
au1500_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
au1500_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -820,6 +820,10 @@ const urj_bus_driver_t urj_bus_avr32_bus = {
avr32_bus_read_next,
avr32_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
avr32_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -536,6 +536,10 @@ const urj_bus_driver_t urj_bus_bcm1250_bus = {
#else
bcm1250_bus_read,
#endif
urj_bus_generic_write_start,
bcm1250_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -80,8 +80,12 @@ const urj_bus_driver_t urj_bus_##board##_bus = \
bfin_bus_read_next, \
bfin_bus_read_end, \
urj_bus_generic_read, \
urj_bus_generic_write_start, \
/*funcs##_bus_write,*/ bfin_bus_write, \
urj_bus_generic_no_init \
urj_bus_generic_no_init, \
urj_bus_generic_no_enable, \
urj_bus_generic_no_disable, \
URJ_BUS_TYPE_PARALLEL, \
}
#define BFIN_BUS_DECLARE(board, desc) _BFIN_BUS_DECLARE(board, board, desc)

@ -385,6 +385,10 @@ const urj_bus_driver_t urj_bus_bscoach_bus = {
flashbscoach_bus_read_next,
flashbscoach_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
flashbscoach_bus_write,
flashbscoach_bus_init
flashbscoach_bus_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -773,6 +773,10 @@ const urj_bus_driver_t urj_bus_ejtag_bus = {
ejtag_bus_read_next,
ejtag_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
ejtag_bus_write,
ejtag_bus_init
ejtag_bus_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -694,6 +694,10 @@ const urj_bus_driver_t urj_bus_ejtag_dma_bus = {
ejtag_dma_bus_read_next,
ejtag_dma_bus_read_end,
ejtag_dma_bus_read,
urj_bus_generic_write_start,
ejtag_dma_bus_write,
ejtag_dma_bus_init
ejtag_dma_bus_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -741,8 +741,12 @@ const urj_bus_driver_t urj_bus_fjmem_bus = {
fjmem_bus_read_next,
fjmem_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
fjmem_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -100,6 +100,30 @@ urj_bus_generic_no_init (urj_bus_t *bus)
return URJ_STATUS_OK;
}
/**
* bus->driver->(*enable)
*
*/
int
urj_bus_generic_no_enable (urj_bus_t *bus)
{
bus->enabled = 1;
return URJ_STATUS_OK;
}
/**
* bus->driver->(*disable)
*
*/
int
urj_bus_generic_no_disable (urj_bus_t *bus)
{
bus->enabled = 0;
return URJ_STATUS_OK;
}
/**
* bus->driver->(*prepare)
*
@ -114,6 +138,16 @@ urj_bus_generic_prepare_extest (urj_bus_t *bus)
urj_tap_chain_shift_instructions (bus->chain);
}
/**
* bus->driver->(*write_start)
*
*/
int
urj_bus_generic_write_start (urj_bus_t *bus, uint32_t adr)
{
return 0;
}
/**
* bus->driver->(*read)
*

@ -37,7 +37,10 @@ urj_bus_t *urj_bus_generic_new (urj_chain_t *chain,
size_t param_size);
void urj_bus_generic_free (urj_bus_t *bus);
int urj_bus_generic_no_init (urj_bus_t *bus);
int urj_bus_generic_no_enable (urj_bus_t *bus);
int urj_bus_generic_no_disable (urj_bus_t *bus);
void urj_bus_generic_prepare_extest (urj_bus_t *bus);
int urj_bus_generic_write_start(urj_bus_t *bus, uint32_t adr);
uint32_t urj_bus_generic_read (urj_bus_t *bus, uint32_t adr);
#endif /* URJ_BUS_GENERIC_BUS_H */

@ -303,6 +303,10 @@ const urj_bus_driver_t urj_bus_h7202_bus = {
h7202_bus_read_next,
h7202_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
h7202_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -297,6 +297,10 @@ const urj_bus_driver_t urj_bus_ixp425_bus = {
ixp425_bus_read_next,
ixp425_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
ixp425_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -285,6 +285,10 @@ const urj_bus_driver_t urj_bus_ixp435_bus = {
ixp435_bus_read_next,
ixp435_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
ixp435_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -309,6 +309,10 @@ const urj_bus_driver_t urj_bus_ixp465_bus = {
ixp465_bus_read_next,
ixp465_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
ixp465_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -701,8 +701,12 @@ const urj_bus_driver_t urj_bus_jopcyc_bus = {
jopcyc_bus_read_next,
jopcyc_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
jopcyc_bus_write,
jopcyc_bus_init
jopcyc_bus_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -334,6 +334,10 @@ const urj_bus_driver_t urj_bus_lh7a400_bus = {
lh7a400_bus_read_next,
lh7a400_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
lh7a400_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -408,6 +408,10 @@ const urj_bus_driver_t urj_bus_mpc5200_bus = {
mpc5200_bus_read_next,
mpc5200_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
mpc5200_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -590,6 +590,10 @@ const urj_bus_driver_t urj_bus_mpc824x_bus = {
mpc824x_bus_read_next,
mpc824x_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
mpc824x_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -500,6 +500,10 @@ const urj_bus_driver_t urj_bus_mpc837x_bus = {
mpc837x_bus_read_next,
mpc837x_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
mpc837x_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -274,6 +274,10 @@ const urj_bus_driver_t urj_bus_ppc405ep_bus = {
ppc405ep_bus_read_next,
ppc405ep_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
ppc405ep_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -278,6 +278,10 @@ const urj_bus_driver_t urj_bus_ppc440gx_ebc8_bus = {
ppc440gx_ebc8_bus_read_next,
ppc440gx_ebc8_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
ppc440gx_ebc8_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -526,6 +526,10 @@ const urj_bus_driver_t urj_bus_prototype_bus = {
prototype_bus_read_next,
prototype_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
prototype_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -768,8 +768,12 @@ const urj_bus_driver_t urj_bus_pxa2x0_bus = {
pxa2xx_bus_read_next,
pxa2xx_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
pxa2xx_bus_write,
pxa2xx_bus_init
pxa2xx_bus_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};
const urj_bus_driver_t urj_bus_pxa27x_bus = {
@ -784,6 +788,10 @@ const urj_bus_driver_t urj_bus_pxa27x_bus = {
pxa2xx_bus_read_next,
pxa2xx_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
pxa2xx_bus_write,
pxa2xx_bus_init
pxa2xx_bus_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -434,6 +434,10 @@ const urj_bus_driver_t urj_bus_s3c4510_bus = {
s3c4510_bus_read_next,
s3c4510_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
s3c4510_bus_write,
s3c4510_bus_init
s3c4510_bus_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -314,6 +314,10 @@ const urj_bus_driver_t urj_bus_sa1110_bus = {
sa1110_bus_read_next,
sa1110_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
sa1110_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -354,6 +354,10 @@ const urj_bus_driver_t urj_bus_sh7727_bus = {
sh7727_bus_read_next,
sh7727_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
sh7727_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -335,6 +335,10 @@ const urj_bus_driver_t urj_bus_sh7750r_bus = {
sh7750r_bus_read_next,
sh7750r_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
sh7750r_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -323,6 +323,10 @@ const urj_bus_driver_t urj_bus_sh7751r_bus = {
sh7751r_bus_read_next,
sh7751r_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
sh7751r_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -323,6 +323,10 @@ const urj_bus_driver_t urj_bus_sharc_21065L_bus = {
sharc_21065L_bus_read_next,
sharc_21065L_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
sharc_21065L_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -309,6 +309,10 @@ const urj_bus_driver_t urj_bus_sharc_21369_ezkit_bus = {
sharc_21369_bus_read_next,
sharc_21369_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
sharc_21369_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -447,6 +447,10 @@ const urj_bus_driver_t urj_bus_slsup3_bus = {
slsup3_bus_read_next,
slsup3_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
slsup3_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -318,6 +318,10 @@ const urj_bus_driver_t urj_bus_tx4925_bus = {
tx4925_bus_read_next,
tx4925_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
tx4925_bus_write,
urj_bus_generic_no_init
urj_bus_generic_no_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -995,8 +995,12 @@ const urj_bus_driver_t urj_bus_zefant_xs3_bus = {
zefant_xs3_bus_read_next,
zefant_xs3_bus_read_end,
urj_bus_generic_read,
urj_bus_generic_write_start,
zefant_xs3_bus_write,
zefant_xs3_bus_init
zefant_xs3_bus_init,
urj_bus_generic_no_enable,
urj_bus_generic_no_disable,
URJ_BUS_TYPE_PARALLEL,
};

@ -107,6 +107,8 @@ urj_flash_amd_detect (urj_bus_t *bus, uint32_t adr,
// retain error state
return URJ_STATUS_FAIL;
if (URJ_BUS_TYPE (bus) != URJ_BUS_TYPE_PARALLEL)
return URJ_STATUS_FAIL;
URJ_BUS_WRITE (bus, adr + 0x0, 0xf0);
URJ_BUS_WRITE (bus, adr + 0x555, 0xaa);
URJ_BUS_WRITE (bus, adr + 0x2AA, 0x55);

@ -100,6 +100,8 @@ urj_flash_cfi_detect (urj_bus_t *bus, uint32_t adr,
if (URJ_BUS_AREA (bus, adr, &area) != URJ_STATUS_OK)
// retain error state
return URJ_STATUS_FAIL;
if (URJ_BUS_TYPE (bus) != URJ_BUS_TYPE_PARALLEL)
return URJ_STATUS_FAIL;
bw = area.width;
if (bw != 8 && bw != 16 && bw != 32)
{

@ -447,6 +447,8 @@ urj_flash_jedec_detect (urj_bus_t *bus, uint32_t adr,
if (URJ_BUS_AREA (bus, adr, &area) != URJ_STATUS_OK)
// retain error state
return URJ_STATUS_FAIL;
if (URJ_BUS_TYPE (bus) != URJ_BUS_TYPE_PARALLEL)
return URJ_STATUS_FAIL;
bw = area.width;
if (bw != 8 && bw != 16 && bw != 32)
{

@ -88,6 +88,8 @@ urj_flash_jedec_exp_detect (urj_bus_t *bus, uint32_t adr,
if (URJ_BUS_AREA (bus, adr, &area) != URJ_STATUS_OK)
// retain error state
return URJ_STATUS_FAIL;
if (URJ_BUS_TYPE (bus) != URJ_BUS_TYPE_PARALLEL)
return URJ_STATUS_FAIL;
bw = area.width;
if (bw == 0)

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