Updates to JIM; the intel flash now could be detected (but UrJTAG fails on this one..)
git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@950 b68d4a1b-bc3d-0410-92ed-d4ac073336b7master
Kolja Waschk
17 years ago
parent
8d7e8c7c57
commit
b5df073aa0
@ -1,27 +1,191 @@
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/*
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* $Id: tap.c $
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*
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* Copyright (C) 2008 Kolja Waschk <kawk>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This code simulates an Intel Advanced Boot Block Flash Memory (B3) 28FxxxB3.
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* The simulation is based on documentation found in the corresponding datasheet,
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* Order Number 290580, Revision: 020, 18 Aug 2005.
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*/
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#include <jim.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdio.h>
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typedef enum
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{
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READ_ARRAY,
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READ_STATUS,
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READ_ID,
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PROG_SETUP,
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PROG_CONTINUE,
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PROG_SUSP_TO_READ_STATUS,
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PROG_SUSP_TO_READ_ARRAY,
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PROG_SUSP_TO_READ_ID,
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PROG_COMPLETE,
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ERASE_SETUP,
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ERASE_ERROR,
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ERASE_CONTINUE,
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ERASE_SUSP_TO_READ_STATUS,
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ERASE_SUSP_TO_READ_ARRAY,
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ERASE_SUSP_TO_READ_ID,
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ERASE_COMPLETE
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}
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intel_f28xxxb3_op_state_t;
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void intel_28f800b3_init(jim_bus_device_t *d)
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typedef enum
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{
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TOP = 0,
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BOTTOM = 1
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}
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b3_boot_type_t;
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void intel_28f800b3_free(jim_bus_device_t *d)
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typedef struct
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{
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uint16_t identifier;
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uint32_t control_buffer;
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uint8_t status, status_buffer;
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intel_f28xxxb3_op_state_t opstate;
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b3_boot_type_t boot_type;
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}
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intel_f28xxxb3_state_t;
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void intel_28f800b3_access(jim_bus_device_t *d,
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uint32_t address, uint32_t data, uint32_t control)
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void intel_28fxxxb3_init(jim_bus_device_t *d, uint16_t id, b3_boot_type_t bt)
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{
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d->state = malloc(sizeof(intel_f28xxxb3_state_t));
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if(d->state != NULL)
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{
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intel_f28xxxb3_state_t *is = d->state;
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is->opstate = READ_ARRAY;
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is->identifier = id;
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is->boot_type = bt;
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is->status = 0x00;
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is->status_buffer = 0x00;
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is->control_buffer = 0x00000000;
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}
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}
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void intel_28f800b3t_init(jim_bus_device_t *d)
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{
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intel_28fxxxb3_init(d, 0x8893, BOTTOM);
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}
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void intel_28fxxxb3_free(jim_bus_device_t *d)
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{
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if(d->state != NULL) free(d->state);
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}
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uint32_t intel_28fxxxb3_capture(jim_bus_device_t *d,
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uint32_t address, uint32_t control,
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uint8_t *shmem, size_t shmem_size)
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{
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uint32_t data = 0;
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if((control&7) == 5) /* OE and CS: READ */
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{
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intel_f28xxxb3_state_t *is = d->state;
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switch(is->opstate)
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{
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case READ_STATUS:
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data = is->status_buffer;
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break;
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case READ_ID:
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if(address == 0) data = is->identifier;
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else if(address == 1) data = 0x0089;
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break;
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case READ_ARRAY:
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data = shmem[(address<<1)]<<8;
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data |= shmem[(address<<1)]+1;
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break;
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default:
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break;
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}
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}
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printf("capture A=%08X, D=%08X%s%s%s\n", address, data,
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(control & 1) ? ", OE":"",
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(control & 2) ? ", WE":"",
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(control & 4) ? ", CS":"");
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return data;
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}
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void intel_28fxxxb3_update(jim_bus_device_t *d,
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uint32_t address, uint32_t data, uint32_t control,
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uint8_t *shmem, size_t shmem_size)
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{
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printf("update A=%08X, D=%08X%s%s%s\n", address, data,
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(control & 1) ? ", OE":"",
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(control & 2) ? ", WE":"",
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(control & 4) ? ", CS":"");
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if(d->state != NULL)
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{
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intel_f28xxxb3_state_t *is = d->state;
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if( (((is->control_buffer&1)==0) && ((control&1)==1)) /* OE rise */
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||(((is->control_buffer&4)==0) && ((control&4)==1))) /* CS rise */
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{
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is->status_buffer = is->status; /* latch status */
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};
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if(((control&7)==6)&&((is->control_buffer&2)!=2)) /* WE rise, CS active: WRITE */
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{
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intel_f28xxxb3_state_t *is = d->state;
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uint8_t dl = data & 0xFF;
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switch(is->opstate)
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{
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case READ_ARRAY:
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case READ_STATUS:
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case READ_ID:
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switch(dl)
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{
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case 0x10:
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case 0x40: is->opstate = PROG_SETUP; break;
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case 0x20: is->opstate = ERASE_SETUP; break;
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case 0x70: is->opstate = READ_STATUS; break;
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case 0x90: is->opstate = READ_ID; break;
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case 0xD0: is->opstate = READ_ARRAY; break;
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case 0xB0: is->opstate = READ_ARRAY; break;
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case 0xFF: is->opstate = READ_ARRAY; break;
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default: is->opstate = READ_ARRAY; break;
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}
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break;
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default:
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break;
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}
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};
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is->control_buffer = control;
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}
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}
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jim_bus_device_t intel_28f800b3 =
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jim_bus_device_t intel_28f800b3t =
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{
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16, /* width [bits] */
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0x800, /* size [bytes] */
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NULL, /* state */
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intel_28f800b3_init, /* init() */
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intel_28f800b3_access, /* access() */
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intel_28f800b3_free /* free() */
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2, /* width [bytes] */
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0x80000, /* size [words, each <width> bytes] */
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NULL, /* state */
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intel_28f800b3t_init, /* init() */
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intel_28fxxxb3_capture, /* access() */
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intel_28fxxxb3_update, /* access() */
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intel_28fxxxb3_free /* free() */
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};
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