From ba4136a09a4303d57c1b01de734cbe70595c9cd5 Mon Sep 17 00:00:00 2001 From: Marcel Telka Date: Mon, 22 Jul 2002 12:05:55 +0000 Subject: [PATCH] Added JTAG declarations for SA-1110. git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@62 b68d4a1b-bc3d-0410-92ed-d4ac073336b7 --- jtag/data/intel/sa1110/sa1110 | 507 ++++++++++++++++++++++++++++++++++ 1 file changed, 507 insertions(+) create mode 100644 jtag/data/intel/sa1110/sa1110 diff --git a/jtag/data/intel/sa1110/sa1110 b/jtag/data/intel/sa1110/sa1110 new file mode 100644 index 00000000..4c2f23e9 --- /dev/null +++ b/jtag/data/intel/sa1110/sa1110 @@ -0,0 +1,507 @@ +# +# $Id$ +# +# JTAG declarations for SA-1110 +# Copyright (C) 2002 ETC s.r.o. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 +# of the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA +# 02111-1307, USA. +# +# Written by Marcel Telka , 2002. +# +# [1] Intel Corporation, "Intel StrongARM SA-1110 Microprocessor +# Developer's Manual", October 2001, Order Number: 278240-004 +# [2] Intel Corporation, "Intel StrongARM SA-1110 Microprocessor +# Specification Update", December 2001, Order Number: 278259-023 +# + +# see Table 14-2 in [1] +pin A0 D12 +pin A1 C12 +pin A2 B12 +pin A3 A13 +pin A4 C13 +pin A5 B13 +pin A6 A14 +pin A7 A15 +pin A8 A16 +pin A9 B15 +pin A10 B14 +pin A11 C14 +pin A12 B16 +pin A13 D13 +pin A14 E13 +pin A15 C16 +pin A16 D15 +pin A17 E14 +pin A18 D16 +pin A19 E15 +pin A20 F14 +pin A21 E16 +pin A22 F15 +pin A23 F13 +pin A24 G13 +pin A25 F16 +pin BATT_FAULT A4 +pin nCAS0 J14 +pin nCAS1 J15 +pin nCAS2 K15 +pin nCAS3 K13 +pin nCS0 G14 +pin nCS1 G15 +pin nCS2 G16 +pin nCS3 H14 +pin nCS4 H15 +pin nCS5 H16 +pin D0 E4 +pin D1 F4 +pin D2 F2 +pin D3 G2 +pin D4 H1 +pin D5 J4 +pin D6 K1 +pin D7 L1 +pin D8 D2 +pin D9 E2 +pin D10 F1 +pin D11 H6 +pin D12 J6 +pin D13 J1 +pin D14 K4 +pin D15 L4 +pin D16 D1 +pin D17 E1 +pin D18 G4 +pin D19 G1 +pin D20 J2 +pin D21 K2 +pin D22 L3 +pin D23 M2 +pin D24 E3 +pin D25 F3 +pin D26 G3 +pin D27 H4 +pin D28 J3 +pin D29 K3 +pin D30 L2 +pin D31 M1 +pin GP0 T10 +pin GP1 P10 +pin GP2 R10 +pin GP3 N10 +pin GP4 T9 +pin GP5 P9 +pin GP6 R8 +pin GP7 N8 +pin GP8 P8 +pin GP9 T7 +pin GP10 P7 +pin GP11 T6 +pin GP12 R7 +pin GP13 R6 +pin GP14 P6 +pin GP15 N6 +pin GP16 T5 +pin GP17 R5 +pin GP18 P5 +pin GP19 T4 +pin GP20 R4 +pin GP21 T3 +pin GP22 R3 +pin GP23 T2 +pin GP24 P4 +pin GP25 R2 +pin GP26 T1 +pin GP27 R1 +pin nIOIS16 N13 +pin L_BIAS R11 +pin L_FCLK T14 +pin L_LCLK R14 +pin L_PCLK P11 +pin LDD0 N12 +pin LDD1 T11 +pin LDD2 R12 +pin LDD3 P12 +pin LDD4 T12 +pin LDD5 R13 +pin LDD6 T13 +pin LDD7 P13 +pin nOE M15 +pin nPCE1 M16 +pin nPCE2 N15 +pin PEXTAL A8 +pin nPIOR T16 +pin nPIOW R16 +pin nPOE R15 +pin nPREG N14 +pin PSKTSEL P16 +pin nPWAIT N16 +pin nPWE T16 +pin PWR_EN A3 +pin PXTAL B8 +pin nRAS0 K16 +pin nRAS1 L13 +pin nRAS2 L14 +pin nRAS3 L15 +pin RD_nWR J13 +pin RDY H13 +pin nRESET B7 +pin nRESET_OUT C7 +pin ROMSEL D6 +pin RXD_1 B11 +pin RXD_2 B10 +pin RXD_3 C10 +pin RXD_C B1 +pin SCLK_C A2 +pin nSDCAS L16 +pin SDCKE0 N1 +pin SDCKE1 N2 +pin SDCLK0 P1 +pin SDCLK1 N3 +pin SDCLK2 M3 +pin nSDRAS M14 +pin SFRM_C B3 +pin SMROM_EN M4 +pin TCK C5 +pin TCK_BYP A6 +pin TDI A5 +pin TDO B5 +pin TESTCLK B6 +pin TEXTAL C9 +pin TMS C6 +pin nTRST B4 +pin TXTAL B9 +pin TXD_1 A11 +pin TXD_2 D10 +pin TXD_3 A10 +pin TXD_C C2 +pin UDC- A12 +pin UDC+ C11 +pin VDD A7 C1 C15 H3 J16 P3 P15 T8 +pin VDD_FAULT C4 +pin VDDP C8 +pin VDDX1 D5 D9 D11 E6 E7 E8 E9 E10 E11 K10 K11 L10 L11 M6 M7 M8 M9 M10 M11 N7 N9 N11 +pin VDDX2 E12 F5 F12 G5 G12 H5 H12 J5 J12 K5 K12 L5 L12 M5 M12 N4 N5 +pin VDDX3 D7 +pin VSS A8 D3 D8 D14 H2 K14 P2 P14 R9 +pin VSSX A1 B2 C3 D4 E5 F6 F7 F8 F9 F10 F11 G6 G7 G8 G9 G10 G11 H7 H8 H9 H10 H11 J7 J8 J9 J10 J11 K6 K7 K8 K9 L6 L7 L8 L9 +pin nWE M13 + +# see 16.5 in [1] +instruction length 5 + +instruction EXTEST 00000 +instruction SAMPLE/PRELOAD 00001 +instruction BYPASS 11111 + +instruction CLAMP 00100 +instruction HIGHZ 00101 +instruction IDCODE 00110 + +# see Table 16-2 in [1] +boundary length 292 + +bit 291 I ? BATT_FAULT +bit 290 I ? VDD_FAULT +bit 289 O ? PWR_EN +bit 288 C ? SFRM_C +bit 287 O ? SFRM_C 288 0 Z +bit 286 I ? SFRM_C +bit 285 C ? SCLK_C +bit 284 O ? SCLK_C 285 0 Z +bit 283 I ? SCLK_C +bit 282 C ? RXD_C +bit 281 O ? RXD_C 282 0 Z +bit 280 I ? RXD_C +bit 279 C ? TXD_C +bit 278 O ? TXD_C 279 0 Z +bit 277 I ? TXD_C +bit 276 O ? D0 212 1 Z +bit 275 I ? D0 +bit 274 O ? D8 212 1 Z +bit 273 I ? D8 +bit 272 O ? D16 212 1 Z +bit 271 I ? D16 +bit 270 O ? D24 212 1 Z +bit 269 I ? D24 +bit 268 O ? D1 212 1 Z +bit 267 I ? D1 +bit 266 O ? D9 212 1 Z +bit 265 I ? D9 +bit 264 O ? D17 212 1 Z +bit 263 I ? D17 +bit 262 O ? D25 212 1 Z +bit 261 I ? D25 +bit 260 O ? D2 212 1 Z +bit 259 I ? D2 +bit 258 O ? D10 212 1 Z +bit 257 I ? D10 +bit 256 O ? D18 212 1 Z +bit 255 I ? D18 +bit 254 O ? D26 212 1 Z +bit 253 I ? D26 +bit 252 O ? D3 212 1 Z +bit 251 I ? D3 +bit 250 O ? D11 212 1 Z +bit 249 I ? D11 +bit 248 O ? D19 212 1 Z +bit 247 I ? D19 +bit 246 O ? D27 212 1 Z +bit 245 I ? D27 +bit 244 O ? D4 212 1 Z +bit 243 I ? D4 +bit 242 O ? D12 212 1 Z +bit 241 I ? D12 +bit 240 O ? D20 212 1 Z +bit 239 I ? D20 +bit 238 O ? D28 212 1 Z +bit 237 I ? D28 +bit 236 O ? D5 212 1 Z +bit 235 I ? D5 +bit 234 O ? D13 212 1 Z +bit 233 I ? D13 +bit 232 O ? D21 212 1 Z +bit 231 I ? D21 +bit 230 O ? D29 212 1 Z +bit 229 I ? D29 +bit 228 O ? D6 212 1 Z +bit 227 I ? D6 +bit 226 O ? D14 212 1 Z +bit 225 I ? D14 +bit 224 O ? D22 212 1 Z +bit 223 I ? D22 +bit 222 O ? D30 212 1 Z +bit 221 I ? D30 +bit 220 O ? D7 212 1 Z +bit 219 I ? D7 +bit 218 O ? D15 212 1 Z +bit 217 I ? D15 +bit 216 O ? D23 212 1 Z +bit 215 I ? D23 +bit 214 O ? D31 212 1 Z +bit 213 I ? D31 +bit 212 C ? D[31:0] +bit 211 O ? SDCLK2 +bit 210 O ? SDCKE1 +bit 209 C ? SDCLK1 +bit 208 O ? SDCLK1 209 1 Z # error (bad name) in Table 16-2 in [1] +bit 207 O ? SDCLK0 +bit 206 O ? SDCKE0 +bit 205 I ? SMROM_EN +bit 204 C ? GP27 +bit 203 O ? GP27 204 0 Z +bit 202 I ? GP27 +bit 201 C ? GP26 +bit 200 O ? GP26 201 0 Z +bit 199 I ? GP26 +bit 198 C ? GP25 +bit 197 O ? GP25 198 0 Z +bit 196 I ? GP25 +bit 195 C ? GP24 +bit 194 O ? GP24 195 0 Z +bit 193 I ? GP24 +bit 192 C ? GP23 +bit 191 O ? GP23 192 0 Z +bit 190 I ? GP23 +bit 189 C ? GP22 +bit 188 O ? GP22 189 0 Z +bit 187 I ? GP22 +bit 186 C ? GP21 +bit 185 O ? GP21 186 0 Z +bit 184 I ? GP21 +bit 183 C ? GP20 +bit 182 O ? GP20 183 0 Z +bit 181 I ? GP20 +bit 180 C ? GP19 +bit 179 O ? GP19 180 0 Z +bit 178 I ? GP19 +bit 177 C ? GP18 +bit 176 O ? GP18 177 0 Z +bit 175 I ? GP18 +bit 174 C ? GP17 +bit 173 O ? GP17 174 0 Z +bit 172 I ? GP17 +bit 171 C ? GP16 +bit 170 O ? GP16 171 0 Z +bit 169 I ? GP16 +bit 168 C ? GP15 +bit 167 O ? GP15 168 0 Z +bit 166 I ? GP15 +bit 165 C ? GP14 +bit 164 O ? GP14 165 0 Z +bit 163 I ? GP14 +bit 162 C ? GP13 +bit 161 O ? GP13 162 0 Z +bit 160 I ? GP13 +bit 159 C ? GP12 +bit 158 O ? GP12 159 0 Z +bit 157 I ? GP12 +bit 156 C ? GP11 +bit 155 O ? GP11 156 0 Z +bit 154 I ? GP11 +bit 153 C ? GP10 +bit 152 O ? GP10 153 0 Z +bit 151 I ? GP10 +bit 150 C ? GP9 +bit 149 O ? GP9 150 0 Z +bit 148 I ? GP9 +bit 147 C ? GP8 +bit 146 O ? GP8 147 0 Z +bit 145 I ? GP8 +bit 144 C ? GP7 +bit 143 O ? GP7 144 0 Z +bit 142 I ? GP7 +bit 141 C ? GP6 +bit 140 O ? GP6 141 0 Z +bit 139 I ? GP6 +bit 138 C ? GP5 +bit 137 O ? GP5 138 0 Z +bit 136 I ? GP5 +bit 135 C ? GP4 +bit 134 O ? GP4 135 0 Z +bit 133 I ? GP4 +bit 132 C ? GP3 +bit 131 O ? GP3 132 0 Z +bit 130 I ? GP3 +bit 129 C ? GP2 +bit 128 O ? GP2 129 0 Z +bit 127 I ? GP2 +bit 126 C ? GP1 +bit 125 O ? GP1 126 0 Z +bit 124 I ? GP1 +bit 123 C ? GP0 +bit 122 O ? GP0 123 0 Z +bit 121 I ? GP0 +bit 120 C ? L_BIAS +bit 119 O ? L_BIAS 120 0 Z +bit 118 I ? L_BIAS +bit 117 C ? L_PCLK +bit 116 O ? L_PCLK 117 0 Z +bit 115 I ? L_PCLK +bit 114 C ? LDD0 +bit 113 O ? LDD0 114 0 Z +bit 112 I ? LDD0 +bit 111 C ? LDD1 +bit 110 O ? LDD1 111 0 Z +bit 109 I ? LDD1 +bit 108 C ? LDD2 +bit 107 O ? LDD2 108 0 Z +bit 106 I ? LDD2 +bit 105 C ? LDD3 +bit 104 O ? LDD3 105 0 Z +bit 103 I ? LDD3 +bit 102 C ? LDD4 +bit 101 O ? LDD4 102 0 Z +bit 100 I ? LDD4 +bit 99 C ? LDD5 +bit 98 O ? LDD5 99 0 Z +bit 97 I ? LDD5 +bit 96 C ? LDD6 +bit 95 O ? LDD6 96 0 Z +bit 94 I ? LDD6 +bit 93 C ? LDD7 +bit 92 O ? LDD7 93 0 Z +bit 91 I ? LDD7 +bit 90 C ? L_LCLK +bit 89 O ? L_LCLK 90 0 Z +bit 88 I ? L_LCLK +bit 87 C ? L_FCLK +bit 86 O ? L_FCLK 87 0 Z +bit 85 I ? L_FCLK +bit 84 O ? nPOE +bit 83 O ? nPWE +bit 82 O ? nPIOR +bit 81 O ? nPIOW +bit 80 O ? PSKTSEL +bit 79 I ? nIOIS16 +bit 78 I ? nPWAIT +bit 77 O ? nPREG +bit 76 O ? nPCE2 +bit 75 O ? nPCE1 +bit 74 O ? . +bit 73 O ? nWE 74 1 Z +bit 72 O ? nOE 74 1 Z +bit 71 O ? nSDRAS 74 1 Z +bit 70 O ? nSDCAS 74 1 Z +bit 69 O ? nRAS3 +bit 68 O ? nRAS2 +bit 67 O ? nRAS1 +bit 66 O ? nRAS0 74 1 Z +bit 65 O ? nCAS3 74 1 Z +bit 64 O ? nCAS2 74 1 Z +bit 63 O ? nCAS1 74 1 Z +bit 62 O ? nCAS0 74 1 Z +bit 61 O ? RD_nWR +bit 60 I ? RDY +bit 59 O ? nCS5 +bit 58 O ? nCS4 +bit 57 O ? nCS3 +bit 56 O ? nCS2 +bit 55 O ? nCS1 +bit 54 O ? nCS0 +bit 53 O ? A25 74 1 Z +bit 52 O ? A24 74 1 Z +bit 51 O ? A23 74 1 Z +bit 50 O ? A22 74 1 Z +bit 49 O ? A21 74 1 Z +bit 48 O ? A20 74 1 Z +bit 47 O ? A19 74 1 Z +bit 46 O ? A18 74 1 Z +bit 45 O ? A17 74 1 Z +bit 44 O ? A16 74 1 Z +bit 43 O ? A15 74 1 Z +bit 42 O ? A14 74 1 Z +bit 41 O ? A13 74 1 Z +bit 40 O ? A12 74 1 Z +bit 39 O ? A11 74 1 Z +bit 38 O ? A10 74 1 Z +bit 37 O ? A9 74 1 Z +bit 36 O ? A8 74 1 Z +bit 35 O ? A7 74 1 Z +bit 34 O ? A6 74 1 Z +bit 33 O ? A5 74 1 Z +bit 32 O ? A4 74 1 Z +bit 31 O ? A3 74 1 Z +bit 30 O ? A2 74 1 Z +bit 29 O ? A1 74 1 Z +bit 28 O ? A0 74 1 Z +bit 27 C ? UDC- +bit 26 O ? UDC- 27 1 Z +bit 25 I ? UDC- +bit 24 X ? UDC-/UDC+ +bit 23 C ? UDC+ +bit 22 O ? UDC+ 23 1 Z +bit 21 I ? UDC+ +bit 20 C ? RXD_1 +bit 19 O ? RXD_1 20 0 Z +bit 18 I ? RXD_1 +bit 17 C ? TXD_1 +bit 16 O ? TXD_1 17 0 Z +bit 15 I ? TXD_1 +bit 14 C ? RXD_2 +bit 13 O ? RXD_2 14 0 Z +bit 12 I ? RXD_2 +bit 11 C ? TXD_2 +bit 10 O ? TXD_2 11 0 Z +bit 9 I ? TXD_2 +bit 8 C ? RXD_3 +bit 7 O ? RXD_3 8 0 Z +bit 6 I ? RXD_3 +bit 5 C ? TXD_3 +bit 4 O ? TXD_3 5 0 Z +bit 3 I ? TXD_3 +bit 2 I ? nRESET +bit 1 O ? nRESET_OUT +bit 0 I ? ROM_SEL