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@ -24,6 +24,11 @@
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** Jiun-Shian Ho <asky@syncom.com.tw>,
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** Copy from other bus drivers written by Marcel Telka <marcel@telka.sk>
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**
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** Krzysztof Blaszkowski <info@sysmikro.com.pl>
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** - fixed bug with driving nWBE, nECS, nSDCS (for SDRAM),
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** - fixed bug with preparing bus state after each chain_shift_data_registers().
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** tested on "peek" command only (2003/10/07).
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**
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** @brief
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** Bus driver for Samsung S3C4510X (ARM7TDMI) micro controller.
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**
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@ -59,6 +64,10 @@
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#include "buses.h"
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#ifndef DEBUG_LVL2
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#define DEBUG_LVL2(x)
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#endif
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/** @brief Bus driver for Samsung S3C4510X */
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typedef struct {
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chain_t *chain;
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@ -67,8 +76,12 @@ typedef struct {
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signal_t *d[32]; /**< Data bus */
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signal_t *nrcs[6]; /**< not ROM/SRAM/Flash Chip Select;
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** Only using nRCS0. */
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signal_t *necs[4];
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signal_t *nsdcs[4];
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signal_t *nwbe[4]; /**< not Write Byte Enable */
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signal_t *noe; /**< not Output Enable */
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int dbuswidth;
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} bus_params_t;
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#define CHAIN ((bus_params_t *) bus->params)->chain
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@ -76,12 +89,14 @@ typedef struct {
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#define A ((bus_params_t *) bus->params)->a
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#define D ((bus_params_t *) bus->params)->d
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#define nRCS ((bus_params_t *) bus->params)->nrcs
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#define nECS ((bus_params_t *) bus->params)->necs
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#define nSDCS ((bus_params_t *) bus->params)->nsdcs
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#define nWBE ((bus_params_t *) bus->params)->nwbe
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#define nOE ((bus_params_t *) bus->params)->noe
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/** @brief Width of Data Bus. Detected by B0SIZE[1:0] */
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unsigned char dbus_width = 16;
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#define dbus_width ((bus_params_t *) bus->params)->dbuswidth
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/** @brief Width of Data Bus. Detected by B0SIZE[1:0]
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unsigned char dbus_width = 16; */
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static void
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@ -125,7 +140,7 @@ s3c4510_bus_printinfo( bus_t *bus )
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for (i = 0; i < CHAIN->parts->len; i++)
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if (PART == CHAIN->parts->parts[i])
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break;
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printf( _("Samsung S3C4510B compatible bus driver via BSR (JTAG part No. %d)\n"), i );
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printf( _("Samsung S3C4510B compatibile bus driver via BSR (JTAG part No. %d) RCS0=%ubit\n"), i ,dbus_width );
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}
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static void
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@ -135,28 +150,35 @@ s3c4510_bus_prepare( bus_t *bus )
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chain_shift_instructions( CHAIN );
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}
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static void s3c4510_bus_setup_ctrl( bus_t *bus, int mode )
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{
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int k;
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part_t *p = PART;
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for (k = 0; k < 6; k++)
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part_set_signal( p, nRCS[k], 1, (mode & (1 << k)) ? 1 : 0 );
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for (k = 0; k < 4; k++)
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part_set_signal( p, nECS[k], 1, 1 );
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for (k = 0; k < 4; k++)
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part_set_signal( p, nSDCS[k], 1, 1 );
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for (k = 0; k < 4; k++)
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part_set_signal( p, nWBE[k], 1, (mode & (1 << (k + 8))) ? 1 : 0 );
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part_set_signal( p, nOE, 1, (mode & (1 << 16)) ? 1 : 0 );
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}
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static void
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s3c4510_bus_read_start( bus_t *bus, uint32_t adr )
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{
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/* see Figure 4-19 in [1] */
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part_t *p = PART;
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chain_t *chain = CHAIN;
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part_set_signal( p, nRCS[0], 1, 0 );
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part_set_signal( p, nRCS[1], 1, 1 );
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part_set_signal( p, nRCS[2], 1, 1 );
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part_set_signal( p, nRCS[3], 1, 1 );
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part_set_signal( p, nRCS[4], 1, 1 );
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part_set_signal( p, nRCS[5], 1, 1 );
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part_set_signal( p, nWBE[0], 1, 1 );
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part_set_signal( p, nWBE[1], 1, 1 );
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part_set_signal( p, nWBE[2], 1, 1 );
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part_set_signal( p, nWBE[3], 1, 1 );
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part_set_signal( p, nOE, 1, 0 );
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s3c4510_bus_setup_ctrl( bus, 0x00fffe); /* nOE=0, nRCS0 =0 */
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setup_address( bus, adr );
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set_data_in( bus );
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chain_shift_data_registers( chain, 0 );
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}
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@ -169,7 +191,9 @@ s3c4510_bus_read_next( bus_t *bus, uint32_t adr )
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int i;
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uint32_t d = 0;
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s3c4510_bus_setup_ctrl( bus, 0x00fffe); /* nOE=0, nRCS0 =0 */
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setup_address( bus, adr );
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set_data_in( bus );
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chain_shift_data_registers( chain, 1 );
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for (i = 0; i < dbus_width; i++)
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@ -187,17 +211,7 @@ s3c4510_bus_read_end( bus_t *bus )
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int i;
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uint32_t d = 0;
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part_set_signal( p, nRCS[0], 1, 1 );
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part_set_signal( p, nRCS[1], 1, 1 );
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part_set_signal( p, nRCS[2], 1, 1 );
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part_set_signal( p, nRCS[3], 1, 1 );
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part_set_signal( p, nRCS[4], 1, 1 );
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part_set_signal( p, nRCS[5], 1, 1 );
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part_set_signal( p, nWBE[0], 1, 1 );
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part_set_signal( p, nWBE[1], 1, 1 );
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part_set_signal( p, nWBE[2], 1, 1 );
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part_set_signal( p, nWBE[3], 1, 1 );
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part_set_signal( p, nOE, 1, 1 );
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s3c4510_bus_setup_ctrl( bus, 0x01ffff); /* nOE=1, nRCS0 =1 */
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chain_shift_data_registers( chain, 1 );
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for (i = 0; i < dbus_width; i++)
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@ -218,42 +232,46 @@ s3c4510_bus_read( bus_t *bus, uint32_t adr )
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** @brief
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** ROM/SRAM/FlashPage Write Access Timing
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*/
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static void
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s3c4510_bus_write( bus_t *bus, uint32_t adr, uint32_t data )
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{
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/* see Figure 4-21 in [1] */
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part_t *p = PART;
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chain_t *chain = CHAIN;
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part_set_signal( p, nRCS[0], 1, 0 );
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part_set_signal( p, nRCS[1], 1, 1 );
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part_set_signal( p, nRCS[2], 1, 1 );
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part_set_signal( p, nRCS[3], 1, 1 );
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part_set_signal( p, nRCS[4], 1, 1 );
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part_set_signal( p, nRCS[5], 1, 1 );
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part_set_signal( p, nWBE[0], 1, 1 );
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part_set_signal( p, nWBE[1], 1, 1 );
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part_set_signal( p, nWBE[2], 1, 1 );
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part_set_signal( p, nWBE[3], 1, 1 );
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part_set_signal( p, nOE, 1, 1 );
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s3c4510_bus_setup_ctrl( bus, 0x01fffe); /* nOE=1, nRCS0 =0 */
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setup_address( bus, adr );
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setup_data( bus, data );
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chain_shift_data_registers( chain, 0 );
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part_set_signal( p, nWBE[0], 1, 0 );
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switch (dbus_width)
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{
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default:
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case 8:
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s3c4510_bus_setup_ctrl( bus, 0x01fefe); /* nOE=1, nRCS0 =0, nWBE0=0 */
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break;
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case 16:
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s3c4510_bus_setup_ctrl( bus, 0x01fcfe); /* nOE=1, nRCS0 =0, nWBE0-1=0 */
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break;
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case 32:
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s3c4510_bus_setup_ctrl( bus, 0x01f0fe); /* nOE=1, nRCS0 =0, nWBE0-3=0 */
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break;
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}
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setup_address( bus, adr );
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setup_data( bus, data );
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chain_shift_data_registers( chain, 0 );
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part_set_signal( p, nWBE[0], 1, 1 );
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part_set_signal( p, nRCS[0], 1, 1 );
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part_set_signal( p, nRCS[1], 1, 1 );
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part_set_signal( p, nRCS[2], 1, 1 );
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part_set_signal( p, nRCS[3], 1, 1 );
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part_set_signal( p, nRCS[4], 1, 1 );
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part_set_signal( p, nRCS[5], 1, 1 );
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s3c4510_bus_setup_ctrl( bus, 0x01ffff); /* nOE=1, nRCS0 =1 */
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chain_shift_data_registers( chain, 0 );
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DEBUG_LVL2( printf("bus_write %08x @ %08x\n", data, adr); )
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}
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static int
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s3c4510_bus_area( bus_t *bus, uint32_t adr, bus_area_t *area )
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{
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@ -329,6 +347,8 @@ s3c4510_bus_new( void )
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return NULL;
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}
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dbus_width = 16;
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CHAIN = chain;
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PART = chain->parts->parts[chain->active_part];
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@ -359,10 +379,29 @@ s3c4510_bus_new( void )
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break;
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}
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}
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for (i = 0; i < 4; i++) {
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sprintf( buff, "nECS%d", i );
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nECS[i] = part_find_signal( PART, buff );
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if (!nECS[i]) {
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printf( _("signal '%s' not found\n"), buff );
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failed = 1;
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break;
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}
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}
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for (i = 0; i < 4; i++) {
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sprintf( buff, "nRAS%d", i ); /* those are nSDCS for SDRAMs only */
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nSDCS[i] = part_find_signal( PART, buff );
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if (!nSDCS[i]) {
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printf( _("signal '%s' not found\n"), buff );
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failed = 1;
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break;
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}
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}
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for (i = 0; i < 4; i++) {
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sprintf( buff, "nWBE%d", i );
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nWBE[i] = part_find_signal( PART, "nWBE" );
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if (!nWBE) {
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nWBE[i] = part_find_signal( PART, buff );
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if (!nWBE[i]) {
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printf( _("signal '%s' not found\n"), buff );
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failed = 1;
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break;
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@ -384,6 +423,7 @@ s3c4510_bus_new( void )
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}
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/*=============================================================================
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**
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** CVS Log
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