Temporary fixes.

urjtag/src/bus/ejtag.c

@@ -239,6 +239,10 @@ ejtag_run_pracc (urj_bus_t *bus, const uint32_t *code, unsigned int len)
         }
         else
         {
+	    /* Some older EJTAG 2.0 chips need this */
+	    if (addr == 0)
+		addr = UINT32_C (0xff200200);
+
             if (addr == UINT32_C (0xff200200) && pass++)
                 break;
 

urjtag/src/bus/ejtag_dma.c

@@ -472,6 +472,12 @@ ejtag_dma_bus_init (urj_bus_t *bus)
     ejctrl->in->data[PerRst] = 0;
     urj_tap_chain_shift_data_registers (bus->chain, 0);
 
+    // Clear Memory Protection Bit in DCR
+    urj_log (URJ_LOG_LEVEL_NORMAL, _("Clear memory protection bit in DCR\n"));
+    unsigned int val = ejtag_dma_read (bus, 0xff300000, DMA_WORD);
+
+    ejtag_dma_write (bus, 0xff300000, val & ~(1 << 2), DMA_WORD);
+
     ejctrl->in->data[PrAcc] = 1;
     ejctrl->in->data[ProbEn] = 1;
     ejctrl->in->data[ProbTrap] = 1;
@@ -507,13 +513,18 @@ ejtag_dma_bus_init (urj_bus_t *bus)
         urj_tap_chain_shift_data_registers (bus->chain, 1);
     }
 
+    // Clear watchdog, if any
 
-    // Clear Memory Protection Bit in DCR
-    urj_log (URJ_LOG_LEVEL_NORMAL, _("Clear memory protection bit in DCR\n"));
-    unsigned int val = ejtag_dma_read (bus, 0xff300000, DMA_WORD);
-    ejtag_dma_write (bus, 0xff300000, val & ~(1 << 2), DMA_WORD);
+    // Reset the processor
+    ejctrl->in->data[PrRst] = 1;
+    ejctrl->in->data[PerRst] = 1;
+    urj_tap_chain_shift_data_registers (bus->chain, 0);
+
+    // Release reset
+    ejctrl->in->data[PrRst] = 0;
+    ejctrl->in->data[PerRst] = 0;
+    urj_tap_chain_shift_data_registers (bus->chain, 0);
 
-    // Clear watchdog, if any
     urj_log (URJ_LOG_LEVEL_NORMAL, _("Clear Watchdog\n"));
     ejtag_dma_write (bus, 0xb8000080, 0, DMA_WORD);