add support for the Blackfin BF592
git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@1761 b68d4a1b-bc3d-0410-92ed-d4ac073336b7master
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#
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# $Id: STEPPINGS
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; either version 2
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# of the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
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# 02111-1307, USA.
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#
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#
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# bits 31-28 of the Device Identification Register
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0000 bf592 0
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signal GND
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signal PF1
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signal PF0
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signal XTAL
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signal CLKIN
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signal SCL
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signal SDA
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signal CLKBUF
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signal PPICLK
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signal NMIB
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signal RESETB
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signal PGB
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signal EXT_WAKE
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signal PG15
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signal PG14
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signal PG13
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signal PG12
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signal PG11
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signal PG10
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signal PG9
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signal PG8
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signal PG7
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signal PG6
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signal PG5
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signal PG4
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signal PG3
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signal PG2
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signal PG1
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signal PG0
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signal BMODE0
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signal BMODE1
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signal BMODE2
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signal TCK
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signal TDO
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signal TDI
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signal TMS
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signal TRST_B
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signal EMU
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signal PF15
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signal PF14
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signal PF13
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signal PF12
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signal PF11
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signal PF10
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signal PF9
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signal PF8
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signal VDD(0)
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signal VDD(1)
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signal VDD(2)
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signal VDD(3)
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signal VDD(4)
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signal VDD(5)
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signal PF7
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signal PF6
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signal PF5
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signal PF4
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signal EVDD(0)
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signal EVDD(1)
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signal EVDD(2)
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signal EVDD(3)
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signal EVDD(4)
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signal EVDD(5)
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signal PF3
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signal PF2
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instruction length 5
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register DIR 32
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register BSR 126
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register BYPASS 1
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instruction IDCODE 00010 DIR
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instruction SAMPLE/PRELOAD 10000 BSR
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instruction EXTEST 00000 BSR
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instruction BYPASS 11111 BYPASS
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bit 0 I ? BMODE2
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bit 1 O ? *
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bit 2 O ? *
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bit 3 I ? BMODE1
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bit 4 O ? *
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bit 5 O ? *
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bit 6 I ? BMODE0
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bit 7 O ? *
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bit 8 O ? *
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bit 9 O ? *
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bit 10 O ? *
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bit 11 O ? *
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bit 12 I ? PG0
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bit 13 O ? PG0 14 0 Z
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bit 14 C 0 *
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bit 15 I ? PG1
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bit 16 O ? PG1 17 0 Z
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bit 17 C 0 *
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bit 18 I ? PG2
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bit 19 O ? PG2 20 0 Z
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bit 20 C 0 *
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bit 21 I ? PG3
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bit 22 O ? PG3 23 0 Z
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bit 23 C 0 *
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bit 24 I ? PG4
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bit 25 O ? PG4 26 0 Z
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bit 26 C 0 *
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bit 27 I ? PG5
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bit 28 O ? PG5 29 0 Z
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bit 29 C 0 *
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bit 30 I ? PG6
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bit 31 O ? PG6 32 0 Z
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bit 32 C 0 *
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bit 33 I ? PG7
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bit 34 O ? PG7 35 0 Z
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bit 35 C 0 *
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bit 36 I ? PG8
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bit 37 O ? PG8 38 0 Z
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bit 38 C 0 *
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bit 39 I ? PG9
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bit 40 O ? PG9 41 0 Z
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bit 41 C 0 *
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bit 42 I ? PG10
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bit 43 O ? PG10 44 0 Z
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bit 44 C 0 *
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bit 45 I ? PG11
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bit 46 O ? PG11 47 0 Z
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bit 47 C 0 *
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bit 48 I ? PG12
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bit 49 O ? PG12 50 0 Z
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bit 50 C 0 *
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bit 51 I ? PG13
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bit 52 O ? PG13 53 0 Z
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bit 53 C 0 *
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bit 54 I ? PG14
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bit 55 O ? PG14 56 0 Z
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bit 56 C 0 *
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bit 57 I ? PG15
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bit 58 O ? PG15 59 0 Z
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bit 59 C 0 *
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bit 60 I ? RESETB
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bit 61 O ? *
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bit 62 O ? *
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bit 63 I ? NMIB
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bit 64 O ? *
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bit 65 O ? *
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bit 66 I ? PPICLK
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bit 67 O ? *
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bit 68 O ? *
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bit 69 O ? *
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bit 70 O ? CLKBUF 71 0 Z
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bit 71 C 0 *
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bit 72 I ? SDA
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bit 73 O ? SDA 74 0 Z
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bit 74 C 0 *
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bit 75 I ? SCL
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bit 76 O ? SCL 77 0 Z
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bit 77 C 0 *
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bit 78 I ? PF0
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bit 79 O ? PF0 80 0 Z
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bit 80 C 0 *
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bit 81 I ? PF1
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bit 82 O ? PF1 83 0 Z
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bit 83 C 0 *
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bit 84 I ? PF2
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bit 85 O ? PF2 86 0 Z
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bit 86 C 0 *
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bit 87 I ? PF3
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bit 88 O ? PF3 89 0 Z
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bit 89 C 0 *
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bit 90 I ? PF4
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bit 91 O ? PF4 92 0 Z
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bit 92 C 0 *
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bit 93 I ? PF5
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bit 94 O ? PF5 95 0 Z
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bit 95 C 0 *
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bit 96 I ? PF6
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bit 97 O ? PF6 98 0 Z
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bit 98 C 0 *
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bit 99 I ? PF7
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bit 100 O ? PF7 101 0 Z
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bit 101 C 0 *
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bit 102 I ? PF8
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bit 103 O ? PF8 104 0 Z
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bit 104 C 0 *
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bit 105 I ? PF9
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bit 106 O ? PF9 107 0 Z
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bit 107 C 0 *
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bit 108 I ? PF10
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bit 109 O ? PF10 110 0 Z
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bit 110 C 0 *
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bit 111 I ? PF11
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bit 112 O ? PF11 113 0 Z
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bit 113 C 0 *
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bit 114 I ? PF12
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bit 115 O ? PF12 116 0 Z
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bit 116 C 0 *
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bit 117 I ? PF13
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bit 118 O ? PF13 119 0 Z
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bit 119 C 0 *
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bit 120 I ? PF14
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bit 121 O ? PF14 122 0 Z
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bit 122 C 0 *
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bit 123 I ? PF15
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bit 124 O ? PF15 125 0 Z
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bit 125 C 0 *
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