2003-04-14 Marcel Telka <marcel@telka.sk>

* arm/arm.h: Added System Control Coprocessor Control Register bits.
	(PSR_MODE): Fixed bug in macro declaration.
	(PSR_MODE_MASK): Rewritten using bits() macro.


git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@421 b68d4a1b-bc3d-0410-92ed-d4ac073336b7

include/ChangeLog

@@ -1,3 +1,9 @@
+2003-04-14  Marcel Telka  <marcel@telka.sk>
+
+	* arm/arm.h: Added System Control Coprocessor Control Register bits.
+	(PSR_MODE): Fixed bug in macro declaration.
+	(PSR_MODE_MASK): Rewritten using bits() macro.
+
 2003-04-04  Marcel Telka  <marcel@telka.sk>
 
 	Version 0.2.3 released.

include/NEWS

@@ -1,5 +1,7 @@
 $Id$
 
+	* Added System Control Coprocessor Register 1 (Control Register) bits.
+
 include-0.2.3 (2003-04-04):
 
 	* Ported stdint.h to NetBSD (thanks to Jachym Holecek).

include/arm/arm.h

@@ -2,7 +2,7 @@
  * $Id$
  *
  * ARM specific declarations
- * Copyright (C) 2002 ETC s.r.o.
+ * Copyright (C) 2002, 2003 ETC s.r.o.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -28,7 +28,7 @@
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Written by Marcel Telka <marcel@telka.sk>, 2002.
+ * Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
  *
  * Documentation:
  * [1] ARM Limited, "ARM Architecture Reference Manual", June 2000,
@@ -41,19 +41,19 @@
 
 #include <common.h>
 
-/* PSR bits - see 2.5 in [1] */
+/* PSR bits - see A2.5 in [1] */
 
 #define	PSR_N		bit(31)
 #define	PSR_Z		bit(30)
 #define	PSR_C		bit(29)
 #define	PSR_V		bit(28)
-#define	PSR_Q		bit(27)		/* E variants of the ARMV5 and above - see 2.5.1 in [1] */
+#define	PSR_Q		bit(27)		/* E variants of the ARMV5 and above - see A2.5.1 in [1] */
 
 #define	PSR_I		bit(7)
 #define	PSR_F		bit(6)
 #define	PSR_T		bit(5)
-#define	PSR_MODE_MASK	0x0000001F
-#define	PSR_MODE(x)	(x & PSR_MODE_MASK)
+#define	PSR_MODE_MASK	bits(4,0)
+#define	PSR_MODE(x)	((x) & PSR_MODE_MASK)
 
 #define	PSR_MODE_USR	PSR_MODE(0x10)
 #define	PSR_MODE_FIQ	PSR_MODE(0x11)
@@ -63,4 +63,23 @@
 #define	PSR_MODE_UND	PSR_MODE(0x1B)
 #define	PSR_MODE_SYS	PSR_MODE(0x1F)	/* ARMV4 and above */
 
+/* System Control Coprocessor (SCC) Register 1: Control Register (CR) bits - see B2.4 in [1] */
+
+#define	SCC_CR_L4	bit(15)
+#define	SCC_CR_RR	bit(14)
+#define	SCC_CR_V	bit(13)
+#define	SCC_CR_I	bit(12)
+#define	SCC_CR_Z	bit(11)
+#define	SCC_CR_F	bit(10)
+#define	SCC_CR_R	bit(9)
+#define	SCC_CR_S	bit(8)
+#define	SCC_CR_B	bit(7)
+#define	SCC_CR_L	bit(6)
+#define	SCC_CR_D	bit(5)
+#define	SCC_CR_P	bit(4)
+#define	SCC_CR_W	bit(3)
+#define	SCC_CR_C	bit(2)
+#define	SCC_CR_A	bit(1)
+#define	SCC_CR_M	bit(0)
+
 #endif /* ARM_H */