From df8ac7fa89c0bd7056ffba90388acf91abd5d88f Mon Sep 17 00:00:00 2001 From: Marcel Telka Date: Mon, 4 Nov 2002 06:41:18 +0000 Subject: [PATCH] 2002-11-04 Marcel Telka * arm/pxa2x0/*: Added support for Intel PXA2x0 family processors. * arm/pxa2x0/uart.h: Fixed SPR_SP declaration, removed access to STMRS register. * arm/pxa2x0/mc.h: Fixed BOOT_DEF_OFFSET declaration. * arm/pxa2x0/gpio.h: Added ALT_FN_0_IN and ALT_FN_0_OUT declarations. * arm/pxa2x0/pmrc.h: Added missing PWER_WEx (where x = 0 through 15) declarations. * arm/pxa2x0/rtc.h: Fixed RTTR bit declarations. * NEWS: Added new file. git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@253 b68d4a1b-bc3d-0410-92ed-d4ac073336b7 --- include/ChangeLog | 10 ++ include/NEWS | 21 +++ include/arm/pxa2x0/ac97.h | 44 +++--- include/arm/pxa2x0/cm.h | 21 ++- include/arm/pxa2x0/dma.h | 12 +- include/arm/pxa2x0/gpio.h | 46 +++++- include/arm/pxa2x0/i2c.h | 14 +- include/arm/pxa2x0/i2s.h | 18 ++- include/arm/pxa2x0/ic.h | 17 ++- include/arm/pxa2x0/icp.h | 16 +- include/arm/pxa2x0/lcd.h | 28 ++-- include/arm/pxa2x0/mc.h | 58 +++++-- include/arm/pxa2x0/mmc.h | 40 ++--- include/arm/pxa2x0/ost.h | 10 +- include/arm/pxa2x0/pmrc.h | 32 +++- include/arm/pxa2x0/pwm.h | 10 +- include/arm/pxa2x0/rtc.h | 22 +-- include/arm/pxa2x0/ssp.h | 310 +++++++++++++++++++++++++++++++++++++- include/arm/pxa2x0/uart.h | 120 ++++++++++++--- include/arm/pxa2x0/udc.h | 54 +++---- 20 files changed, 720 insertions(+), 183 deletions(-) create mode 100644 include/NEWS diff --git a/include/ChangeLog b/include/ChangeLog index 0011153b..d81faea7 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,13 @@ +2002-11-04 Marcel Telka + + * arm/pxa2x0/*: Added support for Intel PXA2x0 family processors. + * arm/pxa2x0/uart.h: Fixed SPR_SP declaration, removed access to STMRS register. + * arm/pxa2x0/mc.h: Fixed BOOT_DEF_OFFSET declaration. + * arm/pxa2x0/gpio.h: Added ALT_FN_0_IN and ALT_FN_0_OUT declarations. + * arm/pxa2x0/pmrc.h: Added missing PWER_WEx (where x = 0 through 15) declarations. + * arm/pxa2x0/rtc.h: Fixed RTTR bit declarations. + * NEWS: Added new file. + 2002-11-02 Marcel Telka * arm/pxa2x0/*: Added _t suffix for register type names. diff --git a/include/NEWS b/include/NEWS new file mode 100644 index 00000000..3f4bca4b --- /dev/null +++ b/include/NEWS @@ -0,0 +1,21 @@ +Changes in include since version 0.1: + + * Added support for Intel PXA26x family processors. + * Changes in PXA2x0 support: + - removed access to STMRS register + - fixed SPR_SP declaration + - fixed BOOT_DEF_OFFSET declaration + - added _t suffix for register type names + - added ALT_FN_0_IN and ALT_FN_0_OUT declarations + - added missing PWER_WEx (where x = 0 through 15) declarations + - fixed RTTR bit declarations + * Changes in SA11x0 support: + - added _t suffix for register type names + * Removed _t suffix from structure names in CFI declarations. + +include-0.1 (2002-11-01): + + * Initial public release with intial support for Intel SA-11x0/PXA2x0 + processors, Common Flash Interface (CFI), Intel extensions to CFI, + JEDEC Manufacturer's Identification Codes, base AC'97 declarations + and Philips UCB1400 support. diff --git a/include/arm/pxa2x0/ac97.h b/include/arm/pxa2x0/ac97.h index b9accd8e..803f650b 100644 --- a/include/arm/pxa2x0/ac97.h +++ b/include/arm/pxa2x0/ac97.h @@ -1,7 +1,7 @@ /* * $Id$ * - * XScale PXA250/PXA210 AC97 Registers + * XScale PXA26x/PXA250/PXA210 AC97 Registers * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * @@ -33,6 +33,8 @@ * Documentation: * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", + * October 2002, Order Number: 278638-001 * */ @@ -101,10 +103,10 @@ typedef volatile struct AC97_registers { #define MOSR AC97_pointer->mosr #define MISR AC97_pointer->misr #define MODR AC97_pointer->modr -#define __PACR(r) AC97_pointer->__pacr[r >> 1] -#define __SACR(r) AC97_pointer->__sacr[r >> 1] -#define __PMCR(r) AC97_pointer->__pmcr[r >> 1] -#define __SMCR(r) AC97_pointer->__smcr[r >> 1] +#define __PACR(r) AC97_pointer->__pacr[(r) >> 1] +#define __SACR(r) AC97_pointer->__sacr[(r) >> 1] +#define __PMCR(r) AC97_pointer->__pmcr[(r) >> 1] +#define __SMCR(r) AC97_pointer->__smcr[(r) >> 1] #endif /* LANGUAGE == C */ #define POCR_OFFSET 0x000 @@ -124,19 +126,19 @@ typedef volatile struct AC97_registers { #define MISR_OFFSET 0x118 #define MODR_OFFSET 0x140 -/* POCR bits - see Table 13-50 in [1] */ +/* POCR bits - see Table 13-50 in [1], Table 13-10 in [2] */ #define POCR_FEIE bit(3) -/* PICR bits - see Table 13-51 in [1] */ +/* PICR bits - see Table 13-51 in [1], Table 13-11 in [2] */ #define PICR_FEIE bit(3) -/* MCCR bits - see Table 13-56 in [1] */ +/* MCCR bits - see Table 13-56 in [1], Table 13-16 in [2] */ #define MCCR_FEIE bit(3) -/* GCR bits - see Table 13-48 in [1] */ +/* GCR bits - see Table 13-48 in [1], Table 13-8 in [2] */ #define GCR_CDONE_IE bit(19) #define GCR_SDONE_IE bit(18) @@ -149,19 +151,19 @@ typedef volatile struct AC97_registers { #define GCR_COLD_RST bit(1) #define GCR_GIE bit(0) -/* POSR bits - see Table 13-52 in [1] */ +/* POSR bits - see Table 13-52 in [1], Table 13-12 in [2] */ #define POSR_FIFOE bit(4) -/* PISR bits - see Table 13-53 in [1] */ +/* PISR bits - see Table 13-53 in [1], Table 13-13 in [2] */ #define PISR_FIFOE bit(4) -/* MCSR bits - see Table 13-57 in [1] */ +/* MCSR bits - see Table 13-57 in [1], Table 13-17 in [2] */ #define MCSR_FIFOE bit(4) -/* GSR bits - see Table 13-49 in [1] */ +/* GSR bits - see Table 13-49 in [1], Table 13-9 in [2] */ #define GSR_CDONE bit(19) #define GSR_SDONE bit(18) @@ -180,39 +182,39 @@ typedef volatile struct AC97_registers { #define GSR_MIINT bit(1) #define GSR_GSCI bit(0) -/* CAR bits - see Table 13-54 in [1] */ +/* CAR bits - see Table 13-54 in [1], Table 13-14 in [2] */ #define CAR_CAIP bit(0) -/* PCDR bits - see Table 13-55 in [1] */ +/* PCDR bits - see Table 13-55 in [1], Table 13-15 in [2] */ #define PCDR_PCM_RDATA_MASK bits(31,16) #define PCDR_PCM_RDATA(x) bits_val(31,16,x) #define PCDR_PCM_LDATA_MASK bits(15,0) #define PCDR_PCM_LDATA(x) bits_val(15,0,x) -/* MCDR bits - see Table 13-58 in [1] */ +/* MCDR bits - see Table 13-58 in [1], Table 13-18 in [2] */ #define MCDR_MIC_IN_DAT_MASK bits(15,0) #define MCDR_MIC_IN_DAT(x) bits_val(15,0,x) -/* MOCR bits - see Table 13-59 in [1] */ +/* MOCR bits - see Table 13-59 in [1], Table 13-19 in [2] */ #define MOCR_FEIE bit(3) -/* MICR bits - see Table 13-60 in [1] */ +/* MICR bits - see Table 13-60 in [1], Table 13-20 in [2] */ #define MICR_FEIE bit(3) -/* MOSR bits - see Table 13-61 in [1] */ +/* MOSR bits - see Table 13-61 in [1], Table 13-21 in [2] */ #define MOSR_FIFOE bit(4) -/* MISR bits - see Table 16-62 in [1] */ +/* MISR bits - see Table 16-62 in [1], Table 13-22 in [2] */ #define MISR_FIFOE bit(4) -/* MODR bits - see Table 16-63 in [1] */ +/* MODR bits - see Table 16-63 in [1], Table 13-23 in [2] */ #define MODR_MODEM_DAT_MASK bits(15,0) #define MODR_MODEM_DAT(x) bits_val(15,0,x) diff --git a/include/arm/pxa2x0/cm.h b/include/arm/pxa2x0/cm.h index 0dd0816a..2d61a6ca 100644 --- a/include/arm/pxa2x0/cm.h +++ b/include/arm/pxa2x0/cm.h @@ -1,7 +1,7 @@ /* * $Id$ * - * XScale PXA250/PXA210 Clocks Manager Registers + * XScale PXA26x/PXA250/PXA210 Clocks Manager Registers * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * @@ -33,6 +33,8 @@ * Documentation: * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", + * October 2002, Order Number: 278638-001 * */ @@ -45,6 +47,10 @@ #include #endif +#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA26X) +#define PXA2X0_NOPXA26X +#endif + /* Clocks Manager Registers */ #define CM_BASE 0x41300000 @@ -69,7 +75,7 @@ typedef volatile struct CM_registers { #define CKEN_OFFSET 0x04 #define OSCC_OFFSET 0x08 -/* CCCR bits - see Table 3-20 in [1] */ +/* CCCR bits - see Table 3-20 in [1], Table 3-20 in [2] */ #define CCCR_N_MASK bits(9,7) #define CCCR_N(x) bits_val(9,7,x) @@ -92,23 +98,30 @@ typedef volatile struct CM_registers { #define CCCR_L_40 CCCR_L(0x04) #define CCCR_L_45 CCCR_L(0x05) -/* CKEN bits - see Table 3-21 in [1] */ +/* CKEN bits - see Table 3-21 in [1], Table 3-21 in [2] */ #define CKEN_CKEN16 bit(16) #define CKEN_CKEN14 bit(14) #define CKEN_CKEN13 bit(13) #define CKEN_CKEN12 bit(12) #define CKEN_CKEN11 bit(11) +#if !defined(PXA2X0_NOPXA26X) +#define CKEN_CKEN10 bit(10) +#define CKEN_CKEN9 bit(9) +#endif /* PXA26x only */ #define CKEN_CKEN8 bit(8) #define CKEN_CKEN7 bit(7) #define CKEN_CKEN6 bit(6) #define CKEN_CKEN5 bit(5) +#if !defined(PXA2X0_NOPXA26X) +#define CKEN_CKEN10 bit(4) +#endif /* PXA26x only */ #define CKEN_CKEN3 bit(3) #define CKEN_CKEN2 bit(2) #define CKEN_CKEN1 bit(1) #define CKEN_CKEN0 bit(0) -/* OSCC bits - see Table 3-22 in [1] */ +/* OSCC bits - see Table 3-22 in [1], Table 3-22 in [2] */ #define OSCC_OON bit(1) #define OSCC_OOK bit(0) diff --git a/include/arm/pxa2x0/dma.h b/include/arm/pxa2x0/dma.h index d584eed8..dcd35939 100644 --- a/include/arm/pxa2x0/dma.h +++ b/include/arm/pxa2x0/dma.h @@ -1,7 +1,7 @@ /* * $Id$ * - * XScale PXA250/PXA210 DMA Controller Registers + * XScale PXA26x/PXA250/PXA210 DMA Controller Registers * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * @@ -33,6 +33,8 @@ * Documentation: * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", + * October 2002, Order Number: 278638-001 * */ @@ -88,7 +90,7 @@ typedef volatile struct DMA_registers { #define DTADR_OFFSET(i) (0x208 + ((i) << 4)) #define DCMD_OFFSET(i) (0x20C + ((i) << 4)) -/* DCSRx bits - see Table 5-7 in [1] */ +/* DCSRx bits - see Table 5-7 in [1], Table 5-7 in [2] */ #define DCSR_RUN bit(31) #define DCSR_NODESCFETCH bit(30) @@ -99,17 +101,17 @@ typedef volatile struct DMA_registers { #define DCSR_STARTINTR bit(1) #define DSCR_BUSERRINTR bit(0) -/* DRCMRx bits - see Table 5-8 in [1] */ +/* DRCMRx bits - see Table 5-8 in [1], Table 5-8 in [2] */ #define DRCMR_MAPVLD bit(7) #define DRCMR_CHLNUM_MASK bits(3,0) #define DRCMR_CHLNUM(x) bits_val(3,0,x) -/* DDADRx bits - see Table 5-9 in [1] */ +/* DDADRx bits - see Table 5-9 in [1], Table 5-9 in [2] */ #define DDADR_STOP bit(0) -/* DCMDx bits - see Table 5-12 in [1] */ +/* DCMDx bits - see Table 5-12 in [1], Table 5-12 in [2] */ #define DCMD_INCSRCADDR bit(31) #define DCMD_INCTRGADDR bit(30) diff --git a/include/arm/pxa2x0/gpio.h b/include/arm/pxa2x0/gpio.h index 5ce89ad9..01d32f0b 100644 --- a/include/arm/pxa2x0/gpio.h +++ b/include/arm/pxa2x0/gpio.h @@ -1,7 +1,7 @@ /* * $Id$ * - * XScale PXA250/PXA210 GPIO Registers + * XScale PXA26x/PXA250/PXA210 GPIO Registers * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * @@ -33,6 +33,8 @@ * Documentation: * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", + * October 2002, Order Number: 278638-001 * */ @@ -45,6 +47,10 @@ #include #endif +#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA26X) +#define PXA2X0_NOPXA26X +#endif + /* GPIO Registers */ #define GPIO_BASE 0x40E00000 @@ -224,18 +230,31 @@ typedef volatile struct GPIO_registers { #define GPIO2_GP78 bit(14) #define GPIO2_GP79 bit(15) #define GPIO2_GP80 bit(16) +#if !defined(PXA2X0_NOPXA26X) +#define GPIO2_GP81 bit(17) +#define GPIO2_GP82 bit(18) +#define GPIO2_GP83 bit(19) +#define GPIO2_GP84 bit(20) +#define GPIO2_GP85 bit(21) +#define GPIO2_GP86 bit(22) +#define GPIO2_GP87 bit(23) +#define GPIO2_GP88 bit(24) +#define GPIO2_GP89 bit(25) +#endif /* PXA26x only */ -/* GAFR constants - see 4.1.3.6 in [1] */ +/* GAFR constants - see 4.1.3.6 in [1], 4.1.3.6 in [2] */ #define ALT_FN_MASK 3 +#define ALT_FN_0_IN 0 #define ALT_FN_1_IN 1 #define ALT_FN_2_IN 2 #define ALT_FN_3_IN 3 +#define ALT_FN_0_OUT 0 #define ALT_FN_1_OUT 1 #define ALT_FN_2_OUT 2 #define ALT_FN_3_OUT 3 -/* GAFR0_L bits - see Table 4-24 in [1] */ +/* GAFR0_L bits - see Table 4-24 in [1], Table 4-24 in [2] */ #define GAFR0_L_AF0(x) ((x) & ALT_FN_MASK) #define GAFR0_L_AF1(x) (((x) & ALT_FN_MASK) << 2) @@ -254,7 +273,7 @@ typedef volatile struct GPIO_registers { #define GAFR0_L_AF14(x) (((x) & ALT_FN_MASK) << 28) #define GAFR0_L_AF15(x) (((x) & ALT_FN_MASK) << 30) -/* GAFR0_U bits - see Table 4-25 in [1] */ +/* GAFR0_U bits - see Table 4-25 in [1], Table 4-25 in [2] */ #define GAFR0_U_AF16(x) ((x) & ALT_FN_MASK) #define GAFR0_U_AF17(x) (((x) & ALT_FN_MASK) << 2) @@ -273,7 +292,7 @@ typedef volatile struct GPIO_registers { #define GAFR0_U_AF30(x) (((x) & ALT_FN_MASK) << 28) #define GAFR0_U_AF31(x) (((x) & ALT_FN_MASK) << 30) -/* GAFR1_L bits - see Table 4-26 in [1] */ +/* GAFR1_L bits - see Table 4-26 in [1], Table 4-26 in [2] */ #define GAFR1_L_AF32(x) ((x) & ALT_FN_MASK) #define GAFR1_L_AF33(x) (((x) & ALT_FN_MASK) << 2) @@ -292,7 +311,7 @@ typedef volatile struct GPIO_registers { #define GAFR1_L_AF46(x) (((x) & ALT_FN_MASK) << 28) #define GAFR1_L_AF47(x) (((x) & ALT_FN_MASK) << 30) -/* GAFR1_U bits - see Table 4-27 in [1] */ +/* GAFR1_U bits - see Table 4-27 in [1], Table 4-27 in [2] */ #define GAFR1_U_AF48(x) ((x) & ALT_FN_MASK) #define GAFR1_U_AF49(x) (((x) & ALT_FN_MASK) << 2) @@ -311,7 +330,7 @@ typedef volatile struct GPIO_registers { #define GAFR1_U_AF62(x) (((x) & ALT_FN_MASK) << 28) #define GAFR1_U_AF63(x) (((x) & ALT_FN_MASK) << 30) -/* GAFR2_L bits - see Table 4-28 in [1] */ +/* GAFR2_L bits - see Table 4-28 in [1], Table 4-28 in [2] */ #define GAFR2_L_AF64(x) ((x) & ALT_FN_MASK) #define GAFR2_L_AF65(x) (((x) & ALT_FN_MASK) << 2) @@ -330,8 +349,19 @@ typedef volatile struct GPIO_registers { #define GAFR2_L_AF78(x) (((x) & ALT_FN_MASK) << 28) #define GAFR2_L_AF79(x) (((x) & ALT_FN_MASK) << 30) -/* GAFR2_U bits - see Table 4-29 in [1] */ +/* GAFR2_U bits - see Table 4-29 in [1], Table 4-29 in [2] */ #define GAFR2_U_AF80(x) ((x) & ALT_FN_MASK) +#if !defined(PXA2X0_NOPXA26X) +#define GAFR2_U_AF81(x) (((x) & ALT_FN_MASK) << 2) +#define GAFR2_U_AF82(x) (((x) & ALT_FN_MASK) << 4) +#define GAFR2_U_AF83(x) (((x) & ALT_FN_MASK) << 6) +#define GAFR2_U_AF84(x) (((x) & ALT_FN_MASK) << 8) +#define GAFR2_U_AF85(x) (((x) & ALT_FN_MASK) << 10) +#define GAFR2_U_AF86(x) (((x) & ALT_FN_MASK) << 12) +#define GAFR2_U_AF87(x) (((x) & ALT_FN_MASK) << 14) +#define GAFR2_U_AF88(x) (((x) & ALT_FN_MASK) << 16) +#define GAFR2_U_AF89(x) (((x) & ALT_FN_MASK) << 18) +#endif /* PXA26x only */ #endif /* PXA2X0_GPIO_H */ diff --git a/include/arm/pxa2x0/i2c.h b/include/arm/pxa2x0/i2c.h index 6740ca37..7f74c9ab 100644 --- a/include/arm/pxa2x0/i2c.h +++ b/include/arm/pxa2x0/i2c.h @@ -1,7 +1,7 @@ /* * $Id$ * - * XScale PXA250/PXA210 I2C Registers + * XScale PXA26x/PXA250/PXA210 I2C Registers * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * @@ -33,6 +33,8 @@ * Documentation: * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", + * October 2002, Order Number: 278638-001 * */ @@ -80,17 +82,17 @@ typedef volatile struct I2C_registers { #define ISR_OFFSET 0x1698 #define ISAR_OFFSET 0x16A0 -/* IBMR bits - see Table 9-9 in [1] */ +/* IBMR bits - see Table 9-9 in [1], Table 9-9 in [2] */ #define IBMR_SCLS bit(1) #define IBMR_SDAS bit(0) -/* IDBR bits - see Table 9-10 in [1] */ +/* IDBR bits - see Table 9-10 in [1], Table 9-10 in [2] */ #define IDBR_IDB_MASK bits(7,0) #define IDBR_IDB(x) bits_val(7,0,x) -/* ICR bits - see Table 9-11 in [1] */ +/* ICR bits - see Table 9-11 in [1], Table 9-11 in [2] */ #define ICR_FM bit(15) #define ICR_UR bit(14) @@ -109,7 +111,7 @@ typedef volatile struct I2C_registers { #define ICR_STOP bit(1) #define ICR_START bit(0) -/* ISR bits - see Table 9-12 in [1] */ +/* ISR bits - see Table 9-12 in [1], Table 9-12 in [2] */ #define ISR_BED bit(10) #define ISR_SAD bit(9) @@ -123,7 +125,7 @@ typedef volatile struct I2C_registers { #define ISR_ACKNAK bit(1) #define ISR_RWM bit(0) -/* ISAR bits - see Table 9-13 in [1] */ +/* ISAR bits - see Table 9-13 in [1], Table 9-13 in [2] */ #define ISAR_ISA_MASK bits(6,0) #define ISAR_ISA(x) bits_val(6,0,x) diff --git a/include/arm/pxa2x0/i2s.h b/include/arm/pxa2x0/i2s.h index 2c8b4022..0eaf72d9 100644 --- a/include/arm/pxa2x0/i2s.h +++ b/include/arm/pxa2x0/i2s.h @@ -1,7 +1,7 @@ /* * $Id$ * - * XScale PXA250/PXA210 I2S Registers + * XScale PXA26x/PXA250/PXA210 I2S Registers * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * @@ -33,6 +33,8 @@ * Documentation: * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", + * October 2002, Order Number: 278638-001 * */ @@ -85,7 +87,7 @@ typedef volatile struct I2S_registers { #define SADIV_OFFSET 0x60 #define SADR_OFFSET 0x80 -/* SACR0 bits - see Table 14-3 in [1] */ +/* SACR0 bits - see Table 14-3 in [1], Table 14-3 in [2] */ #define SACR0_RFTH_MASK bits(15,12) #define SACR0_RFTH(x) bits_val(15,12,x) @@ -97,14 +99,14 @@ typedef volatile struct I2S_registers { #define SACR0_BCKD bit(2) #define SACR0_ENB bit(0) -/* SACR1 bits - see Table 14-6 in [1] */ +/* SACR1 bits - see Table 14-6 in [1], Table 14-6 in [2] */ #define SACR1_ENLBF bit(5) #define SACR1_DRPL bit(4) #define SACR1_DREC bit(3) #define SACR1_AMSL bit(0) -/* SASR0 bits - see Table 14-7 in [1] */ +/* SASR0 bits - see Table 14-7 in [1], Table 14-7 in [2] */ #define SASR0_RFL_MASK bits(15,12) #define SASR0_RFL(x) bits_val(15,12,x) @@ -118,24 +120,24 @@ typedef volatile struct I2S_registers { #define SASR0_RNE bit(1) #define SASR0_TNF bit(0) -/* SAIMR bits - see Table 14-10 in [1] */ +/* SAIMR bits - see Table 14-10 in [1], Table 14-10 in [2] */ #define SAIMR_ROR bit(6) #define SAIMR_TUR bit(5) #define SAIMR_RFS bit(4) #define SAIMR_TFS bit(3) -/* SAICR bits - see Table 14-9 in [1] */ +/* SAICR bits - see Table 14-9 in [1], Table 14-9 in [2] */ #define SAICR_ROR bit(6) #define SAICR_TUR bit(5) -/* SADIV bits - see Table 14-8 in [1] */ +/* SADIV bits - see Table 14-8 in [1], Table 14-8 in [2] */ #define SADIV_SADIV_MASK bits(6,0) #define SADIV_SADIV(x) bits_val(6,0,x) -/* SADR bits - see Table 14-11 in [1] */ +/* SADR bits - see Table 14-11 in [1], Table 14-11 in [2] */ #define SADR_DTH_MASK bits(31,16) #define SADR_DTH(x) bits_val(31,16,x) diff --git a/include/arm/pxa2x0/ic.h b/include/arm/pxa2x0/ic.h index c021760f..7455d434 100644 --- a/include/arm/pxa2x0/ic.h +++ b/include/arm/pxa2x0/ic.h @@ -1,7 +1,7 @@ /* * $Id$ * - * XScale PXA250/PXA210 Interrupt Control Registers + * XScale PXA26x/PXA250/PXA210 Interrupt Control Registers * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * @@ -33,6 +33,8 @@ * Documentation: * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", + * October 2002, Order Number: 278638-001 * */ @@ -45,6 +47,10 @@ #include #endif +#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA26X) +#define PXA2X0_NOPXA26X +#endif + /* Interrupt Control Registers */ #define IC_BASE 0x40D00000 @@ -95,6 +101,10 @@ typedef volatile struct IC_registers { #define IC_IRQ19 bit(19) #define IC_IRQ18 bit(18) #define IC_IRQ17 bit(17) +#if !defined(PXA2X0_NOPXA26X) +#define IC_IRQ16 bit(16) +#define IC_IRQ15 bit(15) +#endif /* PXA26x only */ #define IC_IRQ14 bit(14) #define IC_IRQ13 bit(13) #define IC_IRQ12 bit(12) @@ -102,8 +112,11 @@ typedef volatile struct IC_registers { #define IC_IRQ10 bit(10) #define IC_IRQ9 bit(9) #define IC_IRQ8 bit(8) +#if !defined(PXA2X0_NOPXA26X) +#define IC_IRQ7 bit(7) +#endif /* PXA26x only */ -/* ICCR bits - see Table 4-33 in [1] */ +/* ICCR bits - see Table 4-33 in [1], Table in [2] */ #define ICCR_DIM bit(0) diff --git a/include/arm/pxa2x0/icp.h b/include/arm/pxa2x0/icp.h index 24601417..d69d8ccc 100644 --- a/include/arm/pxa2x0/icp.h +++ b/include/arm/pxa2x0/icp.h @@ -1,7 +1,7 @@ /* * $Id$ * - * XScale PXA250/PXA210 ICP Registers + * XScale PXA26x/PXA250/PXA210 ICP Registers * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * @@ -33,6 +33,8 @@ * Documentation: * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", + * October 2002, Order Number: 278638-001 * */ @@ -79,7 +81,7 @@ typedef volatile struct ICP_registers { #define ICSR0_OFFSET 0x14 #define ICSR1_OFFSET 0x18 -/* ICCR0 bits - see Table 11-2 in [1] */ +/* ICCR0 bits - see Table 11-2 in [1], Table 11-2 in [2] */ #define ICCR0_AME bit(7) #define ICCR0_TIE bit(6) @@ -90,24 +92,24 @@ typedef volatile struct ICP_registers { #define ICCR0_LBM bit(1) #define ICCR0_ITR bit(0) -/* ICCR1 bits - see Table 11-3 in [1] */ +/* ICCR1 bits - see Table 11-3 in [1], Table 11-3 in [2] */ #define ICCR1_AMV_MASK bits(7,0) #define ICCR1_AMV(x) bits_val(7,0,x) -/* ICCR2 bits - see Table 11-4 in [1] */ +/* ICCR2 bits - see Table 11-4 in [1], Table 11-4 in [2] */ #define ICCR2_RXP bit(3) #define ICCR2_TXP bit(2) #define ICCR2_TRIG_MASK bits(1,0) #define ICCR2_TRIG(x) bits_val(1,0,x) -/* ICDR bits - see Table 11-5 in [1] */ +/* ICDR bits - see Table 11-5 in [1], Table 11-5 in [2] */ #define ICDR_DATA_MASK bits(7,0) #define ICDR_DATA(x) bits_val(7,0,x) -/* ICSR0 bits - see Table 11-6 in [1] */ +/* ICSR0 bits - see Table 11-6 in [1], Table 11-6 in [2] */ #define ICSR0_FRE bit(5) #define ICSR0_RFS bit(4) @@ -116,7 +118,7 @@ typedef volatile struct ICP_registers { #define ICSR0_TUR bit(1) #define ICSR0_EIF bit(0) -/* ICSR1 bits - see Table 11-7 in [1] */ +/* ICSR1 bits - see Table 11-7 in [1], Table 11-7 in [2] */ #define ICSR1_ROR bit(6) #define ICSR1_CRE bit(5) diff --git a/include/arm/pxa2x0/lcd.h b/include/arm/pxa2x0/lcd.h index 8d428fb0..a27a3daf 100644 --- a/include/arm/pxa2x0/lcd.h +++ b/include/arm/pxa2x0/lcd.h @@ -1,7 +1,7 @@ /* * $Id$ * - * XScale PXA250/PXA210 LCD Controller Registers + * XScale PXA26x/PXA250/PXA210 LCD Controller Registers * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * @@ -33,6 +33,8 @@ * Documentation: * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", + * October 2002, Order Number: 278638-001 * */ @@ -115,7 +117,7 @@ typedef volatile struct LCD_registers { #define FIDR1_OFFSET 0x218 #define LDCMD1_OFFSET 0x21C -/* LCCR0 bits - see Table 7-2 in [1] */ +/* LCCR0 bits - see Table 7-2 in [1], Table 7-2 in [2] */ #define LCCR0_OUM bit(21) #define LCCR0_BM bit(20) @@ -133,7 +135,7 @@ typedef volatile struct LCD_registers { #define LCCR0_CMS bit(1) #define LCCR0_ENB bit(0) -/* LCCR1 bits - see Table 7-5 in [1] */ +/* LCCR1 bits - see Table 7-5 in [1], Table 7-4 in [2] */ #define LCCR1_BLW_MASK bits(31,24) #define LCCR1_BLW(x) bits_val(31,24,x) @@ -144,7 +146,7 @@ typedef volatile struct LCD_registers { #define LCCR1_PPL_MASK bits(9,0) #define LCCR1_PPL(x) bits_val(9,0,x) -/* LCCR2 bits - see Table 7-6 in [1] */ +/* LCCR2 bits - see Table 7-6 in [1], Table 7-5 in [2] */ #define LCCR2_BFW_MASK bits(31,24) #define LCCR2_BFW(x) bits_val(31,24,x) @@ -155,7 +157,7 @@ typedef volatile struct LCD_registers { #define LCCR2_LPP_MASK bits(9,0) #define LCCR2_LPP(x) bits_val(9,0,x) -/* LCCR3 bits - see Table 7-7 in [1] */ +/* LCCR3 bits - see Table 7-7 in [1], Table 7-6 in [2] */ #define LCCR3_DPC bit(27) #define LCCR3_BPP_MASK bits(26,24) @@ -171,17 +173,17 @@ typedef volatile struct LCD_registers { #define LCCR3_PCD_MASK bits(7,0) #define LCCR3_PCD(x) bits_val(7,0,x) -/* FBR0 bits - see Table 7-12 in [1] */ +/* FBR0 bits - see Table 7-12 in [1], Table 7-11 in [2] */ #define FBR0_BINT bit(1) #define FBR0_BRA bit(0) -/* FBR1 bits - see Table 7-12 in [1] */ +/* FBR1 bits - see Table 7-12 in [1], Table 7-11 in [2] */ #define FBR1_BINT bit(1) #define FBR1_BRA bit(0) -/* LCSR bits - see Table 7-13 in [1] */ +/* LCSR bits - see Table 7-13 in [1], Table 7-12 in [2] */ #define LCSR_SINT bit(10) #define LCSR_BS bit(9) @@ -195,12 +197,12 @@ typedef volatile struct LCD_registers { #define LCSR_SOF bit(1) #define LCSR_LDD bit(0) -/* LIIDR bits - see Table 7-14 in [1] */ +/* LIIDR bits - see Table 7-14 in [1], Table 7-13 in [2] */ #define LIIDR_IFRAMEID_MASK bits(31,3) #define LIIDR_IFRAMEID(x) bits_val(31,3,x) -/* TRGBR bits - see Table 7-15 in [1] */ +/* TRGBR bits - see Table 7-15 in [1], Table 7-14 in [2] */ #define TRGBR_TBS_MASK bits(23,16) #define TRGBR_TBS(x) bits_val(23,16,x) @@ -209,7 +211,7 @@ typedef volatile struct LCD_registers { #define TRGBR_TRS_MASK bits(7,0) #define TRGBR_TRS(x) bits_val(7,0,x) -/* TCR bits - see Table 7-16 in [1] */ +/* TCR bits - see Table 7-16 in [1], Table 7-15 in [2] */ #define TCR_TED bit(14) #define TCR_THBS_MASK bits(11,8) @@ -221,7 +223,7 @@ typedef volatile struct LCD_registers { #define TCR_FNAM bit(1) #define TCR_COAM bit(0) -/* LDCMD0 bits - see Table 7-11 in [1] */ +/* LDCMD0 bits - see Table 7-11 in [1], Table 7-10 in [2] */ #define LDCMD0_PAL bit(26) #define LDCMD0_SOFINT bit(22) @@ -229,7 +231,7 @@ typedef volatile struct LCD_registers { #define LDCMD0_LEN_MASK bits(20,0) #define LDCMD0_LEN(x) bits_val(20,0,x) -/* LDCMD1 bits - see Table 7-11 in [1] */ +/* LDCMD1 bits - see Table 7-11 in [1], Table 7-10 in [2] */ #define LDCMD1_PAL bit(26) #define LDCMD1_SOFINT bit(22) diff --git a/include/arm/pxa2x0/mc.h b/include/arm/pxa2x0/mc.h index eaaad550..ccd225c9 100644 --- a/include/arm/pxa2x0/mc.h +++ b/include/arm/pxa2x0/mc.h @@ -1,7 +1,7 @@ /* * $Id$ * - * XScale PXA250/PXA210 Memory Controller Registers + * XScale PXA26x/PXA250/PXA210 Memory Controller Registers * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * @@ -34,7 +34,9 @@ * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors * Developer's Manual", February 2002, Order Number: 278522-001 * [2] Intel Corporation, "Intel PXA250 and PXA210 Application Processors - * Specification Update", June 2002, Order Number: 278534-007 + * Specification Update", October 2002, Order Number: 278534-009 + * [3] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", + * October 2002, Order Number: 278638-001 * */ @@ -47,6 +49,10 @@ #include #endif +#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA26X) +#define PXA2X0_NOPXA26X +#endif + /* Memory Controller Registers */ #define MC_BASE 0x48000000 @@ -71,6 +77,12 @@ typedef volatile struct MC_registers { uint32_t mcio1; uint32_t mdmrs; uint32_t boot_def; +#if !defined(PXA2X0_NOPXA26X) + uint32_t __reserved3[4]; + uint32_t mdmrslp; + uint32_t __reserved4[2]; + uint32_t sa1111cr; +#endif /* PXA26x only */ } MC_registers_t; #ifdef PXA2X0_UNMAPPED @@ -93,6 +105,10 @@ typedef volatile struct MC_registers { #define MCIO1 MC_pointer->mcio1 #define MDMRS MC_pointer->mdmrs #define BOOT_DEF MC_pointer->boot_def +#if !defined(PXA2X0_NOPXA26X) +#define MDMRSLP MC_pointer->mdmrslp +#define SA1111CR MC_pointer->sa1111cr +#endif /* PXA26x only */ #endif /* LANGUAGE == C */ #define MDCNFG_OFFSET 0x00 @@ -110,9 +126,13 @@ typedef volatile struct MC_registers { #define MCIO0_OFFSET 0x38 #define MCIO1_OFFSET 0x3C #define MDMRS_OFFSET 0x40 -#define BOOT_DEF 0x44 +#define BOOT_DEF_OFFSET 0x44 +#if !defined(PXA2X0_NOPXA26X) +#define MDMRSLP_OFFSET 0x58 +#define SA1111CR_OFFSET 0x64 +#endif /* PXA26x only */ -/* MDCNFG bits - see Table 6-3 in [1] and D25. in [2] */ +/* MDCNFG bits - see Table 6-3 in [1] and D25 in [2], Table 6-3 in [3] */ #define MDCNFG_DSA1111_2 bit(28) #define MDCNFG_DLATCH2 bit(27) @@ -139,7 +159,7 @@ typedef volatile struct MC_registers { #define MDCNFG_DE1 bit(1) #define MDCNFG_DE0 bit(0) -/* MDREFR bits - see Table 6-5 in [1] */ +/* MDREFR bits - see Table 6-5 in [1], Table 6-6 in [3] */ #define MDREFR_K2FREE bit(25) #define MDREFR_K1FREE bit(24) @@ -157,7 +177,7 @@ typedef volatile struct MC_registers { #define MDREFR_DRI_MASK bits(11,0) #define MDREFR_DRI(x) bits_val(11,0,x) -/* MSC0 bits - see Table 6-21 in [1] */ +/* MSC0 bits - see Table 6-21 in [1], Table 6-25 in [3] */ #define MSC0_RBUFF1 bit(31) #define MSC0_RRR1_MASK bits(30,28) @@ -180,7 +200,7 @@ typedef volatile struct MC_registers { #define MSC0_RT0_MASK bits(2,0) #define MSC0_RT0(x) bits_val(2,0,x) -/* MSC1 bits - see Table 6-21 in [1] */ +/* MSC1 bits - see Table 6-21 in [1], Table 6-25 in [3] */ #define MSC1_RBUFF3 bit(31) #define MSC1_RRR3_MASK bits(30,28) @@ -203,7 +223,7 @@ typedef volatile struct MC_registers { #define MSC1_RT2_MASK bits(2,0) #define MSC1_RT2(x) bits_val(2,0,x) -/* MSC2 bits - see Table 6-21 in [1] */ +/* MSC2 bits - see Table 6-21 in [1], Table 6-25 in [3] */ #define MSC2_RBUFF5 bit(31) #define MSC2_RRR5_MASK bits(30,28) @@ -226,7 +246,7 @@ typedef volatile struct MC_registers { #define MSC2_RT4_MASK bits(2,0) #define MSC2_RT4(x) bits_val(2,0,x) -/* MDMRS bits - see Table 6-4 in [1] */ +/* MDMRS bits - see Table 6-4 in [1], Table 6-4 in [3] */ #define MDMRS_MDMRS2_MASK bits(30,23) #define MDMRS_MDMRS2(x) bits_val(30,23,x) @@ -243,4 +263,24 @@ typedef volatile struct MC_registers { #define MDMRS_MDBL0_MASK bits(2,0) #define MDMRS_MDBL0(x) bits_val(2,0,x) +#if !defined(PXA2X0_NOPXA26X) +/* MDMRSLP bits - see Table 6-5 in [3] */ + +#define MDMRSLP_MDLPEN2 bit(31) +#define MDMRSLP_MDMRSLP2_MASK bits(30,16) +#define MDMRSLP_MDMRSLP2(x) bits_val(30,16,x) +#define MDMRSLP_MDLPEN0 bit(15) +#define MDMRSLP_MDMRSLP0_MASK bits(14,0) +#define MDMRSLP_MDMRSLP0(x) bits_val(14,0,x) + +/* SA1111CR bits - see Table 6-24 in [3] */ + +#define SA1111CR_SA1111_5 bit(5) +#define SA1111CR_SA1111_4 bit(4) +#define SA1111CR_SA1111_3 bit(3) +#define SA1111CR_SA1111_2 bit(2) +#define SA1111CR_SA1111_1 bit(1) +#define SA1111CR_SA1111_0 bit(0) +#endif /* PXA26x only */ + #endif /* PXA2X0_MC_H */ diff --git a/include/arm/pxa2x0/mmc.h b/include/arm/pxa2x0/mmc.h index 80b5ddd2..b9841bef 100644 --- a/include/arm/pxa2x0/mmc.h +++ b/include/arm/pxa2x0/mmc.h @@ -1,7 +1,7 @@ /* * $Id$ * - * XScale PXA250/PXA210 MMC Controller Registers + * XScale PXA26x/PXA250/PXA210 MMC Controller Registers * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * @@ -33,6 +33,8 @@ * Documentation: * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", + * October 2002, Order Number: 278638-001 * */ @@ -114,12 +116,12 @@ typedef volatile struct MMC_registers { #define MMC_RXFIFO_OFFSET 0x40 #define MMC_TXFIFO_OFFSET 0x44 -/* MMC_STRPCL bits - see Table 15-6 in [1] */ +/* MMC_STRPCL bits - see Table 15-6 in [1], Table 15-6 in [2] */ #define MMC_STRPCL_STRPCL_MASK bits(1,0) #define MMC_STRPCL_STRPCL(x) bits_val(1,0,x) -/* MMC_STAT bits - see Table 15-7 in [1] */ +/* MMC_STAT bits - see Table 15-7 in [1], Table 15-7 in [2] */ #define MMC_STAT_END_CMD_RES bit(13) #define MMC_STAT_PRG_DONE bit(12) @@ -134,19 +136,19 @@ typedef volatile struct MMC_registers { #define MMC_STAT_TIME_OUT_RESPONSE bit(1) #define MMC_STAT_READ_TIME_OUT bit(0) -/* MMC_CLKRT bits - see Table 15-8 in [1] */ +/* MMC_CLKRT bits - see Table 15-8 in [1], Table 15-8 in [2] */ #define MMC_CLKRT_CLK_RATE_MASK bits(2,0) #define MMC_CLKRT_CLK_RATE(x) bits_val(2,0,x) -/* MMC_SPI bits - see Table 15-9 in [1] */ +/* MMC_SPI bits - see Table 15-9 in [1], Table 15-9 in [2] */ #define MMC_SPI_SPI_CS_ADDRESS bit(3) #define MMC_SPI_SPI_CS_EN bit(2) #define MMC_SPI_CRC_ON bit(1) #define MMC_SPI_SPI_EN bit(0) -/* MMC_CMDAT bits - see Table 15-10 in [1] */ +/* MMC_CMDAT bits - see Table 15-10 in [1], Table 15-10 in [2] */ #define MMC_CMDAT_MMC_DMA_EN bit(7) #define MMC_CMDAT_INIT bit(6) @@ -157,31 +159,31 @@ typedef volatile struct MMC_registers { #define MMC_CMDAT_RESPONSE_FORMAT_MASK bits(1,0) #define MMC_CMDAT_RESPONSE_FORMAT(x) bits_val(1,0,x) -/* MMC_RESTO bits - see Table 15-11 in [1] */ +/* MMC_RESTO bits - see Table 15-11 in [1], Table 15-11 in [2] */ #define MMC_RESTO_RES_TO_MASK bits(6,0) #define MMC_RESTO_RES_TO(x) bits_val(6,0,x) -/* MMC_RDTO bits - see Table 15-12 in [1] */ +/* MMC_RDTO bits - see Table 15-12 in [1], Table 15-12 in [2] */ #define MMC_RDTO_READ_TO_MASK bits(15,0) #define MMC_RDTO_READ_TO(x) bits_val(15,0,x) -/* MMC_BLKLEN bits - see Table 15-13 in [1] */ +/* MMC_BLKLEN bits - see Table 15-13 in [1], Table 15-13 in [2] */ #define MMC_BLKLEN_BLK_LEN_MASK bits(9,0) #define MMC_BLKLEN_BLK_LEN(x) bits_val(9,0,x) -/* MMC_NOB bits - see Table 15-14 in [1] */ +/* MMC_NOB bits - see Table 15-14 in [1], Table 15-14 in [2] */ #define MMC_NOB_MMC_NOB_MASK bits(15,0) #define MMC_NOB_MMC_NOB(x) bits_val(15,0,x) -/* MMC_PRTBUF bits - see Table 15-15 in [1] */ +/* MMC_PRTBUF bits - see Table 15-15 in [1], Table 15-15 in [2] */ #define MMC_PRTBUF_BUF_PART_FULL bit(0) -/* MMC_I_MASK bits - see Table 15-15 in [1] */ +/* MMC_I_MASK bits - see Table 15-16 in [1], Table 15-16 in [2] */ #define MMC_I_MASK_TXFIFO_WR_REQ bit(6) #define MMC_I_MASK_RXFIFO_RD_REQ bit(5) @@ -191,7 +193,7 @@ typedef volatile struct MMC_registers { #define MMC_I_MASK_PRG_DONE bit(1) #define MMC_I_MASK_DATA_TRAN_DONE bit(0) -/* MMC_I_REG bits - see Table 15-17 in [1] */ +/* MMC_I_REG bits - see Table 15-17 in [1], Table 15-17 in [2] */ #define MMC_I_REG_TXFIFO_WR_REQ bit(6) #define MMC_I_REG_RXFIFO_RD_REQ bit(5) @@ -201,32 +203,32 @@ typedef volatile struct MMC_registers { #define MMC_I_REG_PRG_DONE bit(1) #define MMC_I_REG_DATA_TRAN_DONE bit(0) -/* MMC_CMD bits - see Table 15-18 in [1] */ +/* MMC_CMD bits - see Table 15-18 in [1], Table 15-18 in [2] */ #define MMC_CMD_CMD_INDEX_MASK bits(5,0) #define MMC_CMD_CMD_INDEX(x) bits_val(5,0,x) -/* MMC_ARGH bits - see Table 15-20 in [1] */ +/* MMC_ARGH bits - see Table 15-20 in [1], Table 15-20 in [2] */ #define MMC_ARGH_ARG_H_MASK bits(15,0) #define MMC_ARGH_ARG_H(x) bits_val(15,0,x) -/* MMC_ARGL bits - see Table 15-21 in [1] */ +/* MMC_ARGL bits - see Table 15-21 in [1], Table 15-21 in [2] */ #define MMC_ARGL_ARG_L_MASK bits(15,0) #define MMC_ARGL_ARG_L(x) bits_val(15,0,x) -/* MMC_RES bits - see Table 15-22 in [1] */ +/* MMC_RES bits - see Table 15-22 in [1], Table 15-22 in [2] */ #define MMC_RES_RESPONSE_DATA_MASK bits(15,0) #define MMC_RES_RESPONSE_DATA(x) bits_val(15,0,x) -/* MMC_RXFIFO bits - see Table 15-23 in [1] */ +/* MMC_RXFIFO bits - see Table 15-23 in [1], Table 15-23 in [2] */ #define MMC_RXFIFO_READ_DATA_MASK bits(7,0) #define MMC_RXFIFO_READ_DATA(x) bits_val(7,0,x) -/* MMC_TXFIFO bits - see Table 15-24 in [1] */ +/* MMC_TXFIFO bits - see Table 15-24 in [1], Table 15-24 in [2] */ #define MMC_TXFIFO_WRITE_DATA_MASK bits(7,0) #define MMC_TXFIFO_WRITE_DATA(x) bits_val(7,0,x) diff --git a/include/arm/pxa2x0/ost.h b/include/arm/pxa2x0/ost.h index c29c0a30..48bb2a07 100644 --- a/include/arm/pxa2x0/ost.h +++ b/include/arm/pxa2x0/ost.h @@ -1,7 +1,7 @@ /* * $Id$ * - * XScale PXA250/PXA210 OS Timer Registers + * XScale PXA26x/PXA250/PXA210 OS Timer Registers * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * @@ -33,6 +33,8 @@ * Documentation: * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", + * October 2002, Order Number: 278638-001 * */ @@ -78,18 +80,18 @@ typedef volatile struct OST_registers { #define OWER_OFFSET 0x18 #define OIER_OFFSET 0x1C -/* OSSR bits - see 4.4.2.5 in [1] */ +/* OSSR bits - see 4.4.2.5 in [1], Table 4-48 in [2] */ #define OSSR_M3 bit(3) #define OSSR_M2 bit(2) #define OSSR_M1 bit(1) #define OSSR_M0 bit(0) -/* OWER bits - see Table 4-46 in [1] */ +/* OWER bits - see Table 4-46 in [1], Table 4-46 in [2] */ #define OWER_WME bit(0) -/* OIER bits - see Table 4-45 in [1] */ +/* OIER bits - see Table 4-45 in [1], Table 4-45 in [2] */ #define OIER_E3 bit(3) #define OIER_E2 bit(2) diff --git a/include/arm/pxa2x0/pmrc.h b/include/arm/pxa2x0/pmrc.h index b82b3613..4ac5d843 100644 --- a/include/arm/pxa2x0/pmrc.h +++ b/include/arm/pxa2x0/pmrc.h @@ -1,7 +1,7 @@ /* * $Id$ * - * XScale PXA250/PXA210 Power Manager and Reset Control Registers + * XScale PXA26x/PXA250/PXA210 Power Manager and Reset Control Registers * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * @@ -33,6 +33,8 @@ * Documentation: * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", + * October 2002, Order Number: 278638-001 * */ @@ -97,11 +99,11 @@ typedef volatile struct PMRC_registers { #define PGSR2_OFFSET 0x28 #define RCSR_OFFSET 0x30 -/* PMCR bits - see Table 3-7 in [1] */ +/* PMCR bits - see Table 3-7 in [1], Table 3-7 in [2] */ #define PMCR_IDAE bit(0) -/* PSSR bits - see Table 3-13 in [1] */ +/* PSSR bits - see Table 3-13 in [1], Table 3-13 in [2] */ #define PSSR_RDH bit(5) #define PSSR_PH bit(4) @@ -109,17 +111,33 @@ typedef volatile struct PMRC_registers { #define PSSR_BFS bit(1) #define PSSR_SSS bit(0) -/* PWER bits - see Table 3-9 in [1] */ +/* PWER bits - see Table 3-9 in [1], Table 3-9 in [2] */ #define PWER_WERTC bit(31) - -/* PCFR bits - see Table 3-8 in [1] */ +#define PWER_WE15 bit(15) +#define PWER_WE14 bit(14) +#define PWER_WE13 bit(13) +#define PWER_WE12 bit(12) +#define PWER_WE11 bit(11) +#define PWER_WE10 bit(10) +#define PWER_WE9 bit(9) +#define PWER_WE8 bit(8) +#define PWER_WE7 bit(7) +#define PWER_WE6 bit(6) +#define PWER_WE5 bit(5) +#define PWER_WE4 bit(4) +#define PWER_WE3 bit(3) +#define PWER_WE2 bit(2) +#define PWER_WE1 bit(1) +#define PWER_WE0 bit(0) + +/* PCFR bits - see Table 3-8 in [1], Table 3-8 in [2] */ #define PCFR_FS bit(2) #define PCFR_FP bit(1) #define PCFR_OPDE bit(0) -/* RCSR bits - see Table 3-18 in [1] */ +/* RCSR bits - see Table 3-18 in [1], Table 3-18 in [2] */ #define RCSR_GPR bit(3) #define RCSR_SMR bit(2) diff --git a/include/arm/pxa2x0/pwm.h b/include/arm/pxa2x0/pwm.h index 3418596a..1cccc0e6 100644 --- a/include/arm/pxa2x0/pwm.h +++ b/include/arm/pxa2x0/pwm.h @@ -1,7 +1,7 @@ /* * $Id$ * - * XScale PXA250/PXA210 PWM0 and PWM1 Registers + * XScale PXA26x/PXA250/PXA210 PWM0 and PWM1 Registers * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * @@ -33,6 +33,8 @@ * Documentation: * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", + * October 2002, Order Number: 278638-001 * */ @@ -79,19 +81,19 @@ typedef volatile struct PWM_registers { #define PWM_PWDUTY_OFFSET 0x04 #define PWM_PERVAL_OFFSET 0x08 -/* PWM_CTRL bits - see Table 4-49 in [1] */ +/* PWM_CTRL bits - see Table 4-49 in [1], Table 4-50 in [2] */ #define PWM_CTRL_PWM_SD bit(6) #define PWM_CTRL_PRESCALE_MASK bits(5,0) #define PWM_CTRL_PRESCALE(x) bits_val(5,0,x) -/* PWM_PWDUTY bits - see Table 4-50 in [1] */ +/* PWM_PWDUTY bits - see Table 4-50 in [1], Table 4-51 in [2] */ #define PWM_PWDUTY_FDCYCLE bit(10) #define PWM_PWDUTY_DCYCLE_MASK bits(9,0) #define PWM_PWDUTY_DCYCLE(x) bits_val(9,0,x) -/* PWM_PERVAL bits - see Table 4-51 in [1] */ +/* PWM_PERVAL bits - see Table 4-51 in [1], Table 4-52 in [2] */ #define PWM_PERVAL_PV_MASK bits(9,0) #define PWM_PERVAL_PV(x) bits_val(9,0,x) diff --git a/include/arm/pxa2x0/rtc.h b/include/arm/pxa2x0/rtc.h index 48f7efb3..12d38fd1 100644 --- a/include/arm/pxa2x0/rtc.h +++ b/include/arm/pxa2x0/rtc.h @@ -1,7 +1,7 @@ /* * $Id$ * - * XScale PXA250/PXA210 RTC Registers + * XScale PXA26x/PXA250/PXA210 RTC Registers * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * @@ -33,6 +33,8 @@ * Documentation: * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", + * October 2002, Order Number: 278638-001 * */ @@ -72,19 +74,19 @@ typedef volatile struct RTC_registers { #define RTSR_OFFSET 0x08 #define RTTR_OFFSET 0x0C -/* RCNR bits - see Table 4-39 in [1] */ - -#define RCNR_LCK bit(31) -#define RCNR_DEL_MASK bits(25,16) -#define RCNR_DEL(x) bits_val(25,16,x) -#define RCNR_CK_DIV_MASK bits(15,0) -#define RCNR_CK_DIV(x) bits_val(15,0,x) - -/* RTSR bits - see Table 4-42 in [1] */ +/* RTSR bits - see Table 4-42 in [1], Table 4-42 in [2] */ #define RTSR_HZE bit(3) #define RTSR_ALE bit(2) #define RTSR_HZ bit(1) #define RTSR_AL bit(0) +/* RTTR bits - see Table 4-39 in [1], Table 4-39 in [2] */ + +#define RTTR_LCK bit(31) +#define RTTR_DEL_MASK bits(25,16) +#define RTTR_DEL(x) bits_val(25,16,x) +#define RTTR_CK_DIV_MASK bits(15,0) +#define RTTR_CK_DIV(x) bits_val(15,0,x) + #endif /* PXA2X0_RTC_H */ diff --git a/include/arm/pxa2x0/ssp.h b/include/arm/pxa2x0/ssp.h index aefcf90f..a4dac351 100644 --- a/include/arm/pxa2x0/ssp.h +++ b/include/arm/pxa2x0/ssp.h @@ -1,7 +1,7 @@ /* * $Id$ * - * XScale PXA250/PXA210 SSP Registers + * XScale PXA26x/PXA250/PXA210 SSP/NSSP/ASSP Registers * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * @@ -33,6 +33,8 @@ * Documentation: * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", + * October 2002, Order Number: 278638-001 * */ @@ -45,28 +47,77 @@ #include #endif +#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA26X) +#define PXA2X0_NOPXA26X +#endif + /* SSP Registers */ #define SSP_BASE 0x41000000 +#if !defined(PXA2X0_NOPXA26X) +#define NSSP_BASE 0x41400000 +#define ASSP_BASE 0x41500000 +#endif /* PXA26x only */ #if LANGUAGE == C -/* see Table 8-7 in [1] */ +/* see Table 8-7 in [1], Table 8-7 in [2], Table 16-10 in [2], Table 16-11 in [2] */ typedef volatile struct SSP_registers { uint32_t sscr0; uint32_t sscr1; uint32_t sssr; +#if defined(PXA2X0_NOPXA26X) uint32_t __reserved; +#else /* PXA26x only */ + uint32_t xssitr; /* only for NSSP/ASSP */ +#endif /* PXA26x only */ uint32_t ssdr; +#if !defined(PXA2X0_NOPXA26X) + uint32_t __reserved[5]; + uint32_t xssto; /* only for NSSP/ASSP */ + uint32_t xsspsp; /* only for NSSP/ASSP */ +#endif /* PXA26x only */ } SSP_registers_t; #ifdef PXA2X0_UNMAPPED #define SSP_pointer ((SSP_registers_t*) SSP_BASE) +#if !defined(PXA2X0_NOPXA26X) +#define NSSP_pointer ((SSP_registers_t*) NSSP_BASE) +#define ASSP_pointer ((SSP_registers_t*) ASSP_BASE) +#endif /* PXA26x only */ #endif #define SSCR0 SSP_pointer->sscr0 #define SSCR1 SSP_pointer->sscr1 #define SSSR SSP_pointer->sssr #define SSDR SSP_pointer->ssdr + +#if !defined(PXA2X0_NOPXA26X) +#define NSSCR0 NSSP_pointer->sscr0 +#define NSSCR1 NSSP_pointer->sscr1 +#define NSSSR NSSP_pointer->sssr +#define NSSITR NSSP_pointer->xssitr +#define NSSDR NSSP_pointer->ssdr +#define NSSPTO NSSP_pointer->xsspto +#define NSSPSP NSSP_pointer->xsspsp + +#define ASSCR0 ASSP_pointer->sscr0 +#define ASSCR1 ASSP_pointer->sscr1 +#define ASSSR ASSP_pointer->sssr +#define ASSITR ASSP_pointer->xssitr +#define ASSDR ASSP_pointer->ssdr +#define ASSPTO ASSP_pointer->xsspto +#define ASSPSP ASSP_pointer->xsspsp + +/* common for NSSP/ASSP */ + +#define XSSCR0 XSSP_pointer->sscr0 +#define XSSCR1 XSSP_pointer->sscr1 +#define XSSSR XSSP_pointer->sssr +#define XSSITR XSSP_pointer->xssitr +#define XSSDR XSSP_pointer->ssdr +#define XSSPTO XSSP_pointer->xsspto +#define XSSPSP XSSP_pointer->xsspsp +#endif /* PXA26x only */ #endif /* LANGUAGE == C */ #define SSCR0_OFFSET 0x00 @@ -74,7 +125,35 @@ typedef volatile struct SSP_registers { #define SSSR_OFFSET 0x08 #define SSDR_OFFSET 0x10 -/* SSCR0 bits - see Table 8-2 in [1] */ +#if !defined(PXA2X0_NOPXA26X) +#define NSSCR0_OFFSET 0x00 +#define NSSCR1_OFFSET 0x04 +#define NSSSR_OFFSET 0x08 +#define NSSITR_OFFSET 0x0C +#define NSSDR_OFFSET 0x10 +#define NSSTO_OFFSET 0x28 +#define NSSPSP_OFFSET 0x2C + +#define ASSCR0_OFFSET 0x00 +#define ASSCR1_OFFSET 0x04 +#define ASSSR_OFFSET 0x08 +#define ASSITR_OFFSET 0x0C +#define ASSDR_OFFSET 0x10 +#define ASSTO_OFFSET 0x28 +#define ASSPSP_OFFSET 0x2C + +/* common for NSSP/ASSP */ + +#define XSSCR0_OFFSET 0x00 +#define XSSCR1_OFFSET 0x04 +#define XSSSR_OFFSET 0x08 +#define XSSITR_OFFSET 0x0C +#define XSSDR_OFFSET 0x10 +#define XSSTO_OFFSET 0x28 +#define XSSPSP_OFFSET 0x2C +#endif /* PXA26x only */ + +/* SSCR0 bits - see Table 8-2 in [1], Table 8-2 in [2] */ #define SSCR0_SCR_MASK bits(15,8) #define SSCR0_SCR(x) bits_val(15,8,x) @@ -85,7 +164,7 @@ typedef volatile struct SSP_registers { #define SSCR0_DSS_MASK bits(3,0) #define SSCR0_DSS(x) bits_val(3,0,x) -/* SSCR1 bits - see Table 8-3 in [1] */ +/* SSCR1 bits - see Table 8-3 in [1], Table 8-3 in [2] */ #define SSCR1_RFT_MASK bits(13,10) #define SSCR1_RFT(x) bits_val(13,10,x) @@ -98,7 +177,7 @@ typedef volatile struct SSP_registers { #define SSCR1_TIE bit(1) #define SSCR1_RIE bit(0) -/* SSSR bits - see Table 8-6 in [1] */ +/* SSSR bits - see Table 8-6 in [1], Table 8-6 in [2] */ #define SSSR_RFL_MASK bits(15,12) #define SSSR_RFL(x) bits_val(15,12,x) @@ -111,4 +190,225 @@ typedef volatile struct SSP_registers { #define SSSR_RNE bit(3) #define SSSR_TNF bit(2) +#if !defined(PXA2X0_NOPXA26X) +/* NSSCR0/ASSCR0 bits - see Table 16-3 in [2] */ + +#define NSSCR0_EDSS bit(20) +#define NSSCR0_SCR_MASK bits(19,8) +#define NSSCR0_SCR(x) bits_val(19,8,x) +#define NSSCR0_SSE bit(7) +#define NSSCR0_FRF_MASK bits(5,4) +#define NSSCR0_FRF(x) bits_val(5,4,x) +#define NSSCR0_DSS_MASK bits(3,0) +#define NSSCR0_DSS(x) bits_val(3,0,x) + +#define ASSCR0_EDSS bit(20) +#define ASSCR0_SCR_MASK bits(19,8) +#define ASSCR0_SCR(x) bits_val(19,8,x) +#define ASSCR0_SSE bit(7) +#define ASSCR0_FRF_MASK bits(5,4) +#define ASSCR0_FRF(x) bits_val(5,4,x) +#define ASSCR0_DSS_MASK bits(3,0) +#define ASSCR0_DSS(x) bits_val(3,0,x) + +#define XSSCR0_EDSS bit(20) +#define XSSCR0_SCR_MASK bits(19,8) +#define XSSCR0_SCR(x) bits_val(19,8,x) +#define XSSCR0_SSE bit(7) +#define XSSCR0_FRF_MASK bits(5,4) +#define XSSCR0_FRF(x) bits_val(5,4,x) +#define XSSCR0_DSS_MASK bits(3,0) +#define XSSCR0_DSS(x) bits_val(3,0,x) + +/* NSSCR1/ASSCR1 bits - see Table 16-4 in [2] */ + +#define NSSCR1_TTELP bit(31) +#define NSSCR1_TTE bit(30) +#define NSSCR1_EBCEI bit(29) +#define NSSCR1_SCFR bit(28) +#define NSSCR1_SCLKDIR bit(25) +#define NSSCR1_SFRMDIR bit(24) +#define NSSCR1_RWOT bit(23) +#define NSSCR1_TSRE bit(21) +#define NSSCR1_RSRE bit(20) +#define NSSCR1_TINTE bit(19) +#define NSSCR1_STRF bit(15) +#define NSSCR1_EFWR bit(14) +#define NSSCR1_RFT_MASK bits(13,10) +#define NSSCR1_RFT(x) bits_val(13,10,x) +#define NSSCR1_TFT_MASK bits(9,6) +#define NSSCR1_TFT(x) bits_val(9,6,x) +#define NSSCR1_MWDS bit(5) +#define NSSCR1_SPH bit(4) +#define NSSCR1_SPO bit(3) +#define NSSCR1_LBM bit(2) +#define NSSCR1_TIE bit(1) +#define NSSCR1_RIE bit(0) + +#define ASSCR1_TTELP bit(31) +#define ASSCR1_TTE bit(30) +#define ASSCR1_EBCEI bit(29) +#define ASSCR1_SCFR bit(28) +#define ASSCR1_SCLKDIR bit(25) +#define ASSCR1_SFRMDIR bit(24) +#define ASSCR1_RWOT bit(23) +#define ASSCR1_TSRE bit(21) +#define ASSCR1_RSRE bit(20) +#define ASSCR1_TINTE bit(19) +#define ASSCR1_STRF bit(15) +#define ASSCR1_EFWR bit(14) +#define ASSCR1_RFT_MASK bits(13,10) +#define ASSCR1_RFT(x) bits_val(13,10,x) +#define ASSCR1_TFT_MASK bits(9,6) +#define ASSCR1_TFT(x) bits_val(9,6,x) +#define ASSCR1_MWDS bit(5) +#define ASSCR1_SPH bit(4) +#define ASSCR1_SPO bit(3) +#define ASSCR1_LBM bit(2) +#define ASSCR1_TIE bit(1) +#define ASSCR1_RIE bit(0) + +#define XSSCR1_TTELP bit(31) +#define XSSCR1_TTE bit(30) +#define XSSCR1_EBCEI bit(29) +#define XSSCR1_SCFR bit(28) +#define XSSCR1_SCLKDIR bit(25) +#define XSSCR1_SFRMDIR bit(24) +#define XSSCR1_RWOT bit(23) +#define XSSCR1_TSRE bit(21) +#define XSSCR1_RSRE bit(20) +#define XSSCR1_TINTE bit(19) +#define XSSCR1_STRF bit(15) +#define XSSCR1_EFWR bit(14) +#define XSSCR1_RFT_MASK bits(13,10) +#define XSSCR1_RFT(x) bits_val(13,10,x) +#define XSSCR1_TFT_MASK bits(9,6) +#define XSSCR1_TFT(x) bits_val(9,6,x) +#define XSSCR1_MWDS bit(5) +#define XSSCR1_SPH bit(4) +#define XSSCR1_SPO bit(3) +#define XSSCR1_LBM bit(2) +#define XSSCR1_TIE bit(1) +#define XSSCR1_RIE bit(0) + +/* NSSITR/ASSITR bits - see Table 16-7 in [2] */ + +#define NSSITR_TROR bit(7) +#define NSSITR_TRFS bit(6) +#define NSSITR_TTFS bit(5) + +#define ASSITR_TROR bit(7) +#define ASSITR_TRFS bit(6) +#define ASSITR_TTFS bit(5) + +#define XSSITR_TROR bit(7) +#define XSSITR_TRFS bit(6) +#define XSSITR_TTFS bit(5) + +/* NSSSR/ASSSR bits - see Table 16-8 in [2] */ + +#define NSSSR_BCE bit(23) +#define NSSSR_CSS bit(22) +#define NSSSR_TUR bit(21) +#define NSSSR_TINT bit(19) +#define NSSSR_RFL_MASK bits(15,12) +#define NSSSR_RFL(x) bits_val(15,12,x) +#define NSSSR_TFL_MASK bits(11,8) +#define NSSSR_TFL(x) bits_val(11,8,x) +#define NSSSR_ROR bit(7) +#define NSSSR_RFS bit(6) +#define NSSSR_TFS bit(5) +#define NSSSR_BSY bit(4) +#define NSSSR_RNE bit(3) +#define NSSSR_TNF bit(2) + +#define ASSSR_BCE bit(23) +#define ASSSR_CSS bit(22) +#define ASSSR_TUR bit(21) +#define ASSSR_TINT bit(19) +#define ASSSR_RFL_MASK bits(15,12) +#define ASSSR_RFL(x) bits_val(15,12,x) +#define ASSSR_TFL_MASK bits(11,8) +#define ASSSR_TFL(x) bits_val(11,8,x) +#define ASSSR_ROR bit(7) +#define ASSSR_RFS bit(6) +#define ASSSR_TFS bit(5) +#define ASSSR_BSY bit(4) +#define ASSSR_RNE bit(3) +#define ASSSR_TNF bit(2) + +#define XSSSR_BCE bit(23) +#define XSSSR_CSS bit(22) +#define XSSSR_TUR bit(21) +#define XSSSR_TINT bit(19) +#define XSSSR_RFL_MASK bits(15,12) +#define XSSSR_RFL(x) bits_val(15,12,x) +#define XSSSR_TFL_MASK bits(11,8) +#define XSSSR_TFL(x) bits_val(11,8,x) +#define XSSSR_ROR bit(7) +#define XSSSR_RFS bit(6) +#define XSSSR_TFS bit(5) +#define XSSSR_BSY bit(4) +#define XSSSR_RNE bit(3) +#define XSSSR_TNF bit(2) + +/* NSSTO/ASSTO bits - see Table 16-6 in [2] */ + +#define NSSTO_TIMEOUT_MASK bits(23,0) +#define NSSTO_TIMEOUT(x) bits_val(23,0,x) + +#define ASSTO_TIMEOUT_MASK bits(23,0) +#define ASSTO_TIMEOUT(x) bits_val(23,0,x) + +#define XSSTO_TIMEOUT_MASK bits(23,0) +#define XSSTO_TIMEOUT(x) bits_val(23,0,x) + +/* NSSPSP/ASSPSP bits - see Table 16-5 in [2] */ + +#define NSSPSP_DMYSTOP_MASK bits(24,23) +#define NSSPSP_DMYSTOP(x) bits_val(24,23,x) +#define NSSPSP_SFRMWDTH_MASK bits(21,16) +#define NSSPSP_SFRMWDTH(x) bits_val(21,16,x) +#define NSSPSP_SFRMDLY_MASK bits(15,9) +#define NSSPSP_SFRMDLY(x) bits_val(15,9,x) +#define NSSPSP_DMYSTRT_MASK bits(8,7) +#define NSSPSP_DMYSTRT(x) bits_val(8,7,x) +#define NSSPSP_STRTDLY_MASK bits(6,4) +#define NSSPSP_STRTDLY(x) bits_val(6,4,x) +#define NSSPSP_ETDS bit(3) +#define NSSPSP_SFRMP bit(2) +#define NSSPSP_SCMODE_MASK bits(1,0) +#define NSSPSP_SCMODE(x) bits_val(1,0,x) + +#define ASSPSP_DMYSTOP_MASK bits(24,23) +#define ASSPSP_DMYSTOP(x) bits_val(24,23,x) +#define ASSPSP_SFRMWDTH_MASK bits(21,16) +#define ASSPSP_SFRMWDTH(x) bits_val(21,16,x) +#define ASSPSP_SFRMDLY_MASK bits(15,9) +#define ASSPSP_SFRMDLY(x) bits_val(15,9,x) +#define ASSPSP_DMYSTRT_MASK bits(8,7) +#define ASSPSP_DMYSTRT(x) bits_val(8,7,x) +#define ASSPSP_STRTDLY_MASK bits(6,4) +#define ASSPSP_STRTDLY(x) bits_val(6,4,x) +#define ASSPSP_ETDS bit(3) +#define ASSPSP_SFRMP bit(2) +#define ASSPSP_SCMODE_MASK bits(1,0) +#define ASSPSP_SCMODE(x) bits_val(1,0,x) + +#define XSSPSP_DMYSTOP_MASK bits(24,23) +#define XSSPSP_DMYSTOP(x) bits_val(24,23,x) +#define XSSPSP_SFRMWDTH_MASK bits(21,16) +#define XSSPSP_SFRMWDTH(x) bits_val(21,16,x) +#define XSSPSP_SFRMDLY_MASK bits(15,9) +#define XSSPSP_SFRMDLY(x) bits_val(15,9,x) +#define XSSPSP_DMYSTRT_MASK bits(8,7) +#define XSSPSP_DMYSTRT(x) bits_val(8,7,x) +#define XSSPSP_STRTDLY_MASK bits(6,4) +#define XSSPSP_STRTDLY(x) bits_val(6,4,x) +#define XSSPSP_ETDS bit(3) +#define XSSPSP_SFRMP bit(2) +#define XSSPSP_SCMODE_MASK bits(1,0) +#define XSSPSP_SCMODE(x) bits_val(1,0,x) +#endif /* PXA26x only */ + #endif /* PXA2X0_SSP_H */ diff --git a/include/arm/pxa2x0/uart.h b/include/arm/pxa2x0/uart.h index d69e780b..832a1638 100644 --- a/include/arm/pxa2x0/uart.h +++ b/include/arm/pxa2x0/uart.h @@ -1,7 +1,7 @@ /* * $Id$ * - * XScale PXA250/PXA210 UART (FFUART/BTUART/STUART) Declarations + * XScale PXA26x/PXA250/PXA210 UART (FFUART/BTUART/STUART/HWUART) Declarations * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * @@ -33,6 +33,8 @@ * Documentation: * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", + * October 2002, Order Number: 278638-001 * */ @@ -45,11 +47,18 @@ #include #endif -/* Common UART (FFUART/BTUART/STUART) Declarations */ +#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA26X) +#define PXA2X0_NOPXA26X +#endif + +/* Common UART (FFUART/BTUART/STUART/HWUART) Declarations */ #define FFUART_BASE 0x40100000 #define BTUART_BASE 0x40200000 #define STUART_BASE 0x40700000 +#if !defined(PXA2X0_NOPXA26X) +#define HWUART_BASE 0x41600000 +#endif /* PXA26x only */ #if LANGUAGE == C typedef volatile struct UART_registers { @@ -69,15 +78,23 @@ typedef volatile struct UART_registers { uint32_t lcr; uint32_t mcr; uint32_t lsr; - uint32_t msr; + uint32_t msr; /* only for FFUART, BTUART, HWUART */ uint32_t spr; uint32_t isr; +#if !defined(PXA2X0_NOPXA26X) + uint32_t hwfor; /* only for HWUART */ + uint32_t hwabr; /* only for HWUART */ + uint32_t hwacr; /* only for HWUART */ +#endif /* PXA26x only */ } UART_registers_t; #ifdef PXA2X0_UNMAPPED #define FFUART_pointer ((UART_registers_t*) FFUART_BASE) #define BTUART_pointer ((UART_registers_t*) BTUART_BASE) #define STUART_pointer ((UART_registers_t*) STUART_BASE) +#if !defined(PXA2X0_NOPXA26X) +#define HWUART_pointer ((UART_registers_t*) HWUART_BASE) +#endif /* PXA26x only */ #endif #define RBR UART_pointer->rbr @@ -136,11 +153,31 @@ typedef volatile struct UART_registers { #define STLCR STUART_pointer->lcr #define STMCR STUART_pointer->mcr #define STLSR STUART_pointer->lsr -#define STMSR STUART_pointer->msr #define STSPR STUART_pointer->spr #define STISR STUART_pointer->isr #define STDLL STUART_pointer->dll #define STDLH STUART_pointer->dlh + +#if !defined(PXA2X0_NOPXA26X) +/* HWUART */ + +#define HWRBR HWUART_pointer->rbr +#define HWTHR HWUART_pointer->thr +#define HWIER HWUART_pointer->ier +#define HWIIR HWUART_pointer->iir +#define HWFCR HWUART_pointer->fcr +#define HWLCR HWUART_pointer->lcr +#define HWMCR HWUART_pointer->mcr +#define HWLSR HWUART_pointer->lsr +#define HWMSR HWUART_pointer->msr +#define HWSPR HWUART_pointer->spr +#define HWISR HWUART_pointer->isr +#define HWFOR HWUART_pointer->hwfor +#define HWABR HWUART_pointer->hwabr +#define HWACR HWUART_pointer->hwacr +#define HWDLL HWUART_pointer->dll +#define HWDLH HWUART_pointer->dlh +#endif /* PXA26x only */ #endif /* LANGUAGE == C */ #define RBR_OFFSET 0x00 @@ -154,10 +191,15 @@ typedef volatile struct UART_registers { #define MSR_OFFSET 0x18 #define SPR_OFFSET 0x1C #define ISR_OFFSET 0x20 +#if !defined(PXA2X0_NOPXA26X) +#define HWFOR_OFFSET 0x24 /* only for HWUART */ +#define HWABR_OFFSET 0x28 /* only for HWUART */ +#define HWACR_OFFSET 0x2C /* only for HWUART */ +#endif /* PXA26x only */ #define DLL_OFFSET 0x00 #define DLH_OFFSET 0x04 -/* IER bits */ +/* IER bits - see Table 10-7 in [1], Table 10-7 in [2], Table 17-6 in [2] */ #define IER_DMAE bit(7) #define IER_UUE bit(6) @@ -168,24 +210,30 @@ typedef volatile struct UART_registers { #define IER_TIE bit(1) #define IER_RAVIE bit(0) -/* IIR bits - see Table 10-9 in [1] */ +/* IIR bits - see Table 10-9 in [1], Table 10-9 in [2], Table 17-8 in [2] */ #define IIR_FIFOES_MASK bits(7,6) #define IIR_FIFOES(x) bits_val(7,6,x) +#if !defined(PXA2X0_NOPXA26X) +#define IIR_ABL bit(4) /* only for HWUART */ +#endif /* PXA26x only */ #define IIR_TOD bit(3) #define IIR_IID_MASK bits(2,1) #define IIR_IID(x) bits_val(2,1,x) #define IIR_IP bit(0) -/* FCR bits - see Table 10-11 in [1] */ +/* FCR bits - see Table 10-11 in [1], Table 10-11 in [2], Table 17-10 in [2] */ #define FCR_ITL_MASK bits(7,6) #define FCR_ITL(x) bits_val(7,6,x) +#if !defined(PXA2X0_NOPXA26X) +#define FCR_TIL bit(3) /* only for HWUART */ +#endif /* PXA26x only */ #define FCR_RESETTF bit(2) #define FCR_RESETRF bit(1) #define FCR_TRFIFOE bit(0) -/* LCR bits - see Table 10-12 in [1] */ +/* LCR bits - see Table 10-12 in [1], Table 10-12 in [2], Table 17-14 in [2] */ #define LCR_DLAB bit(7) #define LCR_SB bit(6) @@ -196,7 +244,7 @@ typedef volatile struct UART_registers { #define LCR_WLS_MASK bits(1,0) #define LCR_WLS(x) bits_val(1,0,x) -/* LSR bits */ +/* LSR bits - see Table 10-13 in [1], Table 10-13 in [2], Table 17-15 in [2] */ #define LSR_FIFOE bit(7) #define LSR_TEMT bit(6) @@ -207,31 +255,34 @@ typedef volatile struct UART_registers { #define LSR_OE bit(1) #define LSR_DR bit(0) -/* MCR bits */ +/* MCR bits - see Table 10-14 in [1], Table 10-14 in [2], Table 17-16 in [2] */ +#if !defined(PXA2X0_NOPXA26X) +#define MCR_AFE bit(5) /* only for HWUART */ +#endif /* PXA26x only */ #define MCR_LOOP bit(4) #define MCR_OUT2 bit(3) -#define MCR_OUT1 bit(2) -#define MCR_RTS bit(1) -#define MCR_DTR bit(0) +#define MCR_OUT1 bit(2) /* only for FFUART - see Table 10-21 in [1], Table 10-21 in [2] */ +#define MCR_RTS bit(1) /* only for FFUART, BTUART, HWUART - see Table 10-21 in [1], Table 10-21 in [2] */ +#define MCR_DTR bit(0) /* only for FFUART - see Table 10-21 in [1], Table 10-21 in [2] */ -/* MSR bits */ +/* MSR bits - see Table 10-15 in [1], Table 10-15 in [2], Table 17-17 in [2] */ -#define MSR_DCD bit(7) -#define MSR_RI bit(6) -#define MSR_DSR bit(5) -#define MSR_CTS bit(4) -#define MSR_DDCD bit(3) -#define MSR_TERI bit(2) -#define MSR_DDSR bit(1) -#define MSR_DCTS bit(0) +#define MSR_DCD bit(7) /* only for FFUART */ +#define MSR_RI bit(6) /* only for FFUART */ +#define MSR_DSR bit(5) /* only for FFUART */ +#define MSR_CTS bit(4) /* only for FFUART, BTUART, HWUART - see Table 10-21 in [1], Table 10-21 in [2] */ +#define MSR_DDCD bit(3) /* only for FFUART */ +#define MSR_TERI bit(2) /* only for FFUART */ +#define MSR_DDSR bit(1) /* only for FFUART */ +#define MSR_DCTS bit(0) /* only for FFUART, BTUART, HWUART - see Table 10-21 in [1], Table 10-21 in [2] */ -/* SPR bits - see Table 10-16 in [1] */ +/* SPR bits - see Table 10-16 in [1], Table 10-16 in [2], Table 17-18 in [2] */ #define SPR_SP_MASK bits(7,0) -#define SPR_SP(x) bits(7,0,x) +#define SPR_SP(x) bits_val(7,0,x) -/* ISR bits */ +/* ISR bits - see Table 10-17 in [1], Table 10-17 in [2], Table 17-19 in [2] */ #define ISR_RXPL bit(4) #define ISR_TXPL bit(3) @@ -239,4 +290,23 @@ typedef volatile struct UART_registers { #define ISR_RCVEIR bit(1) #define ISR_XMITIR bit(0) +#if !defined(PXA2X0_NOPXA26X) +/* HWFOR bits - see Table 17-11 in [2] */ + +#define HWFOR_BC_MASK bits(6,0) +#define HWFOR_BC(x) bits_val(6,0,x) + +/* HWABR bits - see Table 17-12 in [2] */ + +#define HWABR_ABT bit(3) +#define HWABR_ABUP bit(2) +#define HWABR_ABLIE bit(1) +#define HWABR_ABE bit(0) + +/* HWACR bits - see Table 17-13 in [2] */ + +#define HWACR_ACR_MASK bits(15,0) +#define HWACR_ACR(x) bits_val(15,0,x) +#endif /* PXA26x only */ + #endif /* PXA2X0_UART_H */ diff --git a/include/arm/pxa2x0/udc.h b/include/arm/pxa2x0/udc.h index b858fd72..55152037 100644 --- a/include/arm/pxa2x0/udc.h +++ b/include/arm/pxa2x0/udc.h @@ -1,7 +1,7 @@ /* * $Id$ * - * XScale PXA250/PXA210 UDC Registers + * XScale PXA26x/PXA250/PXA210 UDC Registers * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * @@ -33,6 +33,8 @@ * Documentation: * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", + * October 2002, Order Number: 278638-001 * */ @@ -198,7 +200,7 @@ typedef volatile struct UDC_registers { #define USIR0_OFFSET 0x058 #define USIR1_OFFSET 0x05C -/* UDCCR bits - see Table 12-20 in [1] */ +/* UDCCR bits - see Table 12-20 in [1], Table 12-12 in [2] */ #define UDCCR_REM bit(7) #define UDCCR_RSTIR bit(6) @@ -209,7 +211,7 @@ typedef volatile struct UDC_registers { #define UDCCR_UDA bit(1) #define UDCCR_UDE bit(0) -/* UDCCS0 bits - see Table 12-21 in [1] */ +/* UDCCS0 bits - see Table 12-21 in [1], Table 12-13 in [2] */ #define UDCCS0_SA bit(7) #define UDCCS0_RNE bit(6) @@ -220,7 +222,7 @@ typedef volatile struct UDC_registers { #define UDCCS0_IPR bit(1) #define UDCCS0_OPR bit(0) -/* UDCCS1 bits - see Table 12-22 in [1] */ +/* UDCCS1 bits - see Table 12-22 in [1], Table 12-14 in [2] */ #define UDCCS1_TSP bit(7) #define UDCCS1_FST bit(5) @@ -230,7 +232,7 @@ typedef volatile struct UDC_registers { #define UDCCS1_TPC bit(1) #define UDCCS1_TFS bit(0) -/* UDCCS2 bits - see Table 12-23 in [1] */ +/* UDCCS2 bits - see Table 12-23 in [1], Table 12-15 in [2] */ #define UDCCS2_RSP bit(7) #define UDCCS2_RNE bit(6) @@ -240,7 +242,7 @@ typedef volatile struct UDC_registers { #define UDCCS2_RPC bit(1) #define UDCCS2_RFS bit(0) -/* UDCCS3 bits - see Table 12-24 in [1] */ +/* UDCCS3 bits - see Table 12-24 in [1], Table 12-16 in [2] */ #define UDCCS3_TSP bit(7) #define UDCCS3_TUR bit(3) @@ -248,7 +250,7 @@ typedef volatile struct UDC_registers { #define UDCCS3_TPC bit(1) #define UDCCS3_TFS bit(0) -/* UDCCS4 bits - see Table 12-25 in [1] */ +/* UDCCS4 bits - see Table 12-25 in [1], Table 12-17 in [2] */ #define UDCCS4_RSP bit(7) #define UDCCS4_RNE bit(6) @@ -257,7 +259,7 @@ typedef volatile struct UDC_registers { #define UDCCS4_RPC bit(1) #define UDCCS4_RFS bit(0) -/* UDCCS5 bits - see Table 12-26 in [1] */ +/* UDCCS5 bits - see Table 12-26 in [1], Table 12-18 in [2] */ #define UDCCS5_TSP bit(7) #define UDCCS5_FST bit(5) @@ -267,7 +269,7 @@ typedef volatile struct UDC_registers { #define UDCCS5_TPC bit(1) #define UDCCS5_TFS bit(0) -/* UDCCS6 bits - see Table 12-22 in [1] */ +/* UDCCS6 bits - see Table 12-22 in [1], Table 12-14 in [2] */ #define UDCCS6_TSP bit(7) #define UDCCS6_FST bit(5) @@ -277,7 +279,7 @@ typedef volatile struct UDC_registers { #define UDCCS6_TPC bit(1) #define UDCCS6_TFS bit(0) -/* UDCCS7 bits - see Table 12-23 in [1] */ +/* UDCCS7 bits - see Table 12-23 in [1], Table 12-15 in [2] */ #define UDCCS7_RSP bit(7) #define UDCCS7_RNE bit(6) @@ -287,7 +289,7 @@ typedef volatile struct UDC_registers { #define UDCCS7_RPC bit(1) #define UDCCS7_RFS bit(0) -/* UDCCS8 bits - see Table 12-24 in [1] */ +/* UDCCS8 bits - see Table 12-24 in [1], Table 12-16 in [2] */ #define UDCCS8_TSP bit(7) #define UDCCS8_TUR bit(3) @@ -295,7 +297,7 @@ typedef volatile struct UDC_registers { #define UDCCS8_TPC bit(1) #define UDCCS8_TFS bit(0) -/* UDCCS9 bits - see Table 12-25 in [1] */ +/* UDCCS9 bits - see Table 12-25 in [1], Table 12-17 in [2] */ #define UDCCS9_RSP bit(7) #define UDCCS9_RNE bit(6) @@ -304,7 +306,7 @@ typedef volatile struct UDC_registers { #define UDCCS9_RPC bit(1) #define UDCCS9_RFS bit(0) -/* UDCCS10 bits - see Table 12-26 in [1] */ +/* UDCCS10 bits - see Table 12-26 in [1], Table 12-18 in [2] */ #define UDCCS10_TSP bit(7) #define UDCCS10_FST bit(5) @@ -314,7 +316,7 @@ typedef volatile struct UDC_registers { #define UDCCS10_TPC bit(1) #define UDCCS10_TFS bit(0) -/* UDCCS11 bits - see Table 12-22 in [1] */ +/* UDCCS11 bits - see Table 12-22 in [1], Table 12-14 in [2] */ #define UDCCS11_TSP bit(7) #define UDCCS11_FST bit(5) @@ -324,7 +326,7 @@ typedef volatile struct UDC_registers { #define UDCCS11_TPC bit(1) #define UDCCS11_TFS bit(0) -/* UDCCS12 bits - see Table 12-23 in [1] */ +/* UDCCS12 bits - see Table 12-23 in [1], Table 12-15 in [2] */ #define UDCCS12_RSP bit(7) #define UDCCS12_RNE bit(6) @@ -334,7 +336,7 @@ typedef volatile struct UDC_registers { #define UDCCS12_RPC bit(1) #define UDCCS12_RFS bit(0) -/* UDCCS13 bits - see Table 12-24 in [1] */ +/* UDCCS13 bits - see Table 12-24 in [1], Table 12-16 in [2] */ #define UDCCS13_TSP bit(7) #define UDCCS13_TUR bit(3) @@ -342,7 +344,7 @@ typedef volatile struct UDC_registers { #define UDCCS13_TPC bit(1) #define UDCCS13_TFS bit(0) -/* UDCCS14 bits - see Table 12-25 in [1] */ +/* UDCCS14 bits - see Table 12-25 in [1], Table 12-17 in [2] */ #define UDCCS14_RSP bit(7) #define UDCCS14_RNE bit(6) @@ -351,7 +353,7 @@ typedef volatile struct UDC_registers { #define UDCCS14_RPC bit(1) #define UDCCS14_RFS bit(0) -/* UDCCS15 bits - see Table 12-26 in [1] */ +/* UDCCS15 bits - see Table 12-26 in [1], Table 12-18 in [2] */ #define UDCCS15_TSP bit(7) #define UDCCS15_FST bit(5) @@ -361,7 +363,7 @@ typedef volatile struct UDC_registers { #define UDCCS15_TPC bit(1) #define UDCCS15_TFS bit(0) -/* UICR0 bits - see Table 12-27 in [1] */ +/* UICR0 bits - see Table 12-27 in [1], Table 12-19 in [2] */ #define UICR0_IM7 bit(7) #define UICR0_IM6 bit(6) @@ -372,7 +374,7 @@ typedef volatile struct UDC_registers { #define UICR0_IM1 bit(1) #define UICR0_IM0 bit(0) -/* UICR1 bits - see Table 12-28 in [1] */ +/* UICR1 bits - see Table 12-28 in [1], Table 12-20 in [2] */ #define UICR1_IM15 bit(7) #define UICR1_IM14 bit(6) @@ -383,7 +385,7 @@ typedef volatile struct UDC_registers { #define UICR1_IM9 bit(1) #define UICR1_IM8 bit(0) -/* USIR0 bits - see Table 12-29 in [1] */ +/* USIR0 bits - see Table 12-29 in [1], Table 12-21 in [2] */ #define USIR0_IR7 bit(7) #define USIR0_IR6 bit(6) @@ -394,7 +396,7 @@ typedef volatile struct UDC_registers { #define USIR0_IR1 bit(1) #define USIR0_IR0 bit(0) -/* USIR1 bits - see Table 12-30 in [1] */ +/* USIR1 bits - see Table 12-30 in [1], Table 12-22 in [2] */ #define USIR1_IR15 bit(7) #define USIR1_IR14 bit(6) @@ -405,7 +407,7 @@ typedef volatile struct UDC_registers { #define USIR1_IR9 bit(1) #define USIR1_IR8 bit(0) -/* UFNHR bits - see Table 12-31 in [1] */ +/* UFNHR bits - see Table 12-31 in [1], Table 12-23 in [2] */ #define UFNHR_SIR bit(7) #define UFNHR_SIM bit(6) @@ -415,17 +417,17 @@ typedef volatile struct UDC_registers { #define UFNHR_FNMSB_MASK bits(2,0) #define UFNHR_FNMSB(x) bits_val(2,0,x) -/* UFNLR bits - see Table 12-32 in [1] */ +/* UFNLR bits - see Table 12-32 in [1], Table 12-24 in [2] */ #define UNFLR_FNLSB_MASK bits(7,0) #define UFNLR_FNLSB(x) bits_val(7,0,x) -/* UBCRx bits - see Table 12-33 in [1] */ +/* UBCRx bits - see Table 12-33 in [1], Table 12-25 in [2] */ #define UBCR_BC_MASK bits(7,0) #define UBCR_BC(x) bits_val(7,0,x) -/* UDDRx bits - see 12.6.15 - 12.6.20 in [1] */ +/* UDDRx bits - see 12.6.15 - 12.6.20 in [1], 12.6.15 - 12.6.20 in [2] */ #define UDDR_DATA_MASK bits(7,0) #define UDDR_DATA(x) bits_val(7,0,x)