Added register offsets and bits.

git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@43 b68d4a1b-bc3d-0410-92ed-d4ac073336b7

include/arm/sa11x0/hssp.h

@@ -32,14 +32,13 @@
 #ifndef	SA11X0_HSSP_H
 #define	SA11X0_HSSP_H
 
-#ifndef uint32_t
-typedef	unsigned int	uint32_t;
-#endif
+#include <common.h>
 
 /* ICP - HSSP Registers (Serial Port 2) */
 
 #define	HSSP_BASE	0x80040060
 
+#if LANGUAGE == C
 typedef volatile struct HSSP_registers {
 	uint32_t hscr0;
 	uint32_t hscr1;
@@ -59,5 +58,42 @@ typedef volatile struct HSSP_registers {
 #define	HSDR		HSSP_pointer->hsdr
 #define	HSSR0		HSSP_pointer->hssr0
 #define	HSSR1		HSSP_pointer->hssr1
+#endif /* LANGUAGE == C */
+
+#define	HSCR0_OFFSET	0x00
+#define	HSCR1_OFFSET	0x04
+#define	HSDR_OFFSET	0x0C
+#define	HSSR0_OFFSET	0x14
+#define	HSSR1_OFFSET	0x18
+
+/* HSCR0 bits */
+
+#define	HSCR0_AME	bit(7)
+#define	HSCR0_TIE	bit(6)
+#define	HSCR0_RIE	bit(5)
+#define	HSCR0_RXE	bit(4)
+#define	HSCR0_TXE	bit(3)
+#define	HSCR0_TUS	bit(2)
+#define	HSCR0_LBM	bit(1)
+#define	HSCR0_ITR	bit(0)
+
+/* HSSR0 bits */
+
+#define	HSSR0_FRE	bit(5)
+#define	HSSR0_RFS	bit(4)
+#define	HSSR0_TFS	bit(3)
+#define	HSSR0_RAB	bit(2)
+#define	HSSR0_TUR	bit(1)
+#define	HSSR0_EIF	bit(0)
+
+/* HSSR1 bits */
+
+#define	HSSR1_ROR	bit(6)
+#define	HSSR1_CRE	bit(5)
+#define	HSSR1_EOF	bit(4)
+#define	HSSR1_TNF	bit(3)
+#define	HSSR1_RNE	bit(2)
+#define	HSSR1_TBY	bit(1)
+#define	HSSR1_RSY	bit(0)
 
-#endif	/* SA11X0_HSSP_H */
+#endif /* SA11X0_HSSP_H */