From e1adf96ca855bcbf4e1f807fa3f3188965e74673 Mon Sep 17 00:00:00 2001 From: Marcel Telka Date: Mon, 27 Jan 2003 14:49:41 +0000 Subject: [PATCH] 2003-01-27 Marcel Telka * arm/pxa2x0/dma.h: Added DRCMR symbolic names and offsets (suggested by Daniel Samek, patch 675417). Added get_* macros for register bits. git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@322 b68d4a1b-bc3d-0410-92ed-d4ac073336b7 --- include/ChangeLog | 5 ++ include/NEWS | 3 ++ include/arm/pxa2x0/dma.h | 108 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 116 insertions(+) diff --git a/include/ChangeLog b/include/ChangeLog index 4dac0894..c0d0659e 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,8 @@ +2003-01-27 Marcel Telka + + * arm/pxa2x0/dma.h: Added DRCMR symbolic names and offsets (suggested by Daniel Samek, + patch 675417). Added get_* macros for register bits. + 2003-01-17 Marcel Telka * arm/pxa2x0/cm.h: Fixed CKEN_CKEN4 declaration. diff --git a/include/NEWS b/include/NEWS index ca455156..4413af51 100644 --- a/include/NEWS +++ b/include/NEWS @@ -8,6 +8,9 @@ $Id$ - added get_* macros for LCD register bits - fixed TCR_TVBS macro declaration - fixed CKEN_CKEN4 declaration + - added get_* macros for DMA register bits + - added symbolic names and offsets for DRCMR registers (suggested by Daniel + Samek, patch 675417) * Added UCB1400_ADCC_AI_* declarations for UCB1400 (suggested by Juraj Fabo) * Moved ac97.h and ucb1400.h files to device/codec directory * Minor fixes. diff --git a/include/arm/pxa2x0/dma.h b/include/arm/pxa2x0/dma.h index 16da4fad..584a377e 100644 --- a/include/arm/pxa2x0/dma.h +++ b/include/arm/pxa2x0/dma.h @@ -47,6 +47,10 @@ #include #endif +#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA26X) +#define PXA2X0_NOPXA26X +#endif + /* DMA Controller Registers */ #define DMA_BASE 0x40000000 @@ -80,6 +84,56 @@ typedef volatile struct DMA_registers { #define DSADR(i) DMA_pointer->dar[i].dsadr #define DTADR(i) DMA_pointer->dar[i].dtadr #define DCMD(i) DMA_pointer->dar[i].dcmd + +/* DRCMR symbolic names - see Table 5-13 in [1], Table 5-13 in [2] */ + +#define DRCMR_DREQ0 DRCMR(0) +#define DRCMR_DREQ1 DRCMR(1) +#define DRCMR_I2S_RX DRCMR(2) +#define DRCMR_I2S_TX DRCMR(3) +#define DRCMR_BTUART_RX DRCMR(4) +#define DRCMR_BTUART_TX DRCMR(5) +#define DRCMR_FFUART_RX DRCMR(6) +#define DRCMR_FFUART_TX DRCMR(7) +#define DRCMR_AC97_MIC_RX DRCMR(8) +#define DRCMR_AC97_MODEM_RX DRCMR(9) +#define DRCMR_AC97_MODEM_TX DRCMR(10) +#define DRCMR_AC97_AUDIO_RX DRCMR(11) +#define DRCMR_AC97_AUDIO_TX DRCMR(12) +#define DRCMR_SSP_RX DRCMR(13) +#define DRCMR_SSP_TX DRCMR(14) +#if !defined(PXA2X0_NOPXA26X) +#define DRCMR_NSSP_RX DRCMR(15) +#define DRCMR_NSSP_TX DRCMR(16) +#endif /* PXA26x only */ +#define DRCMR_FICP_RX DRCMR(17) +#define DRCMR_FICP_TX DRCMR(18) +#define DRCMR_STUART_RX DRCMR(19) +#define DRCMR_STUART_TX DRCMR(20) +#define DRCMR_MMC_RX DRCMR(21) +#define DRCMR_MMC_TX DRCMR(22) +#if !defined(PXA2X0_NOPXA26X) +#define DRCMR_ASSP_RX DRCMR(23) +#define DRCMR_ASSP_TX DRCMR(24) +#endif /* PXA26x only */ +#define DRCMR_USB_EP1 DRCMR(25) +#define DRCMR_USB_EP2 DRCMR(26) +#define DRCMR_USB_EP3 DRCMR(27) +#define DRCMR_USB_EP4 DRCMR(28) +#if !defined(PXA2X0_NOPXA26X) +#define DRCMR_HWUART_RX DRCMR(29) +#endif /* PXA26x only */ +#define DRCMR_USB_EP6 DRCMR(30) +#define DRCMR_USB_EP7 DRCMR(31) +#define DRCMR_USB_EP8 DRCMR(32) +#define DRCMR_USB_EP9 DRCMR(33) +#if !defined(PXA2X0_NOPXA26X) +#define DRCMR_HWUART_TX DRCMR(34) +#endif /* PXA26x only */ +#define DRCMR_USB_EP11 DRCMR(35) +#define DRCMR_USB_EP12 DRCMR(36) +#define DRCMR_USB_EP13 DRCMR(37) +#define DRCMR_USB_EP14 DRCMR(38) #endif /* LANGUAGE == C */ #define DCSR_OFFSET(i) ((i) << 2) @@ -90,6 +144,56 @@ typedef volatile struct DMA_registers { #define DTADR_OFFSET(i) (0x208 + ((i) << 4)) #define DCMD_OFFSET(i) (0x20C + ((i) << 4)) +/* DRCMR symbolic names offsets - see Table 5-13 in [1], Table 5-13 in [2] */ + +#define DRCMR_DREQ0_OFFSET DRCMR_OFFSET(0) +#define DRCMR_DREQ1_OFFSET DRCMR_OFFSET(1) +#define DRCMR_I2S_RX_OFFSET DRCMR_OFFSET(2) +#define DRCMR_I2S_TX_OFFSET DRCMR_OFFSET(3) +#define DRCMR_BTUART_RX_OFFSET DRCMR_OFFSET(4) +#define DRCMR_BTUART_TX_OFFSET DRCMR_OFFSET(5) +#define DRCMR_FFUART_RX_OFFSET DRCMR_OFFSET(6) +#define DRCMR_FFUART_TX_OFFSET DRCMR_OFFSET(7) +#define DRCMR_AC97_MIC_RX_OFFSET DRCMR_OFFSET(8) +#define DRCMR_AC97_MODEM_RX_OFFSET DRCMR_OFFSET(9) +#define DRCMR_AC97_MODEM_TX_OFFSET DRCMR_OFFSET(10) +#define DRCMR_AC97_AUDIO_RX_OFFSET DRCMR_OFFSET(11) +#define DRCMR_AC97_AUDIO_TX_OFFSET DRCMR_OFFSET(12) +#define DRCMR_SSP_RX_OFFSET DRCMR_OFFSET(13) +#define DRCMR_SSP_TX_OFFSET DRCMR_OFFSET(14) +#if !defined(PXA2X0_NOPXA26X) +#define DRCMR_NSSP_RX_OFFSET DRCMR_OFFSET(15) +#define DRCMR_NSSP_TX_OFFSET DRCMR_OFFSET(16) +#endif /* PXA26x only */ +#define DRCMR_FICP_RX_OFFSET DRCMR_OFFSET(17) +#define DRCMR_FICP_TX_OFFSET DRCMR_OFFSET(18) +#define DRCMR_STUART_RX_OFFSET DRCMR_OFFSET(19) +#define DRCMR_STUART_TX_OFFSET DRCMR_OFFSET(20) +#define DRCMR_MMC_RX_OFFSET DRCMR_OFFSET(21) +#define DRCMR_MMC_TX_OFFSET DRCMR_OFFSET(22) +#if !defined(PXA2X0_NOPXA26X) +#define DRCMR_ASSP_RX_OFFSET DRCMR_OFFSET(23) +#define DRCMR_ASSP_TX_OFFSET DRCMR_OFFSET(24) +#endif /* PXA26x only */ +#define DRCMR_USB_EP1_OFFSET DRCMR_OFFSET(25) +#define DRCMR_USB_EP2_OFFSET DRCMR_OFFSET(26) +#define DRCMR_USB_EP3_OFFSET DRCMR_OFFSET(27) +#define DRCMR_USB_EP4_OFFSET DRCMR_OFFSET(28) +#if !defined(PXA2X0_NOPXA26X) +#define DRCMR_HWUART_RX_OFFSET DRCMR_OFFSET(29) +#endif /* PXA26x only */ +#define DRCMR_USB_EP6_OFFSET DRCMR_OFFSET(30) +#define DRCMR_USB_EP7_OFFSET DRCMR_OFFSET(31) +#define DRCMR_USB_EP8_OFFSET DRCMR_OFFSET(32) +#define DRCMR_USB_EP9_OFFSET DRCMR_OFFSET(33) +#if !defined(PXA2X0_NOPXA26X) +#define DRCMR_HWUART_TX_OFFSET DRCMR_OFFSET(34) +#endif /* PXA26x only */ +#define DRCMR_USB_EP11_OFFSET DRCMR_OFFSET(35) +#define DRCMR_USB_EP12_OFFSET DRCMR_OFFSET(36) +#define DRCMR_USB_EP13_OFFSET DRCMR_OFFSET(37) +#define DRCMR_USB_EP14_OFFSET DRCMR_OFFSET(38) + /* DCSRx bits - see Table 5-7 in [1], Table 5-7 in [2] */ #define DCSR_RUN bit(31) @@ -126,6 +230,7 @@ typedef volatile struct DMA_registers { #define DRCMR_MAPVLD bit(7) #define DRCMR_CHLNUM_MASK bits(3,0) #define DRCMR_CHLNUM(x) bits_val(3,0,x) +#define get_DCMR_CHLNUM(x) bits_get(3,0,x) /* DDADRx bits - see Table 5-9 in [1], Table 5-9 in [2] */ @@ -142,9 +247,12 @@ typedef volatile struct DMA_registers { #define DCMD_ENDIAN bit(18) #define DCMD_SIZE_MASK bits(17,16) #define DCMD_SIZE(x) bits_val(17,16,x) +#define get_DCMD_SIZE(x) bits_get(17,16,x) #define DCMD_WIDTH_MASK bits(15,14) #define DCMD_WIDTH(x) bits_val(15,14,x) +#define get_DCMD_WIDTH(x) bits_get(15,14,x) #define DCMD_LENGTH_MASK bits(12,0) #define DCMD_LENGTH(x) bits_val(12,0,x) +#define get_DCMD_LENGTH(x) bits_get(12,0,x) #endif /* PXA2X0_DMA_H */