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2003-01-17 Marcel Telka <marcel@telka.sk>

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* arm/pxa2x0/lcd.h: Added get_* macros for register bits. Fixed TCR_TVBS macro.


git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@318 b68d4a1b-bc3d-0410-92ed-d4ac073336b7
master
Marcel Telka 22 years ago
parent c8a463bc07
commit e4654942b3
3 changed files with 111 additions and 84 deletions
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4
include/ChangeLog
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@ -1,3 +1,7 @@
2003-01-17 Marcel Telka <marcel@telka.sk>
* arm/pxa2x0/lcd.h: Added get_* macros for register bits. Fixed TCR_TVBS macro.
2003-01-17 Marcel Telka <marcel@telka.sk>
* ac97.h: Moved this

2
include/NEWS
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@ -5,6 +5,8 @@ $Id$
- added MMC commands (Juraj Fabo)
- added register bits for MECR, SXCNFG, SXMRS, MCMEMx, MCATTx, MCIOx, BOOT_DEF
- added OSMRx (x = 0 through 3) macros
- added get_* macros for LCD register bits
- fixed TCR_TVBS macro declaration
* Added UCB1400_ADCC_AI_* declarations for UCB1400 (suggested by Juraj Fabo)
* Moved ac97.h and ucb1400.h files to device/codec directory
* Minor fixes.

189
include/arm/pxa2x0/lcd.h
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@ -119,124 +119,145 @@ typedef volatile struct LCD_registers {
/* LCCR0 bits - see Table 7-2 in [1], Table 7-2 in [2] */
#define LCCR0_OUM bit(21)
#define LCCR0_BM bit(20)
#define LCCR0_PDD_MASK bits(19,12)
#define LCCR0_PDD(x) bits_val(19,12,x)
#define LCCR0_QDM bit(11)
#define LCCR0_DIS bit(10)
#define LCCR0_DPD bit(9)
#define LCCR0_PAS bit(7)
#define LCCR0_EFM bit(6)
#define LCCR0_IUM bit(5)
#define LCCR0_SFM bit(4)
#define LCCR0_LDM bit(3)
#define LCCR0_SDS bit(2)
#define LCCR0_CMS bit(1)
#define LCCR0_ENB bit(0)
#define LCCR0_OUM bit(21)
#define LCCR0_BM bit(20)
#define LCCR0_PDD_MASK bits(19,12)
#define LCCR0_PDD(x) bits_val(19,12,x)
#define get_LCCR0_PDD(x) bits_get(19,12,x)
#define LCCR0_QDM bit(11)
#define LCCR0_DIS bit(10)
#define LCCR0_DPD bit(9)
#define LCCR0_PAS bit(7)
#define LCCR0_EFM bit(6)
#define LCCR0_IUM bit(5)
#define LCCR0_SFM bit(4)
#define LCCR0_LDM bit(3)
#define LCCR0_SDS bit(2)
#define LCCR0_CMS bit(1)
#define LCCR0_ENB bit(0)
/* LCCR1 bits - see Table 7-5 in [1], Table 7-4 in [2] */
#define LCCR1_BLW_MASK bits(31,24)
#define LCCR1_BLW(x) bits_val(31,24,x)
#define LCCR1_ELW_MASK bits(23,16)
#define LCCR1_ELW(x) bits_val(23,16,x)
#define LCCR1_HSW_MASK bits(15,10)
#define LCCR1_HSW(x) bits_val(15,10,x)
#define LCCR1_PPL_MASK bits(9,0)
#define LCCR1_PPL(x) bits_val(9,0,x)
#define LCCR1_BLW_MASK bits(31,24)
#define LCCR1_BLW(x) bits_val(31,24,x)
#define get_LCCR1_BLW(x) bits_get(31,24,x)
#define LCCR1_ELW_MASK bits(23,16)
#define LCCR1_ELW(x) bits_val(23,16,x)
#define get_LCCR1_ELW(x) bits_get(23,16,x)
#define LCCR1_HSW_MASK bits(15,10)
#define LCCR1_HSW(x) bits_val(15,10,x)
#define get_LCCR1_HSW(x) bits_get(15,10,x)
#define LCCR1_PPL_MASK bits(9,0)
#define LCCR1_PPL(x) bits_val(9,0,x)
#define get_LCCR1_PPL(x) bits_get(9,0,x)
/* LCCR2 bits - see Table 7-6 in [1], Table 7-5 in [2] */
#define LCCR2_BFW_MASK bits(31,24)
#define LCCR2_BFW(x) bits_val(31,24,x)
#define LCCR2_EFW_MASK bits(23,16)
#define LCCR2_EFW(x) bits_val(23,16,x)
#define LCCR2_VSW_MASK bits(15,10)
#define LCCR2_VSW(x) bits_val(15,10,x)
#define LCCR2_LPP_MASK bits(9,0)
#define LCCR2_LPP(x) bits_val(9,0,x)
#define LCCR2_BFW_MASK bits(31,24)
#define LCCR2_BFW(x) bits_val(31,24,x)
#define get_LCCR2_BFW(x) bits_get(31,24,x)
#define LCCR2_EFW_MASK bits(23,16)
#define LCCR2_EFW(x) bits_val(23,16,x)
#define get_LCCR2_EFW(x) bits_get(23,16,x)
#define LCCR2_VSW_MASK bits(15,10)
#define LCCR2_VSW(x) bits_val(15,10,x)
#define get_LCCR2_VSW(x) bits_get(15,10,x)
#define LCCR2_LPP_MASK bits(9,0)
#define LCCR2_LPP(x) bits_val(9,0,x)
#define get_LCCR2_LPP(x) bits_get(9,0,x)
/* LCCR3 bits - see Table 7-7 in [1], Table 7-6 in [2] */
#define LCCR3_DPC bit(27)
#define LCCR3_BPP_MASK bits(26,24)
#define LCCR3_BPP(x) bits_val(26,24,x)
#define LCCR3_OEP bit(23)
#define LCCR3_PCP bit(22)
#define LCCR3_HSP bit(21)
#define LCCR3_VSP bit(20)
#define LCCR3_API_MASK bits(19,16)
#define LCCR3_API(x) bits_val(19,16,x)
#define LCCR3_ACB_MASK bits(15,8)
#define LCCR3_ACB(x) bits_val(15,8,x)
#define LCCR3_PCD_MASK bits(7,0)
#define LCCR3_PCD(x) bits_val(7,0,x)
#define LCCR3_DPC bit(27)
#define LCCR3_BPP_MASK bits(26,24)
#define LCCR3_BPP(x) bits_val(26,24,x)
#define get_LCCR3_BPP(x) bits_get(26,24,x)
#define LCCR3_OEP bit(23)
#define LCCR3_PCP bit(22)
#define LCCR3_HSP bit(21)
#define LCCR3_VSP bit(20)
#define LCCR3_API_MASK bits(19,16)
#define LCCR3_API(x) bits_val(19,16,x)
#define get_LCCR3_API(x) bits_get(19,16,x)
#define LCCR3_ACB_MASK bits(15,8)
#define LCCR3_ACB(x) bits_val(15,8,x)
#define get_LCCR3_ACB(x) bits_get(15,8,x)
#define LCCR3_PCD_MASK bits(7,0)
#define LCCR3_PCD(x) bits_val(7,0,x)
#define get_LCCR3_PCD(x) bits_get(7,0,x)
/* FBR0 bits - see Table 7-12 in [1], Table 7-11 in [2] */
#define FBR0_BINT bit(1)
#define FBR0_BRA bit(0)
#define FBR0_BINT bit(1)
#define FBR0_BRA bit(0)
/* FBR1 bits - see Table 7-12 in [1], Table 7-11 in [2] */
#define FBR1_BINT bit(1)
#define FBR1_BRA bit(0)
#define FBR1_BINT bit(1)
#define FBR1_BRA bit(0)
/* LCSR bits - see Table 7-13 in [1], Table 7-12 in [2] */
#define LCSR_SINT bit(10)
#define LCSR_BS bit(9)
#define LCSR_EOF bit(8)
#define LCSR_QD bit(7)
#define LCSR_OU bit(6)
#define LCSR_IUU bit(5)
#define LCSR_IUL bit(4)
#define LCSR_ABC bit(3)
#define LCSR_BER bit(2)
#define LCSR_SOF bit(1)
#define LCSR_LDD bit(0)
#define LCSR_SINT bit(10)
#define LCSR_BS bit(9)
#define LCSR_EOF bit(8)
#define LCSR_QD bit(7)
#define LCSR_OU bit(6)
#define LCSR_IUU bit(5)
#define LCSR_IUL bit(4)
#define LCSR_ABC bit(3)
#define LCSR_BER bit(2)
#define LCSR_SOF bit(1)
#define LCSR_LDD bit(0)
/* LIIDR bits - see Table 7-14 in [1], Table 7-13 in [2] */
#define LIIDR_IFRAMEID_MASK bits(31,3)
#define LIIDR_IFRAMEID(x) bits_val(31,3,x)
#define get_LIIDR_IFRAMEID(x) bits_get(31,3,x)
/* TRGBR bits - see Table 7-15 in [1], Table 7-14 in [2] */
#define TRGBR_TBS_MASK bits(23,16)
#define TRGBR_TBS(x) bits_val(23,16,x)
#define TRGBR_TGS_MASK bits(15,8)
#define TRGBR_TGS(x) bits_val(15,8,x)
#define TRGBR_TRS_MASK bits(7,0)
#define TRGBR_TRS(x) bits_val(7,0,x)
#define TRGBR_TBS_MASK bits(23,16)
#define TRGBR_TBS(x) bits_val(23,16,x)
#define get_TRGBR_TBS(x) bits_get(23,16,x)
#define TRGBR_TGS_MASK bits(15,8)
#define TRGBR_TGS(x) bits_val(15,8,x)
#define get_TRGBR_TGS(x) bits_get(15,8,x)
#define TRGBR_TRS_MASK bits(7,0)
#define TRGBR_TRS(x) bits_val(7,0,x)
#define get_TRGBR_TRS(x) bits_vat(7,0,x)
/* TCR bits - see Table 7-16 in [1], Table 7-15 in [2] */
#define TCR_TED bit(14)
#define TCR_THBS_MASK bits(11,8)
#define TCR_THBS(x) bits_val(11,8,x)
#define TCR_TVBS_MASK bits(7,4)
#define TCR_TVBS(x) bits(7,4,x)
#define TCR_FNAME bit(3)
#define TCR_COAE bit(2)
#define TCR_FNAM bit(1)
#define TCR_COAM bit(0)
#define TCR_TED bit(14)
#define TCR_THBS_MASK bits(11,8)
#define TCR_THBS(x) bits_val(11,8,x)
#define get_TCR_THBS(x) bits_get(11,8,x)
#define TCR_TVBS_MASK bits(7,4)
#define TCR_TVBS(x) bits_val(7,4,x)
#define get_TCR_TVBS(x) bits_get(7,4,x)
#define TCR_FNAME bit(3)
#define TCR_COAE bit(2)
#define TCR_FNAM bit(1)
#define TCR_COAM bit(0)
/* LDCMD0 bits - see Table 7-11 in [1], Table 7-10 in [2] */
#define LDCMD0_PAL bit(26)
#define LDCMD0_SOFINT bit(22)
#define LDCMD0_EOFINT bit(21)
#define LDCMD0_LEN_MASK bits(20,0)
#define LDCMD0_LEN(x) bits_val(20,0,x)
#define LDCMD0_PAL bit(26)
#define LDCMD0_SOFINT bit(22)
#define LDCMD0_EOFINT bit(21)
#define LDCMD0_LEN_MASK bits(20,0)
#define LDCMD0_LEN(x) bits_val(20,0,x)
#define get_LDCMD0_LEN(x) bits_get(20,0,x)
/* LDCMD1 bits - see Table 7-11 in [1], Table 7-10 in [2] */
#define LDCMD1_PAL bit(26)
#define LDCMD1_SOFINT bit(22)
#define LDCMD1_EOFINT bit(21)
#define LDCMD1_LEN_MASK bits(20,0)
#define LDCMD1_LEN(x) bits_val(20,0,x)
#define LDCMD1_PAL bit(26)
#define LDCMD1_SOFINT bit(22)
#define LDCMD1_EOFINT bit(21)
#define LDCMD1_LEN_MASK bits(20,0)
#define LDCMD1_LEN(x) bits_val(20,0,x)
#define get_LDCMD1_LEN(x) bits_get(20,0,x)
#endif /* PXA2X0_LCD_H */

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