[ 2820437 ] ARM9 bus support (Jochen Friedrich)
git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@1665 b68d4a1b-bc3d-0410-92ed-d4ac073336b7master
Arnim Läuger
16 years ago
parent
240bd7b59e
commit
ed8ecbd30d
@ -0,0 +1,571 @@
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/*
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* $Id$
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*
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* ARM9TDMI core bus driver
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* Copyright (C) 2003, Rongkai zhan <zhanrk@163.com>
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* Copyright (C) 2009, Jochen Friedrich <jochen@scram.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
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* 02111-1307, USA.
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*
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*/
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#define ARM9DEBUG 0
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#include <sysdep.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include <unistd.h>
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#include <urjtag/part.h>
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#include <urjtag/bus.h>
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#include <urjtag/chain.h>
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#include <urjtag/bssignal.h>
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#include <urjtag/tap_state.h>
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#include <urjtag/tap_register.h>
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#include <urjtag/data_register.h>
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#include "buses.h"
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#include "generic_bus.h"
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typedef struct
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{
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uint32_t chain; /* Chain number */
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} bus_params_t;
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#define BP ((bus_params_t *) bus->params)
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#define ARM9TDMI_ICE_DBGCTL 0x00
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#define ARM9TDMI_ICE_DBGSTAT 0x01
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#define DEBUG_SPEED 0
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#define SYSTEM_SPEED 1
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#define ARM_NOP 0xE1A00000
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static urj_data_register_t *scann = NULL;
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static urj_data_register_t *scan1 = NULL;
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static urj_data_register_t *scan2 = NULL;
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static uint32_t _data_read;
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/**
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* bus->driver->(*new_bus)
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*
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*/
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static urj_bus_t *
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arm9tdmi_bus_new (urj_chain_t *chain, const urj_bus_driver_t *driver,
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const urj_param_t *cmd_params[])
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{
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return urj_bus_generic_new (chain, driver, sizeof (bus_params_t));
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}
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/**
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* bus->driver->(*printinfo)
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*
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*/
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static void
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arm9tdmi_bus_printinfo (urj_log_level_t ll, urj_bus_t *bus)
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{
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int i;
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for (i = 0; i < bus->chain->parts->len; i++)
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if (bus->part == bus->chain->parts->parts[i])
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break;
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urj_log (ll, _("ARM9TDMI compatible bus driver (JTAG part No. %d)\n"),
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i);
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}
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/**
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* helper functions
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*
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*/
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#if (ARM9DEBUG)
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static void
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arm9tdmi_debug_in_reg(urj_data_register_t *reg)
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{
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int i;
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urj_log(URJ_LOG_LEVEL_ALL, "in :");
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for (i = 0; i < reg->in->len; i++)
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urj_log(URJ_LOG_LEVEL_ALL, reg->in->data[i]?"1":"0");
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urj_log(URJ_LOG_LEVEL_ALL, "\n");
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}
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static void
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arm9tdmi_debug_out_reg(urj_data_register_t *reg)
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{
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int i;
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urj_log(URJ_LOG_LEVEL_ALL, "out :");
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for (i = 0; i < reg->out->len; i++)
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urj_log(URJ_LOG_LEVEL_ALL, reg->out->data[i]?"1":"0");
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urj_log(URJ_LOG_LEVEL_ALL, "\n");
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}
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#endif
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static void
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arm9tdmi_exec_instruction(urj_bus_t *bus, unsigned int c1_inst, unsigned int c1_data, unsigned int flags)
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{
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int i;
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for (i = 0; i < 32; i++)
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scan1->in->data[66-i] = (c1_inst >> i) & 1;
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scan1->in->data[34] = flags;
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scan1->in->data[33] = 0;
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scan1->in->data[32] = 0;
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for (i = 0; i < 32; i++)
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scan1->in->data[i] = (c1_data >> i) & 1;
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#if (ARM9DEBUG)
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arm9tdmi_debug_in_reg(scan1);
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#endif
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urj_tap_chain_shift_data_registers (bus->chain, 1);
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#if (ARM9DEBUG)
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arm9tdmi_debug_out_reg(scan1);
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#endif
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}
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static void
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arm9tdmi_select_scanchain(urj_bus_t *bus, unsigned int chain)
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{
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int i;
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urj_part_set_instruction (bus->part, "SCAN_N");
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urj_tap_chain_shift_instructions (bus->chain);
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for (i = 0; i < scann->in->len; i++)
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scann->in->data[i] = (chain >> i) & 1;
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urj_tap_chain_shift_data_registers (bus->chain, 0);
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}
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static void
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arm9tdmi_ice_read(urj_bus_t *bus, unsigned int reg_addr, unsigned int *reg_val)
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{
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int i;
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for (i = 0; i < 32; i++)
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scan2->in->data[i] = 0;
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for (i = 0; i < 5; i++)
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scan2->in->data[i+32] = (reg_addr >> i) & 1;
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scan2->in->data[37] = 0;
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urj_tap_chain_shift_data_registers (bus->chain, 1);
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for (i = 0; i < 32; i++)
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{
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if (scan2->out->data[i])
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*reg_val |= (1 << i);
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}
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}
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static void
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arm9tdmi_ice_write(urj_bus_t *bus, unsigned int reg_addr, unsigned int reg_val)
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{
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int i;
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for (i = 0; i < 32; i++)
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scan2->in->data[i] = (reg_val >> i) & 1;
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for (i = 0; i < 5; i++)
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scan2->in->data[i+32] = (reg_addr >> i) & 1;
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scan2->in->data[37] = 1;
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urj_tap_chain_shift_data_registers (bus->chain, 0);
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}
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/**
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* low-level memory write
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*
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*/
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static void
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arm9tdmi_write(urj_bus_t *bus, unsigned int addr, unsigned int data, unsigned int sz)
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{
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unsigned int c1_inst, c1_data;
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/*
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* Load R0 with the address to write.
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* Load R1 with the data to write.
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*/
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c1_inst = 0xE59F0000; /* LDR R0, [PC] */
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c1_data = 0;
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, DEBUG_SPEED);
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c1_inst = 0xE59F1000; /* LDR R1, [PC] */
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c1_data = 0;
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, DEBUG_SPEED);
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/* Flush pipeline before SYSTEM_SPEED access */
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c1_inst = ARM_NOP;
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c1_data = 0;
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, DEBUG_SPEED);
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c1_data = addr;
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, DEBUG_SPEED);
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c1_data = data;
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, DEBUG_SPEED);
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c1_data = 0;
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, DEBUG_SPEED);
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if (sz == 32)
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c1_inst = 0xE5801000; /* STR R1, [R0] */
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else if (sz == 16)
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c1_inst = 0xE1C010B0; /* STRH R1, [R0] */
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else if (sz == 8)
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c1_inst = 0xE5C01000; /* STRB R1, [R0] */
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c1_data = 0;
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, DEBUG_SPEED);
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/*
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* Execute instruction at SYSTEM_SPEED as we need to access memory
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*/
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c1_inst = ARM_NOP;
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, SYSTEM_SPEED);
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urj_tap_chain_flush(bus->chain);
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/* Write RESTART instruction into the TAP controller.
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* When the state machine enters the Run-Test/Idle state,
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* the ARM9TDMI core will revert back to system mode,
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* and it will resynchronize clock to MCLK.
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*/
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urj_part_set_instruction (bus->part, "RESTART");
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urj_tap_chain_shift_instructions (bus->chain);
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/*
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* Now, the ARM9TDMI core re-entered the debug state.
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* Before the debug session continues, we must load the
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* TAP controller with the INTEST instruction. We can use
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* the instruction "STR R1, [R1]" running at debug-speed to
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* read out the contents of register R1.
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*/
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urj_part_set_instruction (bus->part, "INTEST1");
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urj_tap_chain_shift_instructions_mode (bus->chain, 0, 1,
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URJ_CHAIN_EXITMODE_UPDATE);
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}
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/**
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* low level memory read
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*
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*/
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static unsigned int
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arm9tdmi_read (urj_bus_t *bus, unsigned int addr, unsigned int sz)
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{
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unsigned int c1_inst, c1_data, result, i;
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/*
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* Load R0 with the address to read
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*/
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c1_inst = 0xE59F0000; /* LDR R0, [PC] */
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c1_data = 0;
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, DEBUG_SPEED);
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c1_inst = ARM_NOP;
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c1_data = 0;
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, DEBUG_SPEED);
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, DEBUG_SPEED);
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c1_data = addr;
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, DEBUG_SPEED);
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c1_data = 0;
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, DEBUG_SPEED);
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if (sz == 32)
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c1_inst = 0xE5901000; /* LDR R1, [R0] */
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else if (sz == 16)
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c1_inst = 0xE1D010B0; /* LDRH R1, [R0] */
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else if (sz == 8)
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c1_inst = 0xE5D01000; /* LDRB R1, [R0] */
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c1_data = 0;
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, DEBUG_SPEED);
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/*
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* Execute instruction at SYSTEM_SPEED as we need to access memory
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*/
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c1_inst = ARM_NOP;
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, SYSTEM_SPEED);
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urj_tap_chain_flush(bus->chain);
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/* Write RESTART instruction into the TAP controller.
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* When the state machine enters the Run-Test/Idle state,
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* the ARM9TDMI core will revert back to system mode,
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* and it will resynchronize clock to MCLK.
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*/
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urj_part_set_instruction (bus->part, "RESTART");
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urj_tap_chain_shift_instructions (bus->chain);
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/*
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* Now, the ARM9TDMI core re-entered the debug state.
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* Before the debug session continues, we must load the
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* TAP controller with the INTEST instruction. We can use
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* the instruction "STR R1, [PC]" running at debug-speed to
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* read out the contents of register R1.
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*/
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urj_part_set_instruction (bus->part, "INTEST1");
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urj_tap_chain_shift_instructions_mode (bus->chain, 0, 1,
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URJ_CHAIN_EXITMODE_UPDATE);
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c1_inst = 0xE58F1000; /* STR R1, [PC] */
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c1_data = 0;
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, DEBUG_SPEED);
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c1_inst = ARM_NOP;
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c1_data = 0;
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, DEBUG_SPEED);
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, DEBUG_SPEED);
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, DEBUG_SPEED);
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result = 0;
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for (i = 0; i < 32; i++)
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{
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if (scan1->out->data[i])
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result |= (1 << i);
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}
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arm9tdmi_exec_instruction(bus, c1_inst, c1_data, DEBUG_SPEED);
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return result;
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}
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/**
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* bus->driver->(*initbus)
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*
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*/
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static int
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arm9tdmi_bus_init (urj_bus_t *bus)
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{
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unsigned int i, status, success;
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if (urj_tap_state (bus->chain) != URJ_TAP_STATE_RUN_TEST_IDLE)
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{
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/* silently skip initialization if TAP isn't in RUNTEST/IDLE state
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this is required to avoid interfering with detect when initbus
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is contained in the part description file
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URJ_BUS_INIT() will be called latest by URJ_BUS_PREPARE() */
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return URJ_STATUS_OK;
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}
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if (scann == NULL)
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scann = urj_part_find_data_register (bus->part, "SCANN");
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if (scan1 == NULL)
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scan1 = urj_part_find_data_register (bus->part, "SCAN1");
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if (scan2 == NULL)
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scan2 = urj_part_find_data_register (bus->part, "SCAN2");
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if (!(scann))
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{
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urj_error_set (URJ_ERROR_NOTFOUND,
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_("SCANN register"));
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return URJ_STATUS_FAIL;
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}
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if (!(scan1))
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{
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urj_error_set (URJ_ERROR_NOTFOUND,
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_("SCAN1 register"));
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return URJ_STATUS_FAIL;
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}
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if (!(scan2))
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{
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urj_error_set (URJ_ERROR_NOTFOUND,
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_("SCAN2 register"));
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return URJ_STATUS_FAIL;
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}
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/*
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* select scan chain 2 -- EmbeddedICE-RT
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*/
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arm9tdmi_select_scanchain(bus, 2);
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urj_part_set_instruction (bus->part, "INTEST2");
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urj_tap_chain_shift_instructions (bus->chain);
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arm9tdmi_ice_write(bus, ARM9TDMI_ICE_DBGCTL, 0x3);
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urj_part_set_instruction (bus->part, "RESTART");
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urj_tap_chain_shift_instructions (bus->chain);
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i = 0;
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success = 0;
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status = 0;
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while (i++ < 10) {
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urj_part_set_instruction (bus->part, "INTEST2");
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urj_tap_chain_shift_instructions (bus->chain);
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arm9tdmi_ice_read(bus, ARM9TDMI_ICE_DBGSTAT, &status);
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if (status & 0x01) {
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success = 1;
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break;
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}
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urj_part_set_instruction (bus->part, "RESTART");
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urj_tap_chain_shift_instructions (bus->chain);
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usleep(100);
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}
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if (!success)
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{
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urj_error_set (URJ_ERROR_TIMEOUT,
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_("Failed to enter debug mode, ctrl=%s"),
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urj_tap_register_get_string (scan2->out));
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return URJ_STATUS_FAIL;
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}
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arm9tdmi_ice_write(bus, ARM9TDMI_ICE_DBGCTL, 0x00);
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urj_log (URJ_LOG_LEVEL_NORMAL, _("The target is halted in "));
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if (status & 0x10)
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urj_log (URJ_LOG_LEVEL_NORMAL, _("THUMB mode.\n"));
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else
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urj_log (URJ_LOG_LEVEL_NORMAL, _("ARM mode.\n"));
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/* select scan chain 1, and use INTEST instruction */
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arm9tdmi_select_scanchain(bus, 1);
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urj_part_set_instruction (bus->part, "INTEST1");
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urj_tap_chain_shift_instructions_mode (bus->chain, 0, 1,
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URJ_CHAIN_EXITMODE_UPDATE);
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bus->initialized = 1;
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return URJ_STATUS_OK;
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}
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/**
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* bus->driver->(*prepare)
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*
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*/
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static void
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arm9tdmi_bus_prepare (urj_bus_t *bus)
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{
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if (!bus->initialized)
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URJ_BUS_INIT (bus);
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}
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/**
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* bus->driver->(*area)
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*
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*/
|
||||
static int
|
||||
arm9tdmi_bus_area (urj_bus_t *bus, uint32_t adr, urj_bus_area_t *area)
|
||||
{
|
||||
|
||||
if (adr < UINT32_C (0xF0000000))
|
||||
{
|
||||
area->description = "USEG : User addresses";
|
||||
area->start = UINT32_C (0x00000000);
|
||||
area->length = UINT64_C (0xF0000000);
|
||||
area->width = 32;
|
||||
}
|
||||
else
|
||||
{
|
||||
area->description = "FLASH : Addresses in flash (boot=0xffff0000)";
|
||||
area->start = UINT32_C (0xF0000000);
|
||||
area->length = UINT64_C (0x10000000);
|
||||
area->width = 16;
|
||||
}
|
||||
return URJ_STATUS_OK;
|
||||
}
|
||||
|
||||
static int
|
||||
get_sz (uint32_t adr)
|
||||
{
|
||||
urj_bus_area_t area;
|
||||
|
||||
arm9tdmi_bus_area (NULL, adr, &area);
|
||||
|
||||
return area.width;
|
||||
}
|
||||
|
||||
/**
|
||||
* bus->driver->(*write)
|
||||
*
|
||||
*/
|
||||
static void
|
||||
arm9tdmi_bus_write (urj_bus_t *bus, uint32_t adr, uint32_t data)
|
||||
{
|
||||
urj_log (URJ_LOG_LEVEL_ALL, "%s:adr=0x%lx,got=0x%lx\n", __func__,
|
||||
(long unsigned) adr, (long unsigned) data);
|
||||
arm9tdmi_write (bus, adr, data, get_sz (adr));
|
||||
}
|
||||
|
||||
/**
|
||||
* bus->driver->(*read)
|
||||
*
|
||||
*/
|
||||
static uint32_t
|
||||
arm9tdmi_bus_read (urj_bus_t *bus, uint32_t adr)
|
||||
{
|
||||
int data = arm9tdmi_read (bus, adr, get_sz (adr));
|
||||
urj_log (URJ_LOG_LEVEL_ALL, "%s:adr=0x%lx,got=0x%lx\n", __func__,
|
||||
(long unsigned) adr, (long unsigned) data);
|
||||
return data;
|
||||
}
|
||||
|
||||
/**
|
||||
* bus->driver->(*read_start)
|
||||
*
|
||||
*/
|
||||
static int
|
||||
arm9tdmi_bus_read_start (urj_bus_t *bus, uint32_t adr)
|
||||
{
|
||||
_data_read = arm9tdmi_read (bus, adr, get_sz (adr));
|
||||
urj_log (URJ_LOG_LEVEL_ALL, "%s:adr=0x%lx, got=0x%lx\n", __func__,
|
||||
(long unsigned) adr, (long unsigned) _data_read);
|
||||
|
||||
return URJ_STATUS_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* bus->driver->(*read_next)
|
||||
*
|
||||
*/
|
||||
static uint32_t
|
||||
arm9tdmi_bus_read_next (urj_bus_t *bus, uint32_t adr)
|
||||
{
|
||||
uint32_t tmp_value = _data_read;
|
||||
_data_read = arm9tdmi_read (bus, adr, get_sz (adr));
|
||||
urj_log (URJ_LOG_LEVEL_ALL, "%s:adr=0x%lx, got=0x%lx\n", __func__,
|
||||
(long unsigned) adr, (long unsigned) _data_read);
|
||||
return tmp_value;
|
||||
}
|
||||
|
||||
/**
|
||||
* bus->driver->(*read_end)
|
||||
*
|
||||
*/
|
||||
static uint32_t
|
||||
arm9tdmi_bus_read_end (urj_bus_t *bus)
|
||||
{
|
||||
return _data_read;
|
||||
}
|
||||
|
||||
|
||||
const urj_bus_driver_t urj_bus_arm9tdmi_bus = {
|
||||
"arm9tdmi",
|
||||
N_("ARM9TDMI compatible bus driver"),
|
||||
arm9tdmi_bus_new,
|
||||
urj_bus_generic_free,
|
||||
arm9tdmi_bus_printinfo,
|
||||
arm9tdmi_bus_prepare,
|
||||
arm9tdmi_bus_area,
|
||||
arm9tdmi_bus_read_start,
|
||||
arm9tdmi_bus_read_next,
|
||||
arm9tdmi_bus_read_end,
|
||||
arm9tdmi_bus_read,
|
||||
arm9tdmi_bus_write,
|
||||
arm9tdmi_bus_init
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue