JTAG Tools package is free software, covered by the GNU General Public
License, and you are welcome to change it and/or distribute copies of it
under certain conditions. There is absolutely no warranty for JTAG Tools.
Please read COPYING file for more info.
</para>
<para>
<emphasis>Warning: This software may damage your hardware!</emphasis>
</para>
<para>
Feedback and contributions are welcome.
</para>
</section>
<section><title>UrJTAG Website</title>
<section><title>JTAG</title>
<para>
The most current version of this documentation and UrJTAG sourcecode
is always available from the project page at Sourceforge, http://urjtag.sourceforge.net
JTAG basics can be found all over the internet. This page should go into
some more details about working with JTAG. What hardwarde do you need, what is
the usage of JTAG, where do I get files. What file formats are available...
</para>
</section>
<section><title>The name "UrJTAG"</title>
<para>
I (Kolja) favour short names, so I thought about adding only a few
letters to "JTAG". The prefix "Ur" in German means "ancestral", an "Ur-Vater"
is a forefather. UrJTAG shall become the forefather, the basis for many other
JTAG tools.
</para>
<section><title>Introduction</title>
<para>
JTAG (IEEE 1149.1) is a serial interface for testing devices with
integrated circuits. The problem that the JTAG interface was designed to solve
is checking if connections between ICs are OK. Therefore you can set and check
in- and outputs of ICs. In order to save pins and logic a very simple serial
design was invented.
</para>
<orderedlist>
<listitem><para>one pin serial input</para></listitem>
<listitem><para>one pin serial output</para></listitem>
<listitem><para>one pin clock</para></listitem>
<listitem><para>one pin control</para></listitem>
</orderedlist>
<para>
The control pin (together with clock) allows to switch device states. A state
machine inside each chip can be controlled, e.g. to reset the device. This
control machine also allows to have two internal shift registers in each device
(although we only have on in- and one output-pin). The registers are called
instruction register (IR) and data register (DR). The current UrJTAG tool
allows you to set the IR and set and get the DR. It doesn't allow you to
directly control the statemachine (yet).
</para>
</section><section><title>Interfaces</title>
<para>
The simplest interface that you can build is the Xilinx parallel cable (also
called DLC5). If your device works with a 5V or 3.3V supply voltage then this
device can even be build just with passive parts. (picture missing here)
UrJTAG also supports a number of other interface adapters.
</para>
</section><section><title>Additions</title>
<para>
In the meantime the jtag specification was used as a basis for programming flash files and debugging processors.
UrJTAG supports programming a couple of different flash devices. It also supports programming of non-flash devices via svf files.
UrJTAG does not support debugging yet. Other open source solutions allow you to debug ARM processors with gdb.
</para>
</section><section><title>BSDL files</title>
<para>
The bsdl file format describes the jtag interface for one IC.
It is a vhdl syntax with the needed information (like pin-names, register lengths and commands) that is usually done by the supplier. e.g. the Xilinx .bsd files are all included in their free web-pack.
</para><para>
Urjtag uses a different file format internally. So in order to add a new device to UrJTAG you need to convert those files and produce a directory structure. Currently there are at least three tools available to do that. Please ask on the mailing list in case of problems with that. Please also send proven working files back to this project.
</para>
</section>
<section><title>SVF files</title>
<para>
The svf file format contains a number of high level commands to drive the jtag bus. For example you can shift the IR or DR and even check for the results.
The Xilinxs impact tool allows you to write this file to program devices.
Kolja Waschk
17 years ago