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VHDL 2.6%
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Marcel Telka 0f42de4e72 2003-07-24 Marcel Telka <marcel@telka.sk> 
* po/POTFILES.in: Removed missing files.
	* configure.ac: Removed VL_LIB_READLINE macro and moved it to ...
	* acinclude.m4: ... this new file.


git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@492 b68d4a1b-bc3d-0410-92ed-d4ac073336b7
 		22 years ago
include 2003-06-12 Marcel Telka <marcel@telka.sk> 22 years ago
jtag 2003-07-24 Marcel Telka <marcel@telka.sk> 22 years ago
libbrux 2003-06-18 Marcel Telka <marcel@telka.sk> 22 years ago