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280 lines
6.0 KiB
HTML
280 lines
6.0 KiB
HTML
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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<HTML
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><HEAD
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><TITLE
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>F.A.Q.</TITLE
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><META
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NAME="GENERATOR"
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CONTENT="Modular DocBook HTML Stylesheet Version 1.79"><LINK
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REL="HOME"
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TITLE="Universal JTAG library, server and tools"
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HREF="index.html"><LINK
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REL="PREVIOUS"
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TITLE="Development"
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HREF="_development.html"><LINK
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REL="NEXT"
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TITLE="Licensing"
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HREF="_licensing.html"><LINK
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REL="STYLESHEET"
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TYPE="text/css"
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HREF="UrJTAG.css"></HEAD
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><BODY
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CLASS="chapter"
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BGCOLOR="#FFFFFF"
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TEXT="#000000"
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LINK="#0000FF"
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VLINK="#840084"
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ALINK="#0000FF"
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><DIV
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CLASS="NAVHEADER"
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><TABLE
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SUMMARY="Header navigation table"
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WIDTH="100%"
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BORDER="0"
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CELLPADDING="0"
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CELLSPACING="0"
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><TR
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><TH
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COLSPAN="3"
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ALIGN="center"
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>Universal JTAG library, server and tools</TH
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></TR
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><TR
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><TD
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WIDTH="10%"
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ALIGN="left"
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VALIGN="bottom"
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><A
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HREF="_development.html"
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ACCESSKEY="P"
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>Prev</A
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></TD
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><TD
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WIDTH="80%"
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VALIGN="bottom"
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></TD
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><TD
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WIDTH="10%"
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ALIGN="right"
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VALIGN="bottom"
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><A
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HREF="_licensing.html"
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ACCESSKEY="N"
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>Next</A
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></TD
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></TR
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></TABLE
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><HR
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ALIGN="LEFT"
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WIDTH="100%"></DIV
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><DIV
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CLASS="chapter"
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><H1
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><A
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NAME="_f_a_q"
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></A
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>Chapter 5. F.A.Q.</H1
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><P
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>For a list of known problems in current versions, please also check the "Bugs"
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tracker at the UrJTAG website!</P
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><P
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></P
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><DIV
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CLASS="variablelist"
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><DL
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><DT
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>Q. The documentation is incomplete. Where can I get more information?</DT
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><DD
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><P
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> A. Please ask in the "Using UrJTAG" Forum on <A
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HREF="http://urjtag.org"
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TARGET="_top"
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>http://urjtag.org</A
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>
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</P
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></DD
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><DT
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>Q. My flash isn't detected or can't be programmed. What can I do?</DT
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><DD
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><P
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> A. Please record the output of the "detect" and "detectflash" commands and ask in the Forum. If possible, re-compile UrJTAG before with "—enable-jedec-exp" to get extra information.
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</P
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></DD
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><DT
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>Q. My CPU/FPGA/etc. chip isn't detected. What can I do?</DT
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><DD
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><P
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> A. First try to get hold of a "BSDL" description of the chip from the vendor, and specify where to find this file to UrJTAG using "bsdl path" before you "detect". Second, a bus driver has to be selected. Maybe "ejtag" or "prototype" work.
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</P
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></DD
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><DT
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>Q. When I type "cable parallel 0x378 DLC5" (in a Cygwin environment) I get "Unknown port driver: parallel"?</DT
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><DD
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><P
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> A. Please install the Cygwin ioperm package, and re-configure/compile.
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</P
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></DD
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><DT
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>Q. When I type "cable parallel 0x378 DLC5" (in a Cygwin environment) I get "Error: Cable initialization failed!".</DT
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><DD
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><P
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> A. Please install ioperm.sys driver using <TT
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CLASS="literal"
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>ioperm -i</TT
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> command.
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</P
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></DD
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><DT
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>Q. When running autogen.sh, I get "Can't exec "autopoint": No such file or directory"</DT
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><DD
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><P
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> A. You need the headers for gettext (e.g. Debian package "gettext-devel").
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</P
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></DD
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><DT
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>Q. When running autogen.sh, it complains about missing CVS</DT
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><DD
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><P
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> A. The easiest solution is to actually install CVS for this step, just to get around this error message.
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</P
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></DD
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><DT
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>Q. During compilation, I get "svf_bison.y: No such file or directory"</DT
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><DD
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><P
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> A. You need "bison".
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</P
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></DD
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><DT
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>Q. During compilation, I get "flex: can't open … src/svf/svf_flex.l"</DT
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><DD
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><P
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> A. You need "flex"
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</P
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></DD
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><DT
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>Q. During compilation, I get "src/svf/svf_flex.l", line 27: unrecognized %option: bison-locations"</DT
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><DD
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><P
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> A. You need a newer version of flex. It should be 2.5.31 or newer;
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Unfortunately, Cygwin comes with only 2.5.4a. You may try to compile and
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install a newer version of flex from source to solve this. The distributed
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source tarball contains source pregenerated with a current flex version,
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you need flex yourself only to compile from fresh SVN checkouts.
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</P
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></DD
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><DT
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>Q. When running "make install", I get "Permission denied" errors</DT
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><DD
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><P
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> A. If you want to install into a system directory (the default /usr/local is one), you'll have to run "make install" as the superuser, e.g. do "sudo make install".
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</P
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></DD
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><DT
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>Q. My BSDL file defines the bus DAT as bit_vector(15 downto 0), how should I access single elements?</DT
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><DD
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><P
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> A. BSDL syntax is an extension of the VHDL language. Array elements are indexed with
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parentheses: DAT(4) selects index number 4 of the DAT vector. Also refer to the "print
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signals" command.
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</P
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></DD
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><DT
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>Q. My board requires certain signals to be set to dedicated values before external memories can be accessed.</DT
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><DD
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><P
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> A. Most (if not all) BSR-based bus drivers allow for static configurations of
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pins that are controlled by BSR bits. Apply the required "set" commands before
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issueing the "initbus …" command. These settings are preserved by all bus
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related commands if they don't collide with the signals required for bus operation.
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</P
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></DD
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><DT
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>Q. My USB pod seems slow.</DT
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><DD
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><P
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> A. USB-based JTAG pods suffer from a couple of intrinsic issues. Consider the
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following to get maximum performance:
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</P
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><P
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></P
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><UL
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><LI
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><P
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> Run UrJTAG on native linux. Cygwin and VMWare are reportedly slower.
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</P
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></LI
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><LI
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><P
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> Connect the pod via a high speed USB hub to a high speed USB host port.
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Even though the pod is a full speed device, it benefits from the shorter
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turn-around times between host and hub.
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</P
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></LI
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></UL
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></DD
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></DL
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></DIV
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></DIV
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><DIV
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CLASS="NAVFOOTER"
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><HR
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ALIGN="LEFT"
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WIDTH="100%"><TABLE
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SUMMARY="Footer navigation table"
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WIDTH="100%"
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BORDER="0"
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CELLPADDING="0"
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CELLSPACING="0"
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><TR
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><TD
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WIDTH="33%"
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ALIGN="left"
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VALIGN="top"
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><A
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HREF="_development.html"
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ACCESSKEY="P"
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>Prev</A
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></TD
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><TD
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WIDTH="34%"
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ALIGN="center"
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VALIGN="top"
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><A
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HREF="index.html"
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ACCESSKEY="H"
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>Home</A
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></TD
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><TD
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ALIGN="right"
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VALIGN="top"
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HREF="_licensing.html"
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ACCESSKEY="N"
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>Next</A
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></TD
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></TR
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><TR
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><TD
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WIDTH="33%"
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ALIGN="left"
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VALIGN="top"
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>Development</TD
|
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><TD
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WIDTH="34%"
|
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ALIGN="center"
|
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VALIGN="top"
|
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> </TD
|
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><TD
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WIDTH="33%"
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ALIGN="right"
|
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VALIGN="top"
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>Licensing</TD
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></TR
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></TABLE
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></DIV
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></BODY
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></HTML
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> |