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305 lines
6.6 KiB
HTML
305 lines
6.6 KiB
HTML
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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<HTML
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><HEAD
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><TITLE
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>General</TITLE
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><META
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NAME="GENERATOR"
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CONTENT="Modular DocBook HTML Stylesheet Version 1.79"><LINK
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REL="HOME"
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TITLE="Universal JTAG library, server and tools"
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TITLE="Copyright"
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HREF="_copyright.html"><LINK
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REL="NEXT"
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TITLE="UrJTAG"
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HREF="_urjtag.html"><LINK
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REL="STYLESHEET"
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TYPE="text/css"
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HREF="UrJTAG.css"></HEAD
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><BODY
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CLASS="chapter"
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BGCOLOR="#FFFFFF"
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><TR
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><TH
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>Universal JTAG library, server and tools</TH
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></TR
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><TR
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><TD
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WIDTH="10%"
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ALIGN="left"
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><A
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>Prev</A
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>Next</A
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><DIV
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CLASS="chapter"
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><H1
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><A
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NAME="_general"
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></A
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>Chapter 2. General</H1
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><DIV
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CLASS="section"
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><H1
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CLASS="section"
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><A
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NAME="_jtag"
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>2.1. JTAG</A
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></H1
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><P
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>JTAG basics can be found all over the Internet. This section should go into
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some more details about working with JTAG. What hardware do you need, what is
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the usage of JTAG, where do I get files. What file formats are available…</P
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><DIV
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CLASS="section"
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><H2
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CLASS="section"
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><A
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NAME="_introduction"
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>2.1.1. Introduction</A
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></H2
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><P
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>JTAG (IEEE 1149.1) is a serial interface for testing devices with
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integrated circuits. The problem that the JTAG interface was designed to solve
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is checking if connections between ICs are OK. Therefore you can set and check
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in- and outputs of ICs. In order to save pins and logic a very simple serial
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design was invented.</P
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><P
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></P
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><UL
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><LI
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><P
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> One pin serial input
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</P
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></LI
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><LI
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><P
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> One pin serial output
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</P
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></LI
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><LI
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><P
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> One pin clock
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</P
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></LI
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><LI
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><P
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> One pin control
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</P
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></LI
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></UL
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><P
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>The control pin (together with clock) allows to switch device states. A state
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machine inside each chip can be controlled, e.g. to reset the device. This
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control machine also allows to have two internal shift registers in each device
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(although we only have on in- and one output-pin). The registers are called
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instruction register (IR) and data register (DR). The current UrJTAG tool
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allows you to set the IR and set and get the DR. It doesn't allow you to
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directly control the state machine (yet).</P
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></DIV
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><DIV
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CLASS="section"
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><H2
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CLASS="section"
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><A
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NAME="_interfaces"
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>2.1.2. Interfaces</A
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></H2
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><P
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>The simplest interface that you can build is like the Xilinx parallel cable
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(also called DLC5). If your device works with a 5V or 3.3V supply voltage then
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this device can even be built just with passive parts. (picture missing here)
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UrJTAG also supports a number of other interface adapters.</P
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></DIV
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><DIV
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CLASS="section"
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><H2
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CLASS="section"
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><A
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NAME="_additions"
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>2.1.3. Additions</A
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></H2
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><P
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>In the meantime the JTAG specification was used as a basis for programming
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flash files and debugging processors. UrJTAG supports programming a couple of
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different flash devices. It also supports programming of non-flash devices via
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SVF files. UrJTAG does not support debugging yet. Other open source solutions
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such as OpenOCD allow you to debug ARM processors with gdb.</P
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></DIV
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><DIV
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CLASS="section"
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><H2
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CLASS="section"
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><A
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NAME="_bsdl_and_urjtag_data_files"
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>2.1.4. BSDL and UrJTAG data files</A
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></H2
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><P
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>The BSDL file format describes the JTAG interface for one IC. It is a VHDL
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syntax with the needed information (like pin-names, register lengths and
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commands) that is usually created by the supplier. e.g. Xilinx BSDL files are
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all included in their free web-pack (using file extension ".bsd").</P
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><P
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>UrJTAG uses a different file format internally. So in order to add a new device
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to UrJTAG you need to convert those files and produce a directory structure.
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Currently there are at least three tools available to do that; included with
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UrJTAG is "bsdl2jtag". Please ask on the mailing list in case of problems with
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that. Please also send proven working files back to this project.</P
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><P
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>Starting with post-0.7 releases, UrJTAG contains a BSDL subsystem that
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retrieves the descriptions for chips in the chain from BSDL files on the
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fly. "bsdl2jtag" is in fact a wrapper that uses the BSDL subsystem to
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convert the BSDL file.</P
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></DIV
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><DIV
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CLASS="section"
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><H2
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CLASS="section"
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><A
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NAME="_svf_files"
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>2.1.5. SVF files</A
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></H2
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><P
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>The SVF file format contains a number of high level commands to drive the JTAG
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bus. For example you can shift the IR or DR and even check for the results.
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The Xilinx Impact and Altera QuartusII tools allow you to write this file to
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program devices.</P
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><P
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>The player has been developed according to the "Serial Vector Format
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Specification", Revision E, 8 March 1999 issued by ASSET InterTech, Inc. The
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full specification can be found at
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<A
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HREF="http://www.asset-intertech.com/support/svf.pdf"
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TARGET="_top"
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>http://www.asset-intertech.com/support/svf.pdf</A
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>.</P
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><P
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>UrJTAG features an "SVF player" that can read SVF files and perform the
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described actions on the bus.</P
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><P
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>SVF parser and lexer are also copyright 2002, CDS at <A
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HREF="http://www-csd.ijs.si/"
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TARGET="_top"
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>http://www-csd.ijs.si/</A
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>.
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They have been reused from the "Experimental Boundary Scan" project at
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<A
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HREF="http://ebsp.sourceforge.net/"
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TARGET="_top"
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>http://ebsp.sourceforge.net/</A
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>.</P
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></DIV
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><DIV
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CLASS="section"
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><H2
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CLASS="section"
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><A
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NAME="_jam_stapl_files"
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>2.1.6. JAM/STAPL files</A
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></H2
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><P
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>Another format for describing actions over JTAG interfaces is STAPL, actually
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standardized as JEDEC "JESD-71A". Compared to SVF, it looks more like an
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actual programming language and features looping, conditional execution, and
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more. STAPL is not yet supported by UrJTAG.</P
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></DIV
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></DIV
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></DIV
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CLASS="NAVFOOTER"
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>Prev</A
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>Home</A
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HREF="_urjtag.html"
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>Next</A
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>Copyright</TD
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