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/*
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* $Id$
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*
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* ARM specific declarations
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* Copyright (C) 2002, 2003 ETC s.r.o.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the ETC s.r.o. nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
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*
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* Documentation:
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* [1] ARM Limited, "ARM Architecture Reference Manual", June 2000,
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* Order Number: ARM DDI 0100E
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*
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*/
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#ifndef ARM_H
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#define ARM_H
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#include <openwince.h>
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/* PSR bits - see A2.5 in [1] */
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#define PSR_N bit(31)
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#define PSR_Z bit(30)
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#define PSR_C bit(29)
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#define PSR_V bit(28)
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#define PSR_Q bit(27) /* E variants of the ARMV5 and above - see A2.5.1 in [1] */
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#define PSR_I bit(7)
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#define PSR_F bit(6)
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#define PSR_T bit(5)
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#define PSR_MODE_MASK bits(4,0)
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#define PSR_MODE(x) ((x) & PSR_MODE_MASK)
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#define PSR_MODE_USR PSR_MODE(0x10)
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#define PSR_MODE_FIQ PSR_MODE(0x11)
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#define PSR_MODE_IRQ PSR_MODE(0x12)
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#define PSR_MODE_SVC PSR_MODE(0x13)
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#define PSR_MODE_ABT PSR_MODE(0x17)
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#define PSR_MODE_UND PSR_MODE(0x1B)
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#define PSR_MODE_SYS PSR_MODE(0x1F) /* ARMV4 and above */
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/* System Control Coprocessor (SCC) Register 1: Control Register (CR) bits - see B2.4 in [1] */
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#define SCC_CR_L4 bit(15)
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#define SCC_CR_RR bit(14)
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#define SCC_CR_V bit(13)
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#define SCC_CR_I bit(12)
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#define SCC_CR_Z bit(11)
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#define SCC_CR_F bit(10)
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#define SCC_CR_R bit(9)
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#define SCC_CR_S bit(8)
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#define SCC_CR_B bit(7)
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#define SCC_CR_L bit(6)
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#define SCC_CR_D bit(5)
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#define SCC_CR_P bit(4)
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#define SCC_CR_W bit(3)
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#define SCC_CR_C bit(2)
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#define SCC_CR_A bit(1)
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#define SCC_CR_M bit(0)
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#endif /* ARM_H */
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