2005-05-31 Branislav Petrovsky <brano111@szm.sk>
* h8/h8s2357/bus.h: New file. * h8/h8s2357/dmac.h: Ditto. * h8/h8s2357/ic.h: Ditto. * h8/h8s2357/ppg.h: Ditto. * h8/h8s2357/wdt.h: Ditto. * Makefile.am (nobase_openwinceinc_HEADERS): Added new files. git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@632 b68d4a1b-bc3d-0410-92ed-d4ac073336b7master
Branislav Petrovsk
20 years ago
parent
7b570dd2fe
commit
023edaaa53
@ -0,0 +1,191 @@
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/*
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* $Id$
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*
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* H8S/2357 BUS Controller Registers
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* Copyright (C) 2005 Elcom s.r.o.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holders nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Written by Branislav Petrovsky <brano111@szm.sk>, 2005.
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*
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* Documentation:
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* [1] Renesas Technology Corp., "Hitachi 16-Bit Single-chip Microcomputer
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* H8S/2357 Series, H8S/2357F-ZTAT, H8S/2398F-ZTAT Hardware Manual",
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* Rev. 5.0, 11/22/02, Order Number: ADE-602-146D
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*
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*/
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#ifndef H8S2357_BUS_H
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#define H8S2357_BUS_H
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#include <common.h>
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#if LANGUAGE == C
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#include <stdint.h>
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#endif
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/* BUS registers */
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#define BUS_BASE 0xfffffed0
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#if LANGUAGE == C
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typedef struct BUS_registers {
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uint8_t abwcr;
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uint8_t astcr;
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uint8_t wcrh;
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uint8_t wcrl;
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uint8_t bcrh;
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uint8_t bcrl;
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uint8_t mcr;
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uint8_t dramcr;
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uint8_t rtcnt;
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uint8_t rtcor;
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uint8_t __reserved;
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uint8_t ramer;
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} BUS_registers_t;
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#define BUS_pointer ((BUS_registers_t*) BUS_BASE)
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#define ABWCR BUS_pointer->abwcr
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#define ASTCR BUS_pointer->astcr
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#define WCRH BUS_pointer->wcrh
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#define WCRL BUS_pointer->wcrl
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#define BCRH BUS_pointer->bcrh
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#define BCRL BUS_pointer->bcrl
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#define MCR BUS_pointer->mcr
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#define DRAMCR BUS_pointer->dramcr
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#define RTCNT BUS_pointer->rtcnt
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#define RTCOR BUS_pointer->rtcor
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#define RAMER BUS_pointer->ramer
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#endif /* LANGUAGE == C */
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#define ABWCR_OFFSET 0x00
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#define ASTCR_OFFSET 0x01
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#define WCRH_OFFSET 0x02
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#define WCRL_OFFSET 0x03
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#define BCRH_OFFSET 0x04
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#define BCRL_OFFSET 0x05
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#define MCR_OFFSET 0x06
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#define DRAMCR_OFFSET 0x07
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#define RTCNT_OFFSET 0x08
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#define RTCOR_OFFSET 0x09
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#define RAMER_OFFSET 0x0b
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/* ABWCR bits */
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#define ABWCR_ABW7 bit(7)
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#define ABWCR_ABW6 bit(6)
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#define ABWCR_ABW5 bit(5)
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#define ABWCR_ABW4 bit(4)
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#define ABWCR_ABW3 bit(3)
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#define ABWCR_ABW2 bit(2)
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#define ABWCR_ABW1 bit(1)
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#define ABWCR_ABW0 bit(0)
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/* ASTCR bits */
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#define ASTCR_AST7 bit(7)
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#define ASTCR_AST6 bit(6)
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#define ASTCR_AST5 bit(5)
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#define ASTCR_AST4 bit(4)
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#define ASTCR_AST3 bit(3)
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#define ASTCR_AST2 bit(2)
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#define ASTCR_AST1 bit(1)
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#define ASTCR_AST0 bit(0)
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/* WCRH bits */
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#define WCRH_W7_MASK bits(7,6)
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#define WCRH_W7(x) bits_val(7,6,x)
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#define get_WCRH_W7(x) bits_get(7,6,x)
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#define WCRH_W6_MASK bits(5,4)
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#define WCRH_W6(x) bits_val(5,4,x)
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#define get_WCRH_W6(x) bits_get(5,4,x)
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#define WCRH_W5_MASK bits(3,2)
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#define WCRH_W5(x) bits_val(3,2,x)
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#define get_WCRH_W5(x) bits_get(3,2,x)
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#define WCRH_W4_MASK bits(1,0)
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#define WCRH_W4(x) bits_val(1,0,x)
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#define get_WCRH_W4(x) bits_get(1,0,x)
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/* WCRL bits */
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#define WCRL_W3_MASK bits(7,6)
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#define WCRL_W3(x) bits_val(7,6,x)
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#define get_WCRL_W3(x) bits_get(7,6,x)
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#define WCRL_W2_MASK bits(5,4)
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#define WCRL_W2(x) bits_val(5,4,x)
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#define get_WCRL_W2(x) bits_get(5,4,x)
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#define WCRL_W1_MASK bits(3,2)
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#define WCRL_W1(x) bits_val(3,2,x)
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#define get_WCRL_W1(x) bits_get(3,2,x)
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#define WCRL_W0_MASK bits(1,0)
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#define WCRL_W0(x) bits_val(1,0,x)
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#define get_WCRL_W0(x) bits_get(1,0,x)
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/* BCRH bits */
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#define BCRH_ICIS1 bit(7)
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#define BCRH_ICIS0 bit(6)
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#define BCRH_BRSTRM bit(5)
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#define BCRH_BRSTS1 bit(4)
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#define BCRH_BRSTS0 bit(3)
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#define BCRH_RMTS_MASK bits(2,0)
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#define BCRH_RMTS(x) bits_val(2,0,x)
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#define get_BCRH_RMTS(x) bits_get(2,0,x)
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/* BCRL bits */
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#define BCRL_BRLE bit(7)
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#define BCRL_BREQOE bit(6)
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#define BCRL_EAE bit(5)
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#define BCRL_LCASS bit(4)
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#define BCRL_DDS bit(3)
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#define BCRL_WDBE bit(1)
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#define BCRL_WAITE bit(0)
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/* MCR bits */
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#define MCR_TPC bit(7)
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#define MCR_BE bit(6)
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#define MCR_RCDM bit(5)
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#define MCR_CW2 bit(4)
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#define MCR_MXC_MASK bits(3,2)
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#define MCR_MXC(x) bits_val(3,2,x)
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#define get_MCR_MXC(x) bits_get(3,2,x)
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#define MCR_RLW_MASK bits(1,0)
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#define MCR_RLW(x) bits_val(1,0,x)
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#define get_MCR_RLW(x) bits_get(1,0,x)
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/* DRAMCR bits */
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#define DRAMCR_RFSHE bit(7)
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#define DRAMCR_RCW bit(6)
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#define DRAMCR_RMODE bit(5)
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#define DRAMCR_CMF bit(4)
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#define DRAMCR_CMIE bit(3)
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#define DRAMCR_CKS_MASK bits(2,0)
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#define DRAMCR_CKS(x) bits_val(2,0,x)
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#define get_DRAMCR_CKS(x) bits_get(2,0,x)
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/* RAMER bits */
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#define RAMER_RAMS bit(3)
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#define RAMER_RAM_MASK bits(2,0)
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#define RAMER_RAM(x) bits_val(2,0,x)
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#define get_RAMER_RAM(x) bits_get(2,0,x)
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#endif /* H8S2357_BUS_H */
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@ -0,0 +1,184 @@
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/*
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* $Id$
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*
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* H8S/2357 DMAC Registers
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* Copyright (C) 2005 Elcom s.r.o.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holders nor the names of its contributors
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* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
|
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Written by Branislav Petrovsky <brano111@szm.sk>, 2005.
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*
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* Documentation:
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* [1] Renesas Technology Corp., "Hitachi 16-Bit Single-chip Microcomputer
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* H8S/2357 Series, H8S/2357F-ZTAT, H8S/2398F-ZTAT Hardware Manual",
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* Rev. 5.0, 11/22/02, Order Number: ADE-602-146D
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*
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*/
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#ifndef H8S2357_DMAC_H
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#define H8S2357_DMAC_H
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#include <common.h>
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#if LANGUAGE == C
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#include <stdint.h>
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#endif
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/* DMAC registers */
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#define DMAC_BASE 0xfffffee0
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#if LANGUAGE == C
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typedef struct DMAC_registers {
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uint32_t mar0a;
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uint16_t ioar0a;
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uint16_t etcr0a;
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uint32_t mar0b;
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uint16_t ioar0b;
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uint16_t etcr0b;
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uint32_t mar1a;
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uint16_t ioar1a;
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uint16_t etcr1a;
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uint32_t mar1b;
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uint16_t ioar1b;
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uint16_t etcr1b;
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uint8_t dmawer;
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uint8_t dmatcr;
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uint8_t dmacr0a;
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uint8_t dmacr0b;
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uint8_t dmacr1a;
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uint8_t dmacr1b;
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uint8_t dmabcr;
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} DMAC_registers_t;
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#define DMAC_pointer ((DMAC_registers_t*) DMAC_BASE)
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#define MAR0A DMAC_pointer->mar0a
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#define IOAR0A DMAC_pointer->ioar0a
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#define ETCR0A DMAC_pointer->etcr0a
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#define MAR0B DMAC_pointer->mar0b
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#define IOAR0B DMAC_pointer->ioar0b
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#define ETCR0B DMAC_pointer->etcr0b
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#define MAR1A DMAC_pointer->mar1a
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#define IOAR1A DMAC_pointer->ioar1a
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#define ETCR1A DMAC_pointer->etcr1a
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#define MAR1B DMAC_pointer->mar1b
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#define IOAR1B DMAC_pointer->ioar1b
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#define ETCR1B DMAC_pointer->etcr1b
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#define DMAWER DMAC_pointer->dmawer
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#define DMATCR DMAC_pointer->dmatcr
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#define DMACR0A DMAC_pointer->dmacr0a
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#define DMACR0B DMAC_pointer->dmacr0b
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#define DMACR1A DMAC_pointer->dmacr1a
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#define DMACR1B DMAC_pointer->dmacr1b
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#define DMABCR DMAC_pointer->dmabcr
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#endif /* LANGUAGE == C */
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#define MAR0A_OFFSET 0x00
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#define IOAR0A_OFFSET 0x04
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#define ETCR0A_OFFSET 0x06
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#define MAR0B_OFFSET 0x08
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#define IOAR0B_OFFSET 0x0c
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#define ETCR0B_OFFSET 0x0e
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#define MAR1A_OFFSET 0x10
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#define IOAR1A_OFFSET 0x14
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#define ETCR1A_OFFSET 0x16
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#define MAR1B_OFFSET 0x18
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#define IOAR1B_OFFSET 0x1c
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#define ETCR1B_OFFSET 0x1e
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#define DMAWER_OFFSET 0x20
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#define DMATCR_OFFSET 0x21
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#define DMACR0A_OFFSET 0x22
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#define DMACR0B_OFFSET 0x23
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#define DMACR1A_OFFSET 0x24
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#define DMACR1B_OFFSET 0x25
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#define DMABCR_OFFSET 0x26
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/* DMAWER bits */
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#define DMAWER_WE1B bit(3)
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#define DMAWER_WE1A bit(2)
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#define DMAWER_WE0B bit(1)
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#define DMAWER_WE0A bit(0)
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/* DMATCR bits */
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#define DMATCR_TEE1 bit(5)
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#define DMATCR_TEE0 bit(4)
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/* DMACR bits - short address mode */
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#define DMACR_DTSZ bit(7)
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#define DMACR_DTID bit(6)
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#define DMACR_RPE bit(5)
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#define DMACR_DTDIR bit(4)
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#define DMACR_DTF_MASK bits(3,0)
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#define DMACR_DTF(x) bits_val(3,0,x)
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#define get_DMACR_DTF(x) bits_get(3,0,x)
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/* DMACRA bits - full address mode */
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#define DMACRA_DTSZ bit(7)
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#define DMACRA_SAID bit(6)
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#define DMACRA_SAIDE bit(5)
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#define DMACRA_BLKDIR bit(4)
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#define DMACRA_BLKE bit(3)
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/* DMACRB bits - full address mode */
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#define DMACRB_DAID bit(6)
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#define DMACRB_DAIDE bit(5)
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#define DMACRB_DTF_MASK bits(3,0)
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#define DMACRB_DTF(x) bits_val(3,0,x)
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#define get_DMACRB_DTF(x) bits_get(3,0,x)
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/* DMABCR bits - short address mode */
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#define DMABCR_FAE1 bit(15)
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#define DMABCR_FAE0 bit(14)
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#define DMABCR_SAE1 bit(13)
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#define DMABCR_SAE0 bit(12)
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#define DMABCR_DTA1B bit(11)
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#define DMABCR_DTA1A bit(10)
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#define DMABCR_DTA0B bit(9)
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#define DMABCR_DTA0A bit(8)
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#define DMABCR_DTE1B bit(7)
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#define DMABCR_DTE1A bit(6)
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#define DMABCR_DTE0B bit(5)
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#define DMABCR_DTE0A bit(4)
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#define DMABCR_DTIE1B bit(3)
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#define DMABCR_DTIE1A bit(2)
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#define DMABCR_DTIE0B bit(1)
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#define DMABCR_DTIE0A bit(0)
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/* DMABCR bits - full address mode */
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#define DMABCR_FAE1 bit(15)
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#define DMABCR_FAE0 bit(14)
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#define DMABCR_DTA1 bit(11)
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#define DMABCR_DTA0 bit(9)
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#define DMABCR_DTME1 bit(7)
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#define DMABCR_DTE1 bit(6)
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#define DMABCR_DTME0 bit(5)
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#define DMABCR_DTE0 bit(4)
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#define DMABCR_DTIE1B bit(3)
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#define DMABCR_DTIE1A bit(2)
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#define DMABCR_DTIE0B bit(1)
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#define DMABCR_DTIE0A bit(0)
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#endif /* H8S2357_DMAC_H */
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@ -0,0 +1,157 @@
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/*
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* $Id$
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*
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* H8S/2357 Interrupt Controller (IC) Registers
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* Copyright (C) 2005 Elcom s.r.o.
|
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* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the copyright holders nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Written by Branislav Petrovsky <brano111@szm.sk>, 2005.
|
||||
*
|
||||
* Documentation:
|
||||
* [1] Renesas Technology Corp., "Hitachi 16-Bit Single-chip Microcomputer
|
||||
* H8S/2357 Series, H8S/2357F-ZTAT, H8S/2398F-ZTAT Hardware Manual",
|
||||
* Rev. 5.0, 11/22/02, Order Number: ADE-602-146D
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef H8S2357_IC_H
|
||||
#define H8S2357_IC_H
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#if LANGUAGE == C
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
/* interrupt registers */
|
||||
|
||||
#define IPR_BASE 0xfffffec4
|
||||
#define IC_BASE 0xffffff2c
|
||||
|
||||
#if LANGUAGE == C
|
||||
typedef struct IPR_registers {
|
||||
uint8_t ipra;
|
||||
uint8_t iprb;
|
||||
uint8_t iprc;
|
||||
uint8_t iprd;
|
||||
uint8_t ipre;
|
||||
uint8_t iprf;
|
||||
uint8_t iprg;
|
||||
uint8_t iprh;
|
||||
uint8_t ipri;
|
||||
uint8_t iprj;
|
||||
uint8_t iprk;
|
||||
} IPR_registers_t;
|
||||
|
||||
typedef struct IC_registers {
|
||||
uint16_t iscr;
|
||||
uint8_t ier;
|
||||
uint8_t isr;
|
||||
} IC_registers_t;
|
||||
|
||||
#define IPR_pointer ((IPR_registers_t*) IPR_BASE)
|
||||
#define IC_pointer ((IC_registers_t*) IC_BASE)
|
||||
|
||||
#define IPRA IPR_pointer->ipra
|
||||
#define IPRB IPR_pointer->iprb
|
||||
#define IPRC IPR_pointer->iprc
|
||||
#define IPRD IPR_pointer->iprd
|
||||
#define IPRE IPR_pointer->ipre
|
||||
#define IPRF IPR_pointer->iprf
|
||||
#define IPRG IPR_pointer->iprg
|
||||
#define IPRH IPR_pointer->iprh
|
||||
#define IPRI IPR_pointer->ipri
|
||||
#define IPRJ IPR_pointer->iprj
|
||||
#define IPRK IPR_pointer->iprk
|
||||
|
||||
#define ISCR IC_pointer->iscr
|
||||
#define IER IC_pointer->ier
|
||||
#define ISR IC_pointer->isr
|
||||
#endif /* LANGUAGE == C */
|
||||
|
||||
#define IPRA_OFFSET 0x00
|
||||
#define IPRB_OFFSET 0x01
|
||||
#define IPRC_OFFSET 0x02
|
||||
#define IPRD_OFFSET 0x03
|
||||
#define IPRE_OFFSET 0x04
|
||||
#define IPRF_OFFSET 0x05
|
||||
#define IPRG_OFFSET 0x06
|
||||
#define IPRH_OFFSET 0x07
|
||||
#define IPRI_OFFSET 0x08
|
||||
#define IPRJ_OFFSET 0x09
|
||||
#define IPRK_OFFSET 0x0a
|
||||
|
||||
#define ISCR_OFFSET 0x00
|
||||
#define IER_OFFSET 0x02
|
||||
#define ISR_OFFSET 0x03
|
||||
|
||||
/* IPR bits */
|
||||
#define IPR_IPR6 bit(6)
|
||||
#define IPR_IPR5 bit(5)
|
||||
#define IPR_IPR4 bit(4)
|
||||
#define IPR_IPR2 bit(2)
|
||||
#define IPR_IPR1 bit(1)
|
||||
#define IPR_IPR0 bit(0)
|
||||
|
||||
/* ISCR bits */
|
||||
#define ISCR_IRQ7SCB bit(15)
|
||||
#define ISCR_IRQ7SCA bit(14)
|
||||
#define ISCR_IRQ6SCB bit(13)
|
||||
#define ISCR_IRQ6SCA bit(12)
|
||||
#define ISCR_IRQ5SCB bit(11)
|
||||
#define ISCR_IRQ5SCA bit(10)
|
||||
#define ISCR_IRQ4SCB bit(9)
|
||||
#define ISCR_IRQ4SCA bit(8)
|
||||
#define ISCR_IRQ3SCB bit(7)
|
||||
#define ISCR_IRQ3SCA bit(6)
|
||||
#define ISCR_IRQ2SCB bit(5)
|
||||
#define ISCR_IRQ2SCA bit(4)
|
||||
#define ISCR_IRQ1SCB bit(3)
|
||||
#define ISCR_IRQ1SCA bit(2)
|
||||
#define ISCR_IRQ0SCB bit(1)
|
||||
#define ISCR_IRQ0SCA bit(0)
|
||||
|
||||
/* IER bits */
|
||||
#define IER_IRQ7E bit(7)
|
||||
#define IER_IRQ6E bit(6)
|
||||
#define IER_IRQ5E bit(5)
|
||||
#define IER_IRQ4E bit(4)
|
||||
#define IER_IRQ3E bit(3)
|
||||
#define IER_IRQ2E bit(2)
|
||||
#define IER_IRQ1E bit(1)
|
||||
#define IER_IRQ0E bit(0)
|
||||
|
||||
/* ISR bits */
|
||||
#define ISR_IRQ7F bit(7)
|
||||
#define ISR_IRQ6F bit(6)
|
||||
#define ISR_IRQ5F bit(5)
|
||||
#define ISR_IRQ4F bit(4)
|
||||
#define ISR_IRQ3F bit(3)
|
||||
#define ISR_IRQ2F bit(2)
|
||||
#define ISR_IRQ1F bit(1)
|
||||
#define ISR_IRQ0F bit(0)
|
||||
|
||||
#endif /* H8S2357_IC_H */
|
||||
@ -0,0 +1,176 @@
|
||||
/*
|
||||
* $Id$
|
||||
*
|
||||
* H8S/2357 PPG Registers
|
||||
* Copyright (C) 2005 Elcom s.r.o.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the copyright holders nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Written by Branislav Petrovsky <brano111@szm.sk>, 2005.
|
||||
*
|
||||
* Documentation:
|
||||
* [1] Renesas Technology Corp., "Hitachi 16-Bit Single-chip Microcomputer
|
||||
* H8S/2357 Series, H8S/2357F-ZTAT, H8S/2398F-ZTAT Hardware Manual",
|
||||
* Rev. 5.0, 11/22/02, Order Number: ADE-602-146D
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef H8S2357_PPG_H
|
||||
#define H8S2357_PPG_H
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#if LANGUAGE == C
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
/* PPG registers */
|
||||
|
||||
#define PPG_BASE 0xffffff46
|
||||
|
||||
#if LANGUAGE == C
|
||||
typedef struct PPG_registers {
|
||||
uint8_t pcr;
|
||||
uint8_t pmr;
|
||||
uint8_t nderh;
|
||||
uint8_t nedrl;
|
||||
uint8_t podrh;
|
||||
uint8_t podrl;
|
||||
uint8_t ndrh;
|
||||
uint8_t ndrl;
|
||||
uint8_t ndrh_d;
|
||||
uint8_t ndrl_d;
|
||||
} PPG_registers_t;
|
||||
|
||||
#define PPG_pointer ((PPG_registers_t*) PPG_BASE)
|
||||
|
||||
#define PCR PPG_pointer->pcr
|
||||
#define PMR PPG_pointer->pmr
|
||||
#define NDERH PPG_pointer->nderh
|
||||
#define NEDRL PPG_pointer->nedrl
|
||||
#define PODRH PPG_pointer->podrh
|
||||
#define PODRL PPG_pointer->podrl
|
||||
#define NDRH PPG_pointer->ndrh
|
||||
#define NDRL PPG_pointer->ndrl
|
||||
#define NDRH_d PPG_pointer->ndrh_d
|
||||
#define NDRL_d PPG_pointer->ndrl_d
|
||||
#endif /* LANGUAGE == C */
|
||||
|
||||
#define PCR_OFFSET 0x00
|
||||
#define PMR_OFFSET 0x01
|
||||
#define NDERH_OFFSET 0x02
|
||||
#define NEDRL_OFFSET 0x03
|
||||
#define PODRH_OFFSET 0x04
|
||||
#define PODRL_OFFSET 0x05
|
||||
#define NDRH_OFFSET 0x06
|
||||
#define NDRL_OFFSET 0x07
|
||||
#define NDRH_OFFSET_d 0x08
|
||||
#define NDRL_OFFSET_d 0x09
|
||||
|
||||
/* PCR bits */
|
||||
#define PCR_G3CMS_MASK bits(7,6)
|
||||
#define PCR_G3CMS(x) bits_val(7,6,x)
|
||||
#define get_PCR_G3CMS(x) bits_get(7,6,x)
|
||||
#define PCR_G2CMS_MASK bits(5,4)
|
||||
#define PCR_G2CMS(x) bits_val(5,4,x)
|
||||
#define get_PCR_G2CMS(x) bits_get(5,4,x)
|
||||
#define PCR_G1CMS_MASK bits(3,2)
|
||||
#define PCR_G1CMS(x) bits_val(3,2,x)
|
||||
#define get_PCR_G1CMS(x) bits_get(3,2,x)
|
||||
#define PCR_G0CMS_MASK bits(1,0)
|
||||
#define PCR_G0CMS(x) bits_val(1,0,x)
|
||||
#define get_PCR_G0CMS(x) bits_get(1,0,x)
|
||||
|
||||
/* PMR bits */
|
||||
#define PMR_G3INV bit(7)
|
||||
#define PMR_G2INV bit(6)
|
||||
#define PMR_G1INV bit(5)
|
||||
#define PMR_G0INV bit(4)
|
||||
#define PMR_G3NOV bit(3)
|
||||
#define PMR_G2NOV bit(2)
|
||||
#define PMR_G1NOV bit(1)
|
||||
#define PMR_G0NOV bit(0)
|
||||
|
||||
/* NDERH bits */
|
||||
#define NDERH_NDER15 bit(7)
|
||||
#define NDERH_NDER14 bit(6)
|
||||
#define NDERH_NDER13 bit(5)
|
||||
#define NDERH_NDER12 bit(4)
|
||||
#define NDERH_NDER11 bit(3)
|
||||
#define NDERH_NDER10 bit(2)
|
||||
#define NDERH_NDER9 bit(1)
|
||||
#define NDERH_NDER8 bit(0)
|
||||
|
||||
/* NDERL bits */
|
||||
#define NDERL_NDER7 bit(7)
|
||||
#define NDERL_NDER6 bit(6)
|
||||
#define NDERL_NDER5 bit(5)
|
||||
#define NDERL_NDER4 bit(4)
|
||||
#define NDERL_NDER3 bit(3)
|
||||
#define NDERL_NDER2 bit(2)
|
||||
#define NDERL_NDER1 bit(1)
|
||||
#define NDERL_NDER0 bit(0)
|
||||
|
||||
/* PODRH bits */
|
||||
#define PODRH_POD15 bit(7)
|
||||
#define PODRH_POD14 bit(6)
|
||||
#define PODRH_POD13 bit(5)
|
||||
#define PODRH_POD12 bit(4)
|
||||
#define PODRH_POD11 bit(3)
|
||||
#define PODRH_POD10 bit(2)
|
||||
#define PODRH_POD9 bit(1)
|
||||
#define PODRH_POD8 bit(0)
|
||||
|
||||
/* PODRL bits */
|
||||
#define PODRL_POD7 bit(7)
|
||||
#define PODRL_POD6 bit(6)
|
||||
#define PODRL_POD5 bit(5)
|
||||
#define PODRL_POD4 bit(4)
|
||||
#define PODRL_POD3 bit(3)
|
||||
#define PODRL_POD2 bit(2)
|
||||
#define PODRL_POD1 bit(1)
|
||||
#define PODRL_POD0 bit(0)
|
||||
|
||||
/* NDRH bits */
|
||||
#define NDRH_NDR15 bit(7)
|
||||
#define NDRH_NDR14 bit(6)
|
||||
#define NDRH_NDR13 bit(5)
|
||||
#define NDRH_NDR12 bit(4)
|
||||
#define NDRH_NDR11 bit(3)
|
||||
#define NDRH_NDR10 bit(2)
|
||||
#define NDRH_NDR9 bit(1)
|
||||
#define NDRH_NDR8 bit(0)
|
||||
|
||||
/* NDRL bits */
|
||||
#define NDRL_NDR7 bit(7)
|
||||
#define NDRL_NDR6 bit(6)
|
||||
#define NDRL_NDR5 bit(5)
|
||||
#define NDRL_NDR4 bit(4)
|
||||
#define NDRL_NDR3 bit(3)
|
||||
#define NDRL_NDR2 bit(2)
|
||||
#define NDRL_NDR1 bit(1)
|
||||
#define NDRL_NDR0 bit(0)
|
||||
|
||||
#endif /* H8S2357_PPG_H */
|
||||
@ -0,0 +1,105 @@
|
||||
/*
|
||||
* $Id$
|
||||
*
|
||||
* H8S/2357 WDT Registers
|
||||
* Copyright (C) 2005 Elcom s.r.o.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the copyright holders nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Written by Branislav Petrovsky <brano111@szm.sk>, 2005.
|
||||
*
|
||||
* Documentation:
|
||||
* [1] Renesas Technology Corp., "Hitachi 16-Bit Single-chip Microcomputer
|
||||
* H8S/2357 Series, H8S/2357F-ZTAT, H8S/2398F-ZTAT Hardware Manual",
|
||||
* Rev. 5.0, 11/22/02, Order Number: ADE-602-146D
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef H8S2357_WDT_H
|
||||
#define H8S2357_WDT_H
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#if LANGUAGE == C
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
/* WDT registers */
|
||||
|
||||
#define WDT_BASE 0xffffffbc
|
||||
|
||||
#if LANGUAGE == C
|
||||
typedef struct WDT_registers {
|
||||
union {
|
||||
union {
|
||||
uint16_t tcsr;
|
||||
uint16_t tcnt;
|
||||
} _write;
|
||||
struct {
|
||||
uint8_t tcsr;
|
||||
uint8_t tcnt;
|
||||
} _read;
|
||||
} _timer;
|
||||
union {
|
||||
union {
|
||||
uint16_t rstcsr;
|
||||
} _write;
|
||||
struct {
|
||||
uint8_r __reserved;
|
||||
uint8_t rstcsr;
|
||||
} _read;
|
||||
} _rstcsr;
|
||||
} WDT_registers_t;
|
||||
|
||||
#define WDT_pointer ((WDT_registers_t*) WDT_BASE)
|
||||
|
||||
#define TCSR_r WDT_pointer->_timer._read.tcsr
|
||||
#define TCNT_r WDT_pointer->_timer._read.tcnt
|
||||
#define RSTCSR_r WDT_pointer->_rstcsr._read.rstcsr
|
||||
#define TCSR_w WDT_pointer->_timer._write.tcsr
|
||||
#define TCNT_w WDT_pointer->_timer._write.tcnt
|
||||
#define RSTCSR_w WDT_pointer->_rstcsr._write.rstcsr
|
||||
#endif /* LANGUAGE == C */
|
||||
|
||||
#define TCSR_OFFSET 0x00
|
||||
#define TCNT_OFFSET_w 0x00
|
||||
#define TCNT_OFFSET_r 0x01
|
||||
#define RSTCSR_OFFSET_w 0x02
|
||||
#define RSTCSR_OFFSET_r 0x03
|
||||
|
||||
/* TCSR bits */
|
||||
#define TCSR_OWF bit(7)
|
||||
#define TCSR_WTIT bit(6)
|
||||
#define TCSR_TME bit(5)
|
||||
#define TCSR_CKS_MASK bits(2,0)
|
||||
#define TCSR_CKS(x) bits_val(2,0,x)
|
||||
#define get_TCSR_CKS(x) bits_get(2,0,x)
|
||||
|
||||
/* RSTCSR bits */
|
||||
#define RSTCSR_WOVF bit(7)
|
||||
#define RSTCSR_RSTE bit(6)
|
||||
#define RSTCSR_RSTS bit(5)
|
||||
|
||||
#endif /* H8S2357_WDT_H */
|
||||
Loading…
Reference in New Issue