2005-05-27 Branislav Petrovsky <brano111@szm.sk>
* h8/h8s2357/adc.h: New file. * h8/h8s2357/sci.h: Ditto. * h8/h8s2357/tpu.h: Ditto. * Makefile.am (nobase_openwinceinc_HEADERS): Added new files. git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@629 b68d4a1b-bc3d-0410-92ed-d4ac073336b7master
Branislav Petrovsk
20 years ago
parent
e83c98699c
commit
0b8605b6ee
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/*
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* $Id$
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*
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* H8S/2357 ADC Registers
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* Copyright (C) 2005 Elcom s.r.o.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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||||
* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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||||
* 3. Neither the name of the copyright holders nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Written by Branislav Petrovsky <brano111@szm.sk>, 2005.
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*
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* Documentation:
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* [1] Renesas Technology Corp., "Hitachi 16-Bit Single-chip Microcomputer
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* H8S/2357 Series, H8S/2357F-ZTAT, H8S/2398F-ZTAT Hardware Manual",
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* Rev. 5.0, 11/22/02, Order Number: ADE-602-146D
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*
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*/
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#ifndef H8S2357_ADC_H
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#define H8S2357_ADC_H
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#include <common.h>
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#if LANGUAGE == C
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#include <stdint.h>
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#endif
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/* ADC registers */
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#define ADC_BASE 0xffffff90
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#if LANGUAGE == C
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typedef struct ADC_registers {
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uint8_t addrah;
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uint8_t addral;
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uint8_t addrbh;
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uint8_t addrbl;
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uint8_t addrch;
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uint8_t addrcl;
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uint8_t addrdh;
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uint8_t addrdl;
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uint8_t adcsr;
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uint8_t adcr;
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} ADC_registers_t;
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#define ADC_pointer ((ADC_registers_t*) ADC_BASE)
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#define ADDRAH ADC_pointer->addrah
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#define ADDRAL ADC_pointer->addral
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#define ADDRBH ADC_pointer->addrbh
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#define ADDRBL ADC_pointer->addrbl
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#define ADDRCH ADC_pointer->addrch
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#define ADDRCL ADC_pointer->addrcl
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#define ADDRDH ADC_pointer->addrdh
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#define ADDRDL ADC_pointer->addrdl
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#define ADCSR ADC_pointer->adcsr
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#define ADCR ADC_pointer->adcr
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#endif /* LANGUAGE == C */
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#define ADDRAH_OFFSET 0x00
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#define ADDRAL_OFFSET 0x01
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#define ADDRBH_OFFSET 0x02
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#define ADDRBL_OFFSET 0x03
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#define ADDRCH_OFFSET 0x04
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#define ADDRCL_OFFSET 0x05
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#define ADDRDH_OFFSET 0x06
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#define ADDRDL_OFFSET 0x07
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#define ADCSR_OFFSET 0x08
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#define ADCR_OFFSET 0x09
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/* ADDR bits */
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#define ADDR_AD9 bit(7)
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#define ADDR_AD8 bit(6)
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#define ADDR_AD7 bit(5)
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#define ADDR_AD6 bit(4)
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#define ADDR_AD5 bit(3)
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#define ADDR_AD4 bit(2)
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#define ADDR_AD3 bit(1)
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#define ADDR_AD2 bit(0)
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#define ADDR_AD1 bit(7)
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#define ADDR_AD0 bit(6)
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/* ADCSR bits */
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#define ADCSR_ADF bit(7)
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#define ADCSR_ADIE bit(6)
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#define ADCSR_ADST bit(5)
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#define ADCSR_SCAN bit(4)
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#define ADCSR_CKS bit(3)
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#define ADCSR_CH_MASK bits(2,0)
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#define ADCSR_CH(x) bits_val(2,0,x)
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#define get_ADCSR_CH(x) bits_get(2,0,x)
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/* ADCR bits */
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#define ADCR_TRGS1 bit(7)
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#define ADCR_TRGS0 bit(6)
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#endif /* H8S2357_ADC_H */
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@ -0,0 +1,142 @@
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/*
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* $Id$
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*
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* H8S/2357 SCI Registers
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* Copyright (C) 2005 Elcom s.r.o.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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||||
* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the copyright holders nor the names of its contributors
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||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Written by Branislav Petrovsky <brano111@szm.sk>, 2005.
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*
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* Documentation:
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* [1] Renesas Technology Corp., "Hitachi 16-Bit Single-chip Microcomputer
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* H8S/2357 Series, H8S/2357F-ZTAT, H8S/2398F-ZTAT Hardware Manual",
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* Rev. 5.0, 11/22/02, Order Number: ADE-602-146D
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*
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*/
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#ifndef H8S2357_SCI_H
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#define H8S2357_SCI_H
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#include <common.h>
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#if LANGUAGE == C
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#include <stdint.h>
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#endif
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/* SCI registers */
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#define SCI0_BASE 0xffffff78
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#define SCI1_BASE 0xffffff80
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#define SCI2_BASE 0xffffff88
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#if LANGUAGE == C
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typedef struct SCI_registers {
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uint8_t smr;
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uint8_t brr;
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uint8_t scr;
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uint8_t tdr;
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uint8_t ssr;
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uint8_t rdr;
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uint8_t scmr;
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} SCI_registers_t;
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#define SCI0_pointer ((SCI_registers_t*) SCI0_BASE)
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#define SCI1_pointer ((SCI_registers_t*) SCI1_BASE)
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#define SCI2_pointer ((SCI_registers_t*) SCI2_BASE)
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#define SMR0 SCI0_pointer->smr
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#define BRR0 SCI0_pointer->brr
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#define SCR0 SCI0_pointer->scr
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#define TDR0 SCI0_pointer->tdr
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#define SSR0 SCI0_pointer->ssr
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#define RDR0 SCI0_pointer->rdr
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#define SCMR0 SCI0_pointer->scmr
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#define SMR1 SCI1_pointer->smr
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#define BRR1 SCI1_pointer->brr
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#define SCR1 SCI1_pointer->scr
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#define TDR1 SCI1_pointer->tdr
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#define SSR1 SCI1_pointer->ssr
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#define RDR1 SCI1_pointer->rdr
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#define SCMR1 SCI1_pointer->scmr
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#define SMR2 SCI2_pointer->smr
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#define BRR2 SCI2_pointer->brr
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#define SCR2 SCI2_pointer->scr
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#define TDR2 SCI2_pointer->tdr
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#define SSR2 SCI2_pointer->ssr
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#define RDR2 SCI2_pointer->rdr
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#define SCMR2 SCI2_pointer->scmr
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#endif /* LANGUAGE == C */
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#define SMR_OFFSET 0x00
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#define BRR_OFFSET 0x01
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#define SCR_OFFSET 0x02
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#define TDR_OFFSET 0x03
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#define SSR_OFFSET 0x04
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#define RDR_OFFSET 0x05
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#define SCMR_OFFSET 0x06
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/* SMR bits */
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#define SMR_CA bit(7)
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#define SMR_GM bit(7)
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#define SMR_CHR bit(6)
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#define SMR_PE bit(5)
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#define SMR_OE bit(4)
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#define SMR_STOP bit(3)
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#define SMR_MP bit(2)
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#define SMR_CKS_MASK bits(1,0)
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#define SMR_CKS(x) bits_val(1,0,x)
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#define get_SMR_CKS(x) bits_get(1,0,x)
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/* SCR bits */
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#define SCR_TIE bit(7)
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#define SCR_RIE bit(6)
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#define SCR_TE bit(5)
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#define SCR_RE bit(4)
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#define SCR_MPIE bit(3)
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#define SCR_TEIE bit(2)
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#define SCR_CKE_MASK bits(1,0)
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#define SCR_CKE(x) bits_val(1,0,x)
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#define get_SCR_CKE(x) bits_get(1,0,x)
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/* SSR bits */
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#define SSR_TDRE bit(7)
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#define SSR_RDFR bit(6)
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#define SSR_ORER bit(5)
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#define SSR_FER bit(4)
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#define SSR_ERS bit(4)
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#define SSR_PER bit(3)
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#define SSR_TEND bit(2)
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#define SSR_MPB bit(1)
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#define SSR_MPBT bit(0)
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/* SCMR bits */
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#define SCMR_SDIR bit(3)
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#define SCMR_SINV bit(2)
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#define SCMR_SMIF bit(0)
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#endif /* H8S2357_SCI_H */
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@ -0,0 +1,234 @@
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/*
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* $Id$
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*
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* H8S/2357 TPU0 to TPU5 Registers
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* Copyright (C) 2005 Elcom s.r.o.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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||||
* 3. Neither the name of the copyright holders nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Written by Branislav Petrovsky <brano111@szm.sk>, 2005.
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*
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* Documentation:
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* [1] Renesas Technology Corp., "Hitachi 16-Bit Single-chip Microcomputer
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* H8S/2357 Series, H8S/2357F-ZTAT, H8S/2398F-ZTAT Hardware Manual",
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* Rev. 5.0, 11/22/02, Order Number: ADE-602-146D
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*
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*/
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#ifndef H8S2357_TPU_H
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#define H8S2357_TPU_H
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#include <common.h>
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#if LANGUAGE == C
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#include <stdint.h>
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#endif
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/* TPU registers */
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#define TPU0_BASE 0xffffffd0
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#define TPU1_BASE 0xffffffe0
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#define TPU2_BASE 0xfffffff0
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#define TPU3_BASE 0xfffffe80
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#define TPU4_BASE 0xfffffe90
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#define TPU5_BASE 0xfffffea0
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#define TPU_COMMON_BASE 0xffffffc0
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#if LANGUAGE == C
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typedef struct TPU_registers {
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uint8_t tcr;
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uint8_t tmdr;
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uint8_t tiorh; /* tior in TPU1, TPU2, TPU4, TPU5 */
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uint8_t tiorl; /* only for TPU0 and TPU3 */
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uint8_t tier;
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uint8_t tsr;
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uint16_t tcnt;
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uint16_t tgra;
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uint16_t tgrb;
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uint16_t tgrc; /* only for TPU0 and TPU3 */
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uint16_t tgrd; /* only for TPU0 and TPU3 */
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} TPU_registers_t;
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typedef struct TPU_common_registers {
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uint8_t tstr;
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uint8_t tsyr;
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} TPU_common_registers_t;
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#define TPU0_pointer ((TPU_registers_t*) TPU0_BASE)
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#define TPU1_pointer ((TPU_registers_t*) TPU1_BASE)
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#define TPU2_pointer ((TPU_registers_t*) TPU2_BASE)
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#define TPU3_pointer ((TPU_registers_t*) TPU3_BASE)
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#define TPU4_pointer ((TPU_registers_t*) TPU4_BASE)
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#define TPU5_pointer ((TPU_registers_t*) TPU5_BASE)
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#define TPU_COMMON_pointer ((TPU_common_registers_t*) TPU_COMMON_BASE)
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#define TCR0 TPU0_pointer->tcr
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#define TMDR0 TPU0_pointer->tmdr
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#define TIOR0H TPU0_pointer->tiorh
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#define TIOR0L TPU0_pointer->tiorl
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#define TIER0 TPU0_pointer->tier
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#define TSR0 TPU0_pointer->tsr
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#define TCNT0 TPU0_pointer->tcnt
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#define TGR0A TPU0_pointer->tgra
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#define TGR0B TPU0_pointer->tgrb
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#define TGR0C TPU0_pointer->tgrc
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#define TGR0D TPU0_pointer->tgrd
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#define TCR1 TPU1_pointer->tcr
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#define TMDR1 TPU1_pointer->tmdr
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#define TIOR1 TPU1_pointer->tiorh
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#define TIER1 TPU1_pointer->tier
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#define TSR1 TPU1_pointer->tsr
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#define TCNT1 TPU1_pointer->tcnt
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#define TGR1A TPU1_pointer->tgra
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#define TGR1B TPU1_pointer->tgrb
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#define TCR2 TPU2_pointer->tcr
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#define TMDR2 TPU2_pointer->tmdr
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#define TIOR2 TPU2_pointer->tiorh
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#define TIER2 TPU2_pointer->tier
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#define TSR2 TPU2_pointer->tsr
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#define TCNT2 TPU2_pointer->tcnt
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#define TGR2A TPU2_pointer->tgra
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#define TGR2B TPU2_pointer->tgrb
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#define TCR3 TPU3_pointer->tcr
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#define TMDR3 TPU3_pointer->tmdr
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#define TIOR3H TPU3_pointer->tiorh
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#define TIOR3L TPU3_pointer->tiorl
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#define TIER3 TPU3_pointer->tier
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#define TSR3 TPU3_pointer->tsr
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#define TCNT3 TPU3_pointer->tcnt
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#define TGR3A TPU3_pointer->tgra
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#define TGR3B TPU3_pointer->tgrb
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#define TGR3C TPU3_pointer->tgrc
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#define TGR3D TPU3_pointer->tgrd
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#define TCR4 TPU4_pointer->tcr
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#define TMDR4 TPU4_pointer->tmdr
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#define TIOR4 TPU4_pointer->tiorh
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#define TIER4 TPU4_pointer->tier
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#define TSR4 TPU4_pointer->tsr
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#define TCNT4 TPU4_pointer->tcnt
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#define TGR4A TPU4_pointer->tgra
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#define TGR4B TPU4_pointer->tgrb
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#define TCR5 TPU5_pointer->tcr
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#define TMDR5 TPU5_pointer->tmdr
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#define TIOR5 TPU5_pointer->tiorh
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#define TIER5 TPU5_pointer->tier
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#define TSR5 TPU5_pointer->tsr
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#define TCNT5 TPU5_pointer->tcnt
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#define TGR5A TPU5_pointer->tgra
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#define TGR5B TPU5_pointer->tgrb
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#define TSTR TPU_COMMON_pointer->tstr
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#define TSYR TPU_COMMON_pointer->tsyr
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#endif /* LANGUAGE == C */
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#define TCR_OFFSET 0x00
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#define TMDR_OFFSET 0x01
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#define TIOR_OFFSET 0x02 /* TPU1, TPU2, TPU4, TPU5 */
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#define TIORH_OFFSET 0x02 /* TPU0, TPU3 */
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#define TIORL_OFFSET 0x03 /* TPU0, TPU3 */
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#define TIER_OFFSET 0x04
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#define TSR_OFFSET 0x05
|
||||
#define TCNT_OFFSET 0x06
|
||||
#define TGRA_OFFSET 0x08
|
||||
#define TGRB_OFFSET 0x0a
|
||||
#define TGRC_OFFSET 0x0c /* TPU0, TPU3 */
|
||||
#define TGRD_OFFSET 0x0e /* TPU0, TPU3 */
|
||||
|
||||
#define TSTR_OFFSET 0x00
|
||||
#define TSYR_OFFSET 0x01
|
||||
|
||||
/* TCR bits */
|
||||
#define TCR_CCLR_MASK bits(7,5) /* bit 7 used only in TPU0 and TPU3 */
|
||||
#define TCR_CCLR(x) bits_val(7,5,x)
|
||||
#define get_TCR_CCLR(x) bits_get(7,5,x)
|
||||
#define TCR_CKEG_MASK bits(4,3)
|
||||
#define TCR_CKEG(x) bits_val(4,3,x)
|
||||
#define get_TCR_CKEG(x) bits_get(4,3,x)
|
||||
#define TCR_TPSC_MASK bits(2,0)
|
||||
#define TCR_TPSC(x) bits_val(2,0,x)
|
||||
#define get_TCR_TPSC(x) bits_get(2,0,x)
|
||||
|
||||
/* TMDR bits */
|
||||
#define TMDR_BFB bit(5) /* only for TPU0 and TPU3 */
|
||||
#define TMDR_BFA bit(4) /* only for TPU0 and TPU3 */
|
||||
#define TMDR_MD_MASK bits(3,0)
|
||||
#define TMDR_MD(x) bits_val(3,0,x)
|
||||
#define get_TMDR_MD(x) bits_get(3,0,x)
|
||||
|
||||
/* TIOR bits (TPU1, TPU2, TPU4, TPU5) */
|
||||
#define TIOR_IOB_MASK bits(7,4)
|
||||
#define TIOR_IOB(x) bits_val(7,4,x)
|
||||
#define get_TIOR_IOB(x) bits_get(7,4,x)
|
||||
#define TIOR_IOA_MASK bits(3,0)
|
||||
#define TIOR_IOA(x) bits_val(3,0,x)
|
||||
#define get_TIOR_IOA(x) bits_get(3,0,x)
|
||||
|
||||
/* TIORH bits (TPU0, TPU3) */
|
||||
#define TIORH_IOB_MASK bits(7,4)
|
||||
#define TIORH_IOB(x) bits_val(7,4,x)
|
||||
#define get_TIORH_IOB(x) bits_get(7,4,x)
|
||||
#define TIORH_IOA_MASK bits(3,0)
|
||||
#define TIORH_IOA(x) bits_val(3,0,x)
|
||||
#define get_TIORH_IOA(x) bits_get(3,0,x)
|
||||
|
||||
/* TIORL bits (TPU0, TPU3) */
|
||||
#define TIORL_IOD_MASK bits(7,4)
|
||||
#define TIORL_IOD(x) bits_val(7,4,x)
|
||||
#define get_TIORL_IOD(x) bits_get(7,4,x)
|
||||
#define TIORL_IOC_MASK bits(3,0)
|
||||
#define TIORL_IOC(x) bits_val(3,0,x)
|
||||
#define get_TIORL_IOC(x) bits_get(3,0,x)
|
||||
|
||||
/* TSR bits */
|
||||
#define TSR_TCFD bit(7) /* only for TPU1, TPU2, TPU4, TPU5 */
|
||||
#define TSR_TCFU bit(5) /* only for TPU1, TPU2, TPU4, TPU5 */
|
||||
#define TSR_TCFV bit(4)
|
||||
#define TSR_TGFD bit(3) /* only for TPU0 and TPU3 */
|
||||
#define TSR_TGFC bit(2) /* only for TPU0 and TPU3 */
|
||||
#define TSR_TGFB bit(1)
|
||||
#define TSR_TGFA bit(0)
|
||||
|
||||
/* TSTR bits */
|
||||
#define TSTR_CST5 bit(5)
|
||||
#define TSTR_CST4 bit(4)
|
||||
#define TSTR_CST3 bit(3)
|
||||
#define TSTR_CST2 bit(2)
|
||||
#define TSTR_CST1 bit(1)
|
||||
#define TSTR_CST0 bit(0)
|
||||
|
||||
/* TSYR bits */
|
||||
#define TSYR_SYNC5 bit(5)
|
||||
#define TSYR_SYNC4 bit(4)
|
||||
#define TSYR_SYNC3 bit(3)
|
||||
#define TSYR_SYNC2 bit(2)
|
||||
#define TSYR_SYNC1 bit(1)
|
||||
#define TSYR_SYNC0 bit(0)
|
||||
|
||||
#endif /* H8S2357_TPU_H */
|
||||
Loading…
Reference in New Issue