update html files from doc/UrJTAG.txt

git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@1489 b68d4a1b-bc3d-0410-92ed-d4ac073336b7
master
Arnim Läuger 16 years ago
parent 3cadb23fce
commit 1a2aefbc3b

@ -4,7 +4,7 @@
<book lang="en">
<bookinfo>
<title>Universal JTAG library, server and tools</title>
<date>2009-02-27</date>
<date>2009-04-08</date>
<author>
<firstname>Kolja</firstname>
<othername>Waschk</othername>
@ -12,7 +12,7 @@
</author>
<authorinitials>KW(</authorinitials>
<revhistory><revision><revnumber>1445</revnumber><date>2009-02-27</date><authorinitials>KW(</authorinitials></revision></revhistory>
<revhistory><revision><revnumber>1482</revnumber><date>2009-04-08</date><authorinitials>KW(</authorinitials></revision></revhistory>
</bookinfo>
<chapter id="_copyright">
@ -104,8 +104,8 @@ that. Please also send proven working files back to this project.</simpara>
<simpara>Starting with post-0.7 releases, UrJTAG contains a BSDL subsystem that
retrieves the descriptions for chips in the chain from BSDL files on the
fly. Be aware that this feature is currently experimental and may not work
with every BSDL file yet.</simpara>
fly. "bsdl2jtag" is in fact a wrapper that uses the BSDL subsystem to
convert the BSDL file.</simpara>
</section>
<section id="_svf_files">
@ -308,7 +308,7 @@ Amontec JTAGkey-Tiny (supported as cable "JTAGkey")
</listitem>
<listitem>
<simpara>
TinCanTools Flyswatter
KrisTech UsbScarab2 ARM JTAG <ulink url="http://www.kristech.eu/">http://www.kristech.eu/</ulink>
</simpara>
</listitem>
<listitem>
@ -333,12 +333,27 @@ Other FT2232-based USB JTAG cables (experimental)
</listitem>
<listitem>
<simpara>
TinCanTools Flyswatter
</simpara>
</listitem>
<listitem>
<simpara>
Turtelizer 2 (experimental) <ulink url="http://www.ethernut.de/en/hardware/turtelizer/">http://www.ethernut.de/en/hardware/turtelizer/</ulink>
</simpara>
</listitem>
<listitem>
<simpara>
USB to JTAG Interface (experimental) <ulink url="http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html">http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html</ulink>
USB to JTAG Interface (experimental)
</simpara>
</listitem>
<listitem>
<simpara>
<ulink url="http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html">http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html</ulink>
</simpara>
</listitem>
<listitem>
<simpara>
Black gnICE <ulink url="http://docs.blackfin.uclinux.org/doku.php?id=hw:jtag:gnice">http://docs.blackfin.uclinux.org/doku.php?id=hw:jtag:gnice</ulink>
</simpara>
</listitem>
<listitem>
@ -383,11 +398,21 @@ Altera EP1C20F400
</listitem>
<listitem>
<simpara>
Altera MAX7000 (w/ BSDL)
</simpara>
</listitem>
<listitem>
<simpara>
Altera EPM7128AETC100
</simpara>
</listitem>
<listitem>
<simpara>
Altera Cyclone I &amp; II (w/ BSDL)
</simpara>
</listitem>
<listitem>
<simpara>
Analog Devices Sharc-21065L
</simpara>
</listitem>
@ -521,6 +546,21 @@ Xilinx XCR3128XL-VQ100
Xilinx XCR3256XL-FT256
</simpara>
</listitem>
<listitem>
<simpara>
Xilinx Spartan-IIE
</simpara>
</listitem>
<listitem>
<simpara>
Xilinx Spartan-3/E
</simpara>
</listitem>
<listitem>
<simpara>
Xilinx Spartan-3AN
</simpara>
</listitem>
</itemizedlist>
</section>
<section id="_flash_chips">
@ -554,6 +594,18 @@ AMD Am29xx040B (Am29F040B, Am29LV040B)
</simpara>
</listitem>
</itemizedlist>
<simpara>UrJTAG uses the multi-byte write mode if supported by the particular flash
device. The flash code will automatically switch to this algorithm if the
Device Geometry Definition reports that more than one memory location can be
written in a single step (refer to CFI details shown by <emphasis>detectflash</emphasis>). Since
multiple locations are written in a burst-like manner with only one polling
sequence afterwards, the overall flashing performance increases by factor of
5-17.</simpara>
<simpara>In case you encounter any issues with the multi-byte write mode, run configure
with the <emphasis>&#8212;disable-flash-multi-byte</emphasis> option and re-compile to disable this
algorithm.</simpara>
</section>
</section>
<section id="_compilation_and_installation">
@ -632,7 +684,7 @@ There is a libusb-win32 variant that can be used in a Cygwin environment:</simpa
</listitem>
</itemizedlist>
<simpara>For specific notes regarding the use of these libraries in a Cygwin
environmen, see below.</simpara>
environment, see below.</simpara>
</section>
<section id="_installing_from_source_tar_gz">
@ -1382,6 +1434,13 @@ located there.</simpara>
writing a new bus driver that utilizes a debug module to upload specific code
to access the bus is inevitable.</simpara>
</section>
<section id="_bus">
<title>bus</title>
<simpara>It's possible to initialize more than one bus for part(s) within a chain. The
"bus" command allows to select the active bus for readmem, flashmem,
etc. operation.</simpara>
</section>
</section>
<section id="_part_definition_commands">

@ -568,8 +568,8 @@ that. Please also send proven working files back to this project.</P
><P
>Starting with post-0.7 releases, UrJTAG contains a BSDL subsystem that
retrieves the descriptions for chips in the chain from BSDL files on the
fly. Be aware that this feature is currently experimental and may not work
with every BSDL file yet.</P
fly. "bsdl2jtag" is in fact a wrapper that uses the BSDL subsystem to
convert the BSDL file.</P
></DIV
><DIV
CLASS="section"
@ -906,7 +906,11 @@ CLASS="emphasis"
></LI
><LI
><P
>&#13;TinCanTools Flyswatter
>&#13;KrisTech UsbScarab2 ARM JTAG <A
HREF="http://www.kristech.eu/"
TARGET="_top"
>http://www.kristech.eu/</A
>
</P
></LI
><LI
@ -935,6 +939,11 @@ TARGET="_top"
></LI
><LI
><P
>&#13;TinCanTools Flyswatter
</P
></LI
><LI
><P
>&#13;Turtelizer 2 (experimental) <A
HREF="http://www.ethernut.de/en/hardware/turtelizer/"
TARGET="_top"
@ -944,7 +953,12 @@ TARGET="_top"
></LI
><LI
><P
>&#13;USB to JTAG Interface (experimental) <A
>&#13;USB to JTAG Interface (experimental)
</P
></LI
><LI
><P
>&#13;<A
HREF="http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html"
TARGET="_top"
>http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html</A
@ -953,6 +967,15 @@ TARGET="_top"
></LI
><LI
><P
>&#13;Black gnICE <A
HREF="http://docs.blackfin.uclinux.org/doku.php?id=hw:jtag:gnice"
TARGET="_top"
>http://docs.blackfin.uclinux.org/doku.php?id=hw:jtag:gnice</A
>
</P
></LI
><LI
><P
>&#13;Xverve Signalyzer Tool (experimental)
</P
></LI
@ -1007,11 +1030,21 @@ least the following are supported:</P
></LI
><LI
><P
>&#13;Altera MAX7000 (w/ BSDL)
</P
></LI
><LI
><P
>&#13;Altera EPM7128AETC100
</P
></LI
><LI
><P
>&#13;Altera Cyclone I &#38; II (w/ BSDL)
</P
></LI
><LI
><P
>&#13;Analog Devices Sharc-21065L
</P
></LI
@ -1145,6 +1178,21 @@ least the following are supported:</P
>&#13;Xilinx XCR3256XL-FT256
</P
></LI
><LI
><P
>&#13;Xilinx Spartan-IIE
</P
></LI
><LI
><P
>&#13;Xilinx Spartan-3/E
</P
></LI
><LI
><P
>&#13;Xilinx Spartan-3AN
</P
></LI
></UL
></DIV
><DIV
@ -1211,6 +1259,30 @@ be untested combinations of chip type, bus width, &#8230;</P
</P
></LI
></UL
><P
>UrJTAG uses the multi-byte write mode if supported by the particular flash
device. The flash code will automatically switch to this algorithm if the
Device Geometry Definition reports that more than one memory location can be
written in a single step (refer to CFI details shown by <SPAN
CLASS="emphasis"
><I
CLASS="emphasis"
>detectflash</I
></SPAN
>). Since
multiple locations are written in a burst-like manner with only one polling
sequence afterwards, the overall flashing performance increases by factor of
5-17.</P
><P
>In case you encounter any issues with the multi-byte write mode, run configure
with the <SPAN
CLASS="emphasis"
><I
CLASS="emphasis"
>&#8212;disable-flash-multi-byte</I
></SPAN
> option and re-compile to disable this
algorithm.</P
></DIV
></DIV
><DIV
@ -1326,7 +1398,7 @@ TARGET="_top"
></UL
><P
>For specific notes regarding the use of these libraries in a Cygwin
environmen, see below.</P
environment, see below.</P
></DIV
><DIV
CLASS="section"
@ -1738,7 +1810,7 @@ CLASS="informaltable"
><P
></P
><A
NAME="AEN371"
NAME="AEN393"
></A
><TABLE
BORDER="0"
@ -2637,6 +2709,19 @@ located there.</P
writing a new bus driver that utilizes a debug module to upload specific code
to access the bus is inevitable.</P
></DIV
><DIV
CLASS="section"
><HR><H4
CLASS="section"
><A
NAME="_bus"
>3.2.3.5. bus</A
></H4
><P
>It's possible to initialize more than one bus for part(s) within a chain. The
"bus" command allows to select the active bus for readmem, flashmem,
etc. operation.</P
></DIV
></DIV
><DIV
CLASS="section"
@ -2656,7 +2741,7 @@ CLASS="informaltable"
><P
></P
><A
NAME="AEN628"
NAME="AEN653"
></A
><TABLE
BORDER="0"
@ -2765,7 +2850,7 @@ CLASS="informaltable"
><P
></P
><A
NAME="AEN660"
NAME="AEN685"
></A
><TABLE
BORDER="0"
@ -2932,7 +3017,7 @@ CLASS="informaltable"
><P
></P
><A
NAME="AEN710"
NAME="AEN735"
></A
><TABLE
BORDER="0"
@ -3185,7 +3270,7 @@ CELLPADDING="5"
><DIV
CLASS="sidebar"
><A
NAME="AEN776"
NAME="AEN801"
></A
><P
><B
@ -3576,7 +3661,7 @@ CLASS="informaltable"
><P
></P
><A
NAME="AEN867"
NAME="AEN892"
></A
><TABLE
BORDER="0"

@ -184,7 +184,7 @@ TARGET="_top"
></UL
><P
>For specific notes regarding the use of these libraries in a Cygwin
environmen, see below.</P
environment, see below.</P
></DIV
><DIV
CLASS="section"

@ -185,8 +185,8 @@ that. Please also send proven working files back to this project.</P
><P
>Starting with post-0.7 releases, UrJTAG contains a BSDL subsystem that
retrieves the descriptions for chips in the chain from BSDL files on the
fly. Be aware that this feature is currently experimental and may not work
with every BSDL file yet.</P
fly. "bsdl2jtag" is in fact a wrapper that uses the BSDL subsystem to
convert the BSDL file.</P
></DIV
><DIV
CLASS="section"

@ -99,7 +99,7 @@ CLASS="informaltable"
><P
></P
><A
NAME="AEN867"
NAME="AEN892"
></A
><TABLE
BORDER="0"

@ -95,7 +95,7 @@ CLASS="informaltable"
><P
></P
><A
NAME="AEN371"
NAME="AEN393"
></A
><TABLE
BORDER="0"
@ -994,6 +994,19 @@ located there.</P
writing a new bus driver that utilizes a debug module to upload specific code
to access the bus is inevitable.</P
></DIV
><DIV
CLASS="section"
><H3
CLASS="section"
><A
NAME="_bus"
>3.2.3.5. bus</A
></H3
><P
>It's possible to initialize more than one bus for part(s) within a chain. The
"bus" command allows to select the active bus for readmem, flashmem,
etc. operation.</P
></DIV
></DIV
><DIV
CLASS="section"
@ -1013,7 +1026,7 @@ CLASS="informaltable"
><P
></P
><A
NAME="AEN628"
NAME="AEN653"
></A
><TABLE
BORDER="0"
@ -1122,7 +1135,7 @@ CLASS="informaltable"
><P
></P
><A
NAME="AEN660"
NAME="AEN685"
></A
><TABLE
BORDER="0"
@ -1289,7 +1302,7 @@ CLASS="informaltable"
><P
></P
><A
NAME="AEN710"
NAME="AEN735"
></A
><TABLE
BORDER="0"
@ -1542,7 +1555,7 @@ CELLPADDING="5"
><DIV
CLASS="sidebar"
><A
NAME="AEN776"
NAME="AEN801"
></A
><P
><B

@ -219,7 +219,11 @@ CLASS="emphasis"
></LI
><LI
><P
>&#13;TinCanTools Flyswatter
>&#13;KrisTech UsbScarab2 ARM JTAG <A
HREF="http://www.kristech.eu/"
TARGET="_top"
>http://www.kristech.eu/</A
>
</P
></LI
><LI
@ -248,6 +252,11 @@ TARGET="_top"
></LI
><LI
><P
>&#13;TinCanTools Flyswatter
</P
></LI
><LI
><P
>&#13;Turtelizer 2 (experimental) <A
HREF="http://www.ethernut.de/en/hardware/turtelizer/"
TARGET="_top"
@ -257,7 +266,12 @@ TARGET="_top"
></LI
><LI
><P
>&#13;USB to JTAG Interface (experimental) <A
>&#13;USB to JTAG Interface (experimental)
</P
></LI
><LI
><P
>&#13;<A
HREF="http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html"
TARGET="_top"
>http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html</A
@ -266,6 +280,15 @@ TARGET="_top"
></LI
><LI
><P
>&#13;Black gnICE <A
HREF="http://docs.blackfin.uclinux.org/doku.php?id=hw:jtag:gnice"
TARGET="_top"
>http://docs.blackfin.uclinux.org/doku.php?id=hw:jtag:gnice</A
>
</P
></LI
><LI
><P
>&#13;Xverve Signalyzer Tool (experimental)
</P
></LI
@ -320,11 +343,21 @@ least the following are supported:</P
></LI
><LI
><P
>&#13;Altera MAX7000 (w/ BSDL)
</P
></LI
><LI
><P
>&#13;Altera EPM7128AETC100
</P
></LI
><LI
><P
>&#13;Altera Cyclone I &#38; II (w/ BSDL)
</P
></LI
><LI
><P
>&#13;Analog Devices Sharc-21065L
</P
></LI
@ -458,6 +491,21 @@ least the following are supported:</P
>&#13;Xilinx XCR3256XL-FT256
</P
></LI
><LI
><P
>&#13;Xilinx Spartan-IIE
</P
></LI
><LI
><P
>&#13;Xilinx Spartan-3/E
</P
></LI
><LI
><P
>&#13;Xilinx Spartan-3AN
</P
></LI
></UL
></DIV
><DIV
@ -524,6 +572,30 @@ be untested combinations of chip type, bus width, &#8230;</P
</P
></LI
></UL
><P
>UrJTAG uses the multi-byte write mode if supported by the particular flash
device. The flash code will automatically switch to this algorithm if the
Device Geometry Definition reports that more than one memory location can be
written in a single step (refer to CFI details shown by <SPAN
CLASS="emphasis"
><I
CLASS="emphasis"
>detectflash</I
></SPAN
>). Since
multiple locations are written in a burst-like manner with only one polling
sequence afterwards, the overall flashing performance increases by factor of
5-17.</P
><P
>In case you encounter any issues with the multi-byte write mode, run configure
with the <SPAN
CLASS="emphasis"
><I
CLASS="emphasis"
>&#8212;disable-flash-multi-byte</I
></SPAN
> option and re-compile to disable this
algorithm.</P
></DIV
></DIV
><DIV

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