add xilinx xc18v02pc44 support by Steve Tell
git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@1909 b68d4a1b-bc3d-0410-92ed-d4ac073336b7master
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#
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# $Id: STEPPINGS,v 1.1 2003/02/14 11:14:56 telka Exp $
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#
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# Copyright (C) 2003 Tower Technologies s.r.l.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; either version 2
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# of the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
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# 02111-1307, USA.
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#
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# Written by Alessandro Zummo <azummo@towertech.it>, 2003.
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# DJF:w
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# bits 31-28 of the Device Identification Register
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0000 xc18v02pc44 0
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signal CLK
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signal D2
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signal Gnd_1
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signal D0
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signal Vcc_2
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signal Vcco_4
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signal Vpp
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signal TDO
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signal D1
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signal Gnd_4
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signal D3
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signal Vcco_3
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signal D5
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signal CEO
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signal D7
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signal Gnd_3
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signal Vcc_1
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signal Vcco_2
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signal CE
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signal D6
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signal Reset_OE
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signal CF
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signal D4
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signal Vcco_1
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signal TCK
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signal Gnd_2
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signal TMS
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signal TDI
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instruction length 8
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register DIR 32
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register USERCODE 32
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register BSR 25
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register BYPASS 1
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register USERCODEV 32
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register ADDRESS 16
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register DATA3 3
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register DATA1 2097152
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register DATA0 4096
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register ISPENABLE 6
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instruction CONFIG 11101110 BYPASS
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instruction NORMRST 11110000 BYPASS
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instruction FBLANK6 11100100 USERCODEV
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instruction FBLANK3 11100001 DATA3
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instruction FBLANK0 11100101 DATA1
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instruction FDATA3 11110011 DATA3
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instruction FDATA0 11101101 DATA0
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instruction SERASE 00001010 ADDRESS
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instruction FERASE 11101100 ADDRESS
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instruction FVFY6 11100110 USERCODEV
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instruction FVFY3 11100010 DATA3
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instruction FVFY1 11111000 DATA1
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instruction FVFY0 11101111 DATA0
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instruction FADDR 11101011 ADDRESS
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instruction FPGM 11101010 BYPASS
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instruction ISPENC 11101001 ISPENABLE
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instruction ISPEN 11101000 ISPENABLE
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instruction CLAMP 11111010 BYPASS
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instruction HIGHZ 11111100 BYPASS
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instruction USERCODE 11111101 DIR
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instruction IDCODE 11111110 DIR
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instruction EXTEST 00000000 BSR
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instruction SAMPLE/PRELOAD 00000001 BSR
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instruction BYPASS 11111111 BYPASS
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bit 0 I ? CLK
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bit 1 C 0 *
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bit 2 O ? D2 1 0 Z
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bit 3 C 0 *
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bit 4 O ? D0 3 0 Z
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bit 5 C 0 *
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bit 6 O ? D1 5 0 Z
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bit 7 C 0 *
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bit 8 O ? D3 7 0 Z
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bit 9 C 0 *
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bit 10 O ? D5 9 0 Z
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bit 11 C 0 *
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bit 12 O ? CEO 11 0 Z
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bit 13 C 0 *
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bit 14 O ? D7 13 0 Z
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bit 15 I ? CE
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bit 16 C 0 *
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bit 17 O ? D6 16 0 Z
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bit 18 C 0 *
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bit 19 O ? Reset_OE 18 0 Z
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bit 20 I ? Reset_OE
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bit 21 C 0 *
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bit 22 O ? CF 21 0 Z
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bit 23 C 0 *
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bit 24 O ? D4 23 0 Z
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