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2003-04-26 Marcel Telka <marcel@telka.sk>

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* arm/pxa2x0/ac97.h: Changed comments for PXA255. Replaced PXA2X0_NOPXA26X with
		PXA2X0_NOPXA255 and PXA2X0_NOPXA260.
	* arm/pxa2x0/cm.h: Ditto.
	* arm/pxa2x0/dma.h: Ditto.
	* arm/pxa2x0/gpio.h: Ditto.
	* arm/pxa2x0/i2c.h: Ditto.
	* arm/pxa2x0/i2s.h: Ditto.
	* arm/pxa2x0/ic.h: Ditto.
	* arm/pxa2x0/icp.h: Ditto.
	* arm/pxa2x0/lcd.h: Ditto.
	* arm/pxa2x0/mc.h: Ditto.
	* arm/pxa2x0/mmc.h: Ditto.
	* arm/pxa2x0/ost.h: Ditto.
	* arm/pxa2x0/pmrc.h: Ditto.
	* arm/pxa2x0/pwm.h: Ditto.
	* arm/pxa2x0/rtc.h: Ditto.
	* arm/pxa2x0/ssp.h: Ditto.
	* arm/pxa2x0/uart.h: Ditto.
	* arm/pxa2x0/udc.h: Ditto.
	* arm/pxa2x0/cm.h (CCCR_M_4): New macro for PXA255 and above.
	* arm/pxa2x0/udc.h (UDCCFR): New register for PXA255 and above.


git-svn-id: https://urjtag.svn.sourceforge.net/svnroot/urjtag/trunk@422 b68d4a1b-bc3d-0410-92ed-d4ac073336b7
master
Marcel Telka 22 years ago
parent d5c26f5f9c
commit a32d98b376
20 changed files with 631 additions and 348 deletions
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24
include/ChangeLog
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@ -1,3 +1,27 @@
2003-04-26 Marcel Telka <marcel@telka.sk>
* arm/pxa2x0/ac97.h: Changed comments for PXA255. Replaced PXA2X0_NOPXA26X with
PXA2X0_NOPXA255 and PXA2X0_NOPXA260.
* arm/pxa2x0/cm.h: Ditto.
* arm/pxa2x0/dma.h: Ditto.
* arm/pxa2x0/gpio.h: Ditto.
* arm/pxa2x0/i2c.h: Ditto.
* arm/pxa2x0/i2s.h: Ditto.
* arm/pxa2x0/ic.h: Ditto.
* arm/pxa2x0/icp.h: Ditto.
* arm/pxa2x0/lcd.h: Ditto.
* arm/pxa2x0/mc.h: Ditto.
* arm/pxa2x0/mmc.h: Ditto.
* arm/pxa2x0/ost.h: Ditto.
* arm/pxa2x0/pmrc.h: Ditto.
* arm/pxa2x0/pwm.h: Ditto.
* arm/pxa2x0/rtc.h: Ditto.
* arm/pxa2x0/ssp.h: Ditto.
* arm/pxa2x0/uart.h: Ditto.
* arm/pxa2x0/udc.h: Ditto.
* arm/pxa2x0/cm.h (CCCR_M_4): New macro for PXA255 and above.
* arm/pxa2x0/udc.h (UDCCFR): New register for PXA255 and above.
2003-04-14 Marcel Telka <marcel@telka.sk>
* arm/arm.h: Added System Control Coprocessor Control Register bits.

10
include/NEWS
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@ -1,6 +1,14 @@
$Id$
* Added System Control Coprocessor Register 1 (Control Register) bits.
* Changes in PXA2x0 support:
- added support for Intel PXA255 processor
- replaced PXA2X0_NOPXA26X conditional directive with PXA2X0_NOPXA255
and PXA2X0_NOPXA260 directives to remove support for PXA255
and above (PXA2X0_NOPXA255) or PXA260 and above (PXA2X0_NOPXA260)
processor features
- added CCCR_M_4 multiplier for PXA255 and above
- added new register UDCCFR for PXA255 and above
* Added ARM System Control Coprocessor Register 1 (Control Register) bits.
include-0.2.3 (2003-04-04):

50
include/arm/pxa2x0/ac97.h
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@ -1,8 +1,8 @@
/*
* $Id$
*
* XScale PXA26x/PXA250/PXA210 AC97 Registers
* Copyright (C) 2002 ETC s.r.o.
* XScale PXA26x/PXA255/PXA250/PXA210 AC97 Registers
* Copyright (C) 2002, 2003 ETC s.r.o.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -28,13 +28,15 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
*
* Documentation:
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
* Developer's Manual", February 2002, Order Number: 278522-001
* [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
* October 2002, Order Number: 278638-001
* March 2003, Order Number: 278638-002
* [3] Intel Corporation, "Intel PXA255 Processor Developer's Manual"
* March 2003, Order Number: 278693-001
*
*/
@ -47,6 +49,14 @@
#include <stdint.h>
#endif
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255)
#define PXA2X0_NOPXA255
#endif
#if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260)
#define PXA2X0_NOPXA260
#endif
/* AC97 Registers */
#define AC97_BASE 0x40500000
@ -126,19 +136,19 @@ typedef volatile struct AC97_registers {
#define MISR_OFFSET 0x118
#define MODR_OFFSET 0x140
/* POCR bits - see Table 13-50 in [1], Table 13-10 in [2] */
/* POCR bits - see Table 13-50 in [1], Table 13-10 in [2], Table 13-9 in [3] */
#define POCR_FEIE bit(3)
/* PICR bits - see Table 13-51 in [1], Table 13-11 in [2] */
/* PICR bits - see Table 13-51 in [1], Table 13-11 in [2], Table 13-10 in [3] */
#define PICR_FEIE bit(3)
/* MCCR bits - see Table 13-56 in [1], Table 13-16 in [2] */
/* MCCR bits - see Table 13-56 in [1], Table 13-16 in [2], Table 13-15 in [3] */
#define MCCR_FEIE bit(3)
/* GCR bits - see Table 13-48 in [1], Table 13-8 in [2] */
/* GCR bits - see Table 13-48 in [1], Table 13-8 in [2], Table 13-7 in [3] */
#define GCR_CDONE_IE bit(19)
#define GCR_SDONE_IE bit(18)
@ -151,19 +161,19 @@ typedef volatile struct AC97_registers {
#define GCR_COLD_RST bit(1)
#define GCR_GIE bit(0)
/* POSR bits - see Table 13-52 in [1], Table 13-12 in [2] */
/* POSR bits - see Table 13-52 in [1], Table 13-12 in [2], Table 13-11 in [3] */
#define POSR_FIFOE bit(4)
/* PISR bits - see Table 13-53 in [1], Table 13-13 in [2] */
/* PISR bits - see Table 13-53 in [1], Table 13-13 in [2], Table 13-12 in [3] */
#define PISR_FIFOE bit(4)
/* MCSR bits - see Table 13-57 in [1], Table 13-17 in [2] */
/* MCSR bits - see Table 13-57 in [1], Table 13-17 in [2], Table 13-16 in [3] */
#define MCSR_FIFOE bit(4)
/* GSR bits - see Table 13-49 in [1], Table 13-9 in [2] */
/* GSR bits - see Table 13-49 in [1], Table 13-9 in [2], Table 13-8 in [3] */
#define GSR_CDONE bit(19)
#define GSR_SDONE bit(18)
@ -182,11 +192,11 @@ typedef volatile struct AC97_registers {
#define GSR_MIINT bit(1)
#define GSR_GSCI bit(0)
/* CAR bits - see Table 13-54 in [1], Table 13-14 in [2] */
/* CAR bits - see Table 13-54 in [1], Table 13-14 in [2], Table 13-13 in [3] */
#define CAR_CAIP bit(0)
/* PCDR bits - see Table 13-55 in [1], Table 13-15 in [2] */
/* PCDR bits - see Table 13-55 in [1], Table 13-15 in [2], Table 13-14 in [3] */
#define PCDR_PCM_RDATA_MASK bits(31,16)
#define PCDR_PCM_RDATA(x) bits_val(31,16,x)
@ -195,29 +205,29 @@ typedef volatile struct AC97_registers {
#define PCDR_PCM_LDATA(x) bits_val(15,0,x)
#define get_PCDR_PCM_LDATA(x) bits_get(15,0,x)
/* MCDR bits - see Table 13-58 in [1], Table 13-18 in [2] */
/* MCDR bits - see Table 13-58 in [1], Table 13-18 in [2], Table 13-17 in [3] */
#define MCDR_MIC_IN_DAT_MASK bits(15,0)
#define MCDR_MIC_IN_DAT(x) bits_val(15,0,x)
#define get_MCDR_MIC_IN_DAT(x) bits_get(15,0,x)
/* MOCR bits - see Table 13-59 in [1], Table 13-19 in [2] */
/* MOCR bits - see Table 13-59 in [1], Table 13-19 in [2], Table 13-18 in [3] */
#define MOCR_FEIE bit(3)
/* MICR bits - see Table 13-60 in [1], Table 13-20 in [2] */
/* MICR bits - see Table 13-60 in [1], Table 13-20 in [2], Table 13-19 in [3] */
#define MICR_FEIE bit(3)
/* MOSR bits - see Table 13-61 in [1], Table 13-21 in [2] */
/* MOSR bits - see Table 13-61 in [1], Table 13-21 in [2], Table 13-20 in [3] */
#define MOSR_FIFOE bit(4)
/* MISR bits - see Table 16-62 in [1], Table 13-22 in [2] */
/* MISR bits - see Table 13-62 in [1], Table 13-22 in [2], Table 13-21 in [3] */
#define MISR_FIFOE bit(4)
/* MODR bits - see Table 16-63 in [1], Table 13-23 in [2] */
/* MODR bits - see Table 13-63 in [1], Table 13-23 in [2], Table 13-22 in [3] */
#define MODR_MODEM_DAT_MASK bits(15,0)
#define MODR_MODEM_DAT(x) bits_val(15,0,x)

37
include/arm/pxa2x0/cm.h
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@ -1,8 +1,8 @@
/*
* $Id$
*
* XScale PXA26x/PXA250/PXA210 Clocks Manager Registers
* Copyright (C) 2002 ETC s.r.o.
* XScale PXA26x/PXA255/PXA250/PXA210 Clocks Manager Registers
* Copyright (C) 2002, 2003 ETC s.r.o.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -28,13 +28,15 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
*
* Documentation:
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
* Developer's Manual", February 2002, Order Number: 278522-001
* [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
* October 2002, Order Number: 278638-001
* March 2003, Order Number: 278638-002
* [3] Intel Corporation, "Intel PXA255 Processor Developer's Manual"
* March 2003, Order Number: 278693-001
*
*/
@ -47,8 +49,12 @@
#include <stdint.h>
#endif
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA26X)
#define PXA2X0_NOPXA26X
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255)
#define PXA2X0_NOPXA255
#endif
#if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260)
#define PXA2X0_NOPXA260
#endif
/* Clocks Manager Registers */
@ -75,7 +81,7 @@ typedef volatile struct CM_registers {
#define CKEN_OFFSET 0x04
#define OSCC_OFFSET 0x08
/* CCCR bits - see Table 3-20 in [1], Table 3-20 in [2] */
/* CCCR bits - see Table 3-20 in [1], Table 3-20 in [2], Table 3-20 in [3] */
#define CCCR_N_MASK bits(9,7)
#define CCCR_N(x) bits_val(9,7,x)
@ -94,6 +100,9 @@ typedef volatile struct CM_registers {
#define CCCR_M_1 CCCR_M(0x1)
#define CCCR_M_2 CCCR_M(0x2)
#if !defined(PXA2X0_NOPXA255)
#define CCCR_M_4 CCCR_M(0x3)
#endif /* PXA255 and above only */
#define CCCR_L_27 CCCR_L(0x01)
#define CCCR_L_32 CCCR_L(0x02)
@ -101,30 +110,32 @@ typedef volatile struct CM_registers {
#define CCCR_L_40 CCCR_L(0x04)
#define CCCR_L_45 CCCR_L(0x05)
/* CKEN bits - see Table 3-21 in [1], Table 3-21 in [2] */
/* CKEN bits - see Table 3-21 in [1], Table 3-21 in [2], Table 3-21 in [3] */
#define CKEN_CKEN16 bit(16)
#define CKEN_CKEN14 bit(14)
#define CKEN_CKEN13 bit(13)
#define CKEN_CKEN12 bit(12)
#define CKEN_CKEN11 bit(11)
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA260)
#define CKEN_CKEN10 bit(10)
#endif /* PXA260 and above only */
#if !defined(PXA2X0_NOPXA255)
#define CKEN_CKEN9 bit(9)
#endif /* PXA26x only */
#endif /* PXA255 and above only */
#define CKEN_CKEN8 bit(8)
#define CKEN_CKEN7 bit(7)
#define CKEN_CKEN6 bit(6)
#define CKEN_CKEN5 bit(5)
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define CKEN_CKEN4 bit(4)
#endif /* PXA26x only */
#endif /* PXA255 and above only */
#define CKEN_CKEN3 bit(3)
#define CKEN_CKEN2 bit(2)
#define CKEN_CKEN1 bit(1)
#define CKEN_CKEN0 bit(0)
/* OSCC bits - see Table 3-22 in [1], Table 3-22 in [2] */
/* OSCC bits - see Table 3-22 in [1], Table 3-22 in [2], Table 3-22 in [3] */
#define OSCC_OON bit(1)
#define OSCC_OOK bit(0)

64
include/arm/pxa2x0/dma.h
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@ -1,8 +1,8 @@
/*
* $Id$
*
* XScale PXA26x/PXA250/PXA210 DMA Controller Registers
* Copyright (C) 2002 ETC s.r.o.
* XScale PXA26x/PXA255/PXA250/PXA210 DMA Controller Registers
* Copyright (C) 2002, 2003 ETC s.r.o.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -28,13 +28,15 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
*
* Documentation:
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
* Developer's Manual", February 2002, Order Number: 278522-001
* [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
* October 2002, Order Number: 278638-001
* March 2003, Order Number: 278638-002
* [3] Intel Corporation, "Intel PXA255 Processor Developer's Manual"
* March 2003, Order Number: 278693-001
*
*/
@ -47,8 +49,12 @@
#include <stdint.h>
#endif
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA26X)
#define PXA2X0_NOPXA26X
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255)
#define PXA2X0_NOPXA255
#endif
#if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260)
#define PXA2X0_NOPXA260
#endif
/* DMA Controller Registers */
@ -85,7 +91,7 @@ typedef volatile struct DMA_registers {
#define DTADR(i) DMA_pointer->dar[i].dtadr
#define DCMD(i) DMA_pointer->dar[i].dcmd
/* DRCMR symbolic names - see Table 5-13 in [1], Table 5-13 in [2] */
/* DRCMR symbolic names - see Table 5-13 in [1], Table 5-13 in [2], Table 5-13 in [3] */
#define DRCMR_DREQ0 DRCMR(0)
#define DRCMR_DREQ1 DRCMR(1)
@ -102,34 +108,34 @@ typedef volatile struct DMA_registers {
#define DRCMR_AC97_AUDIO_TX DRCMR(12)
#define DRCMR_SSP_RX DRCMR(13)
#define DRCMR_SSP_TX DRCMR(14)
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define DRCMR_NSSP_RX DRCMR(15)
#define DRCMR_NSSP_TX DRCMR(16)
#endif /* PXA26x only */
#endif /* PXA255 and above only */
#define DRCMR_FICP_RX DRCMR(17)
#define DRCMR_FICP_TX DRCMR(18)
#define DRCMR_STUART_RX DRCMR(19)
#define DRCMR_STUART_TX DRCMR(20)
#define DRCMR_MMC_RX DRCMR(21)
#define DRCMR_MMC_TX DRCMR(22)
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA260)
#define DRCMR_ASSP_RX DRCMR(23)
#define DRCMR_ASSP_TX DRCMR(24)
#endif /* PXA26x only */
#endif /* PXA260 and above only */
#define DRCMR_USB_EP1 DRCMR(25)
#define DRCMR_USB_EP2 DRCMR(26)
#define DRCMR_USB_EP3 DRCMR(27)
#define DRCMR_USB_EP4 DRCMR(28)
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define DRCMR_HWUART_RX DRCMR(29)
#endif /* PXA26x only */
#endif /* PXA255 and above only */
#define DRCMR_USB_EP6 DRCMR(30)
#define DRCMR_USB_EP7 DRCMR(31)
#define DRCMR_USB_EP8 DRCMR(32)
#define DRCMR_USB_EP9 DRCMR(33)
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define DRCMR_HWUART_TX DRCMR(34)
#endif /* PXA26x only */
#endif /* PXA255 and above only */
#define DRCMR_USB_EP11 DRCMR(35)
#define DRCMR_USB_EP12 DRCMR(36)
#define DRCMR_USB_EP13 DRCMR(37)
@ -144,7 +150,7 @@ typedef volatile struct DMA_registers {
#define DTADR_OFFSET(i) (0x208 + ((i) << 4))
#define DCMD_OFFSET(i) (0x20C + ((i) << 4))
/* DRCMR symbolic names offsets - see Table 5-13 in [1], Table 5-13 in [2] */
/* DRCMR symbolic names offsets - see Table 5-13 in [1], Table 5-13 in [2], Table 5-13 in [3] */
#define DRCMR_DREQ0_OFFSET DRCMR_OFFSET(0)
#define DRCMR_DREQ1_OFFSET DRCMR_OFFSET(1)
@ -161,40 +167,40 @@ typedef volatile struct DMA_registers {
#define DRCMR_AC97_AUDIO_TX_OFFSET DRCMR_OFFSET(12)
#define DRCMR_SSP_RX_OFFSET DRCMR_OFFSET(13)
#define DRCMR_SSP_TX_OFFSET DRCMR_OFFSET(14)
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define DRCMR_NSSP_RX_OFFSET DRCMR_OFFSET(15)
#define DRCMR_NSSP_TX_OFFSET DRCMR_OFFSET(16)
#endif /* PXA26x only */
#endif /* PXA255 and above only */
#define DRCMR_FICP_RX_OFFSET DRCMR_OFFSET(17)
#define DRCMR_FICP_TX_OFFSET DRCMR_OFFSET(18)
#define DRCMR_STUART_RX_OFFSET DRCMR_OFFSET(19)
#define DRCMR_STUART_TX_OFFSET DRCMR_OFFSET(20)
#define DRCMR_MMC_RX_OFFSET DRCMR_OFFSET(21)
#define DRCMR_MMC_TX_OFFSET DRCMR_OFFSET(22)
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA260)
#define DRCMR_ASSP_RX_OFFSET DRCMR_OFFSET(23)
#define DRCMR_ASSP_TX_OFFSET DRCMR_OFFSET(24)
#endif /* PXA26x only */
#endif /* PXA260 and above only */
#define DRCMR_USB_EP1_OFFSET DRCMR_OFFSET(25)
#define DRCMR_USB_EP2_OFFSET DRCMR_OFFSET(26)
#define DRCMR_USB_EP3_OFFSET DRCMR_OFFSET(27)
#define DRCMR_USB_EP4_OFFSET DRCMR_OFFSET(28)
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define DRCMR_HWUART_RX_OFFSET DRCMR_OFFSET(29)
#endif /* PXA26x only */
#endif /* PXA255 and above only */
#define DRCMR_USB_EP6_OFFSET DRCMR_OFFSET(30)
#define DRCMR_USB_EP7_OFFSET DRCMR_OFFSET(31)
#define DRCMR_USB_EP8_OFFSET DRCMR_OFFSET(32)
#define DRCMR_USB_EP9_OFFSET DRCMR_OFFSET(33)
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define DRCMR_HWUART_TX_OFFSET DRCMR_OFFSET(34)
#endif /* PXA26x only */
#endif /* PXA255 and above only */
#define DRCMR_USB_EP11_OFFSET DRCMR_OFFSET(35)
#define DRCMR_USB_EP12_OFFSET DRCMR_OFFSET(36)
#define DRCMR_USB_EP13_OFFSET DRCMR_OFFSET(37)
#define DRCMR_USB_EP14_OFFSET DRCMR_OFFSET(38)
/* DCSRx bits - see Table 5-7 in [1], Table 5-7 in [2] */
/* DCSRx bits - see Table 5-7 in [1], Table 5-7 in [2], Table 5-7 in [3] */
#define DCSR_RUN bit(31)
#define DCSR_NODESCFETCH bit(30)
@ -205,7 +211,7 @@ typedef volatile struct DMA_registers {
#define DCSR_STARTINTR bit(1)
#define DCSR_BUSERRINTR bit(0)
/* DINT bits - see Table 5-6 in [1], Table 5-6 in [2] */
/* DINT bits - see Table 5-6 in [1], Table 5-6 in [2], Table 5-6 in [3] */
#define DINT_CHLINTR(x) bit(x)
#define DINT_CHLINTR0 DINT_CHLINTR(0)
@ -225,18 +231,18 @@ typedef volatile struct DMA_registers {
#define DINT_CHLINTR14 DINT_CHLINTR(14)
#define DINT_CHLINTR15 DINT_CHLINTR(15)
/* DRCMRx bits - see Table 5-8 in [1], Table 5-8 in [2] */
/* DRCMRx bits - see Table 5-8 in [1], Table 5-8 in [2], Table 5-8 in [3] */
#define DRCMR_MAPVLD bit(7)
#define DRCMR_CHLNUM_MASK bits(3,0)
#define DRCMR_CHLNUM(x) bits_val(3,0,x)
#define get_DRCMR_CHLNUM(x) bits_get(3,0,x)
/* DDADRx bits - see Table 5-9 in [1], Table 5-9 in [2] */
/* DDADRx bits - see Table 5-9 in [1], Table 5-9 in [2], Table 5-9 in [3] */
#define DDADR_STOP bit(0)
/* DCMDx bits - see Table 5-12 in [1], Table 5-12 in [2] */
/* DCMDx bits - see Table 5-12 in [1], Table 5-12 in [2], Table 5-12 in [3] */
#define DCMD_INCSRCADDR bit(31)
#define DCMD_INCTRGADDR bit(30)

60
include/arm/pxa2x0/gpio.h
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@ -1,8 +1,8 @@
/*
* $Id$
*
* XScale PXA26x/PXA250/PXA210 GPIO Registers
* Copyright (C) 2002 ETC s.r.o.
* XScale PXA26x/PXA255/PXA250/PXA210 GPIO Registers
* Copyright (C) 2002, 2003 ETC s.r.o.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -28,13 +28,15 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
*
* Documentation:
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
* Developer's Manual", February 2002, Order Number: 278522-001
* [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
* October 2002, Order Number: 278638-001
* March 2003, Order Number: 278638-002
* [3] Intel Corporation, "Intel PXA255 Processor Developer's Manual"
* March 2003, Order Number: 278693-001
*
*/
@ -47,8 +49,12 @@
#include <stdint.h>
#endif
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA26X)
#define PXA2X0_NOPXA26X
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255)
#define PXA2X0_NOPXA255
#endif
#if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260)
#define PXA2X0_NOPXA260
#endif
/* GPIO Registers */
@ -165,7 +171,7 @@ typedef volatile struct GPIO_registers {
#define GPIO0_GP12 bit(12)
#define GPIO0_GP13 bit(13)
#define GPIO0_GP14 bit(14)
#endif /* PXA250 and PXA26x only */
#endif /* PXA250 and above only */
#define GPIO0_GP15 bit(15)
#define GPIO0_GP16 bit(16)
#define GPIO0_GP17 bit(17)
@ -175,7 +181,7 @@ typedef volatile struct GPIO_registers {
#define GPIO0_GP20 bit(20)
#define GPIO0_GP21 bit(21)
#define GPIO0_GP22 bit(22)
#endif /* PXA250 and PXA26x only */
#endif /* PXA250 and above only */
#define GPIO0_GP23 bit(23)
#define GPIO0_GP24 bit(24)
#define GPIO0_GP25 bit(25)
@ -193,12 +199,12 @@ typedef volatile struct GPIO_registers {
#define GPIO1_GP36 bit(4)
#define GPIO1_GP37 bit(5)
#define GPIO1_GP38 bit(6)
#endif /* PXA250 and PXA26x only */
#endif /* PXA250 and above only */
#define GPIO1_GP39 bit(7)
#if !defined(PXA2X0_NOPXA250)
#define GPIO1_GP40 bit(8)
#define GPIO1_GP41 bit(9)
#endif /* PXA250 and PXA26x only */
#endif /* PXA250 and above only */
#define GPIO1_GP42 bit(10)
#define GPIO1_GP43 bit(11)
#define GPIO1_GP44 bit(12)
@ -238,19 +244,21 @@ typedef volatile struct GPIO_registers {
#define GPIO2_GP78 bit(14)
#define GPIO2_GP79 bit(15)
#define GPIO2_GP80 bit(16)
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define GPIO2_GP81 bit(17)
#define GPIO2_GP82 bit(18)
#define GPIO2_GP83 bit(19)
#define GPIO2_GP84 bit(20)
#endif /* PXA255 and above only */
#if !defined(PXA2X0_NOPXA260)
#define GPIO2_GP85 bit(21)
#define GPIO2_GP86 bit(22)
#define GPIO2_GP87 bit(23)
#define GPIO2_GP88 bit(24)
#define GPIO2_GP89 bit(25)
#endif /* PXA26x only */
#endif /* PXA260 and above only */
/* GAFR constants - see 4.1.3.6 in [1], 4.1.3.6 in [2] */
/* GAFR constants - see 4.1.3.6 in [1], 4.1.3.6 in [2], 4.1.3.6 in [3] */
#define ALT_FN_MASK 3
#define ALT_FN_0_IN 0
@ -262,7 +270,7 @@ typedef volatile struct GPIO_registers {
#define ALT_FN_2_OUT 2
#define ALT_FN_3_OUT 3
/* GAFR0_L bits - see Table 4-24 in [1], Table 4-24 in [2] */
/* GAFR0_L bits - see Table 4-24 in [1], Table 4-24 in [2], Table 4-24 in [3] */
#define GAFR0_L_AF0(x) ((x) & ALT_FN_MASK)
#define GAFR0_L_AF1(x) (((x) & ALT_FN_MASK) << 2)
@ -280,10 +288,10 @@ typedef volatile struct GPIO_registers {
#define GAFR0_L_AF12(x) (((x) & ALT_FN_MASK) << 24)
#define GAFR0_L_AF13(x) (((x) & ALT_FN_MASK) << 26)
#define GAFR0_L_AF14(x) (((x) & ALT_FN_MASK) << 28)
#endif /* PXA250 and PXA26x only */
#endif /* PXA250 and above only */
#define GAFR0_L_AF15(x) (((x) & ALT_FN_MASK) << 30)
/* GAFR0_U bits - see Table 4-25 in [1], Table 4-25 in [2] */
/* GAFR0_U bits - see Table 4-25 in [1], Table 4-25 in [2], Table 4-25 in [3] */
#define GAFR0_U_AF16(x) ((x) & ALT_FN_MASK)
#define GAFR0_U_AF17(x) (((x) & ALT_FN_MASK) << 2)
@ -293,7 +301,7 @@ typedef volatile struct GPIO_registers {
#define GAFR0_U_AF20(x) (((x) & ALT_FN_MASK) << 8)
#define GAFR0_U_AF21(x) (((x) & ALT_FN_MASK) << 10)
#define GAFR0_U_AF22(x) (((x) & ALT_FN_MASK) << 12)
#endif /* PXA250 and PXA26x only */
#endif /* PXA250 and above only */
#define GAFR0_U_AF23(x) (((x) & ALT_FN_MASK) << 14)
#define GAFR0_U_AF24(x) (((x) & ALT_FN_MASK) << 16)
#define GAFR0_U_AF25(x) (((x) & ALT_FN_MASK) << 18)
@ -304,7 +312,7 @@ typedef volatile struct GPIO_registers {
#define GAFR0_U_AF30(x) (((x) & ALT_FN_MASK) << 28)
#define GAFR0_U_AF31(x) (((x) & ALT_FN_MASK) << 30)
/* GAFR1_L bits - see Table 4-26 in [1], Table 4-26 in [2] */
/* GAFR1_L bits - see Table 4-26 in [1], Table 4-26 in [2], Table 4-26 in [3] */
#define GAFR1_L_AF32(x) ((x) & ALT_FN_MASK)
#define GAFR1_L_AF33(x) (((x) & ALT_FN_MASK) << 2)
@ -314,12 +322,12 @@ typedef volatile struct GPIO_registers {
#define GAFR1_L_AF36(x) (((x) & ALT_FN_MASK) << 8)
#define GAFR1_L_AF37(x) (((x) & ALT_FN_MASK) << 10)
#define GAFR1_L_AF38(x) (((x) & ALT_FN_MASK) << 12)
#endif /* PXA250 and PXA26x only */
#endif /* PXA250 and above only */
#define GAFR1_L_AF39(x) (((x) & ALT_FN_MASK) << 14)
#if !defined(PXA2X0_NOPXA250)
#define GAFR1_L_AF40(x) (((x) & ALT_FN_MASK) << 16)
#define GAFR1_L_AF41(x) (((x) & ALT_FN_MASK) << 18)
#endif /* PXA250 and PXA26x only */
#endif /* PXA250 and above only */
#define GAFR1_L_AF42(x) (((x) & ALT_FN_MASK) << 20)
#define GAFR1_L_AF43(x) (((x) & ALT_FN_MASK) << 22)
#define GAFR1_L_AF44(x) (((x) & ALT_FN_MASK) << 24)
@ -327,7 +335,7 @@ typedef volatile struct GPIO_registers {
#define GAFR1_L_AF46(x) (((x) & ALT_FN_MASK) << 28)
#define GAFR1_L_AF47(x) (((x) & ALT_FN_MASK) << 30)
/* GAFR1_U bits - see Table 4-27 in [1], Table 4-27 in [2] */
/* GAFR1_U bits - see Table 4-27 in [1], Table 4-27 in [2], Table 4-27 in [3] */
#define GAFR1_U_AF48(x) ((x) & ALT_FN_MASK)
#define GAFR1_U_AF49(x) (((x) & ALT_FN_MASK) << 2)
@ -346,7 +354,7 @@ typedef volatile struct GPIO_registers {
#define GAFR1_U_AF62(x) (((x) & ALT_FN_MASK) << 28)
#define GAFR1_U_AF63(x) (((x) & ALT_FN_MASK) << 30)
/* GAFR2_L bits - see Table 4-28 in [1], Table 4-28 in [2] */
/* GAFR2_L bits - see Table 4-28 in [1], Table 4-28 in [2], Table 4-28 in [3] */
#define GAFR2_L_AF64(x) ((x) & ALT_FN_MASK)
#define GAFR2_L_AF65(x) (((x) & ALT_FN_MASK) << 2)
@ -365,19 +373,21 @@ typedef volatile struct GPIO_registers {
#define GAFR2_L_AF78(x) (((x) & ALT_FN_MASK) << 28)
#define GAFR2_L_AF79(x) (((x) & ALT_FN_MASK) << 30)
/* GAFR2_U bits - see Table 4-29 in [1], Table 4-29 in [2] */
/* GAFR2_U bits - see Table 4-29 in [1], Table 4-29 in [2], Table 4-29 in [3] */
#define GAFR2_U_AF80(x) ((x) & ALT_FN_MASK)
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define GAFR2_U_AF81(x) (((x) & ALT_FN_MASK) << 2)
#define GAFR2_U_AF82(x) (((x) & ALT_FN_MASK) << 4)
#define GAFR2_U_AF83(x) (((x) & ALT_FN_MASK) << 6)
#define GAFR2_U_AF84(x) (((x) & ALT_FN_MASK) << 8)
#endif /* PXA255 and above only */
#if !defined(PXA2X0_NOPXA260)
#define GAFR2_U_AF85(x) (((x) & ALT_FN_MASK) << 10)
#define GAFR2_U_AF86(x) (((x) & ALT_FN_MASK) << 12)
#define GAFR2_U_AF87(x) (((x) & ALT_FN_MASK) << 14)
#define GAFR2_U_AF88(x) (((x) & ALT_FN_MASK) << 16)
#define GAFR2_U_AF89(x) (((x) & ALT_FN_MASK) << 18)
#endif /* PXA26x only */
#endif /* PXA260 and above only */
#endif /* PXA2X0_GPIO_H */

28
include/arm/pxa2x0/i2c.h
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@ -1,8 +1,8 @@
/*
* $Id$
*
* XScale PXA26x/PXA250/PXA210 I2C Registers
* Copyright (C) 2002 ETC s.r.o.
* XScale PXA26x/PXA255/PXA250/PXA210 I2C Registers
* Copyright (C) 2002, 2003 ETC s.r.o.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -28,13 +28,15 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
*
* Documentation:
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
* Developer's Manual", February 2002, Order Number: 278522-001
* [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
* October 2002, Order Number: 278638-001
* March 2003, Order Number: 278638-002
* [3] Intel Corporation, "Intel PXA255 Processor Developer's Manual"
* March 2003, Order Number: 278693-001
*
*/
@ -47,6 +49,14 @@
#include <stdint.h>
#endif
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255)
#define PXA2X0_NOPXA255
#endif
#if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260)
#define PXA2X0_NOPXA260
#endif
/* I2C Registers */
#define I2C_BASE 0x40300000
@ -82,18 +92,18 @@ typedef volatile struct I2C_registers {
#define ISR_OFFSET 0x1698
#define ISAR_OFFSET 0x16A0
/* IBMR bits - see Table 9-9 in [1], Table 9-9 in [2] */
/* IBMR bits - see Table 9-9 in [1], Table 9-9 in [2], Table 9-8 in [3] */
#define IBMR_SCLS bit(1)
#define IBMR_SDAS bit(0)
/* IDBR bits - see Table 9-10 in [1], Table 9-10 in [2] */
/* IDBR bits - see Table 9-10 in [1], Table 9-10 in [2], Table 9-9 in [3] */
#define IDBR_IDB_MASK bits(7,0)
#define IDBR_IDB(x) bits_val(7,0,x)
#define get_IDBR_IDB(x) bits_get(7,0,x)
/* ICR bits - see Table 9-11 in [1], Table 9-11 in [2] */
/* ICR bits - see Table 9-11 in [1], Table 9-11 in [2], Table 9-10 in [3] */
#define ICR_FM bit(15)
#define ICR_UR bit(14)
@ -112,7 +122,7 @@ typedef volatile struct I2C_registers {
#define ICR_STOP bit(1)
#define ICR_START bit(0)
/* ISR bits - see Table 9-12 in [1], Table 9-12 in [2] */
/* ISR bits - see Table 9-12 in [1], Table 9-12 in [2], Table 9-11 [3] */
#define ISR_BED bit(10)
#define ISR_SAD bit(9)
@ -126,7 +136,7 @@ typedef volatile struct I2C_registers {
#define ISR_ACKNAK bit(1)
#define ISR_RWM bit(0)
/* ISAR bits - see Table 9-13 in [1], Table 9-13 in [2] */
/* ISAR bits - see Table 9-13 in [1], Table 9-13 in [2], Table 9-12 [3] */
#define ISAR_ISA_MASK bits(6,0)
#define ISAR_ISA(x) bits_val(6,0,x)

32
include/arm/pxa2x0/i2s.h
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@ -1,8 +1,8 @@
/*
* $Id$
*
* XScale PXA26x/PXA250/PXA210 I2S Registers
* Copyright (C) 2002 ETC s.r.o.
* XScale PXA26x/PXA255/PXA250/PXA210 I2S Registers
* Copyright (C) 2002, 2003 ETC s.r.o.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -28,13 +28,15 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
*
* Documentation:
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
* Developer's Manual", February 2002, Order Number: 278522-001
* [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
* October 2002, Order Number: 278638-001
* March 2003, Order Number: 278638-002
* [3] Intel Corporation, "Intel PXA255 Processor Developer's Manual"
* March 2003, Order Number: 278693-001
*
*/
@ -47,6 +49,14 @@
#include <stdint.h>
#endif
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255)
#define PXA2X0_NOPXA255
#endif
#if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260)
#define PXA2X0_NOPXA260
#endif
/* I2S Registers */
#define I2S_BASE 0x40400000
@ -87,7 +97,7 @@ typedef volatile struct I2S_registers {
#define SADIV_OFFSET 0x60
#define SADR_OFFSET 0x80
/* SACR0 bits - see Table 14-3 in [1], Table 14-3 in [2] */
/* SACR0 bits - see Table 14-3 in [1], Table 14-3 in [2], Table 14-3 in [3] */
#define SACR0_RFTH_MASK bits(15,12)
#define SACR0_RFTH(x) bits_val(15,12,x)
@ -101,14 +111,14 @@ typedef volatile struct I2S_registers {
#define SACR0_BCKD bit(2)
#define SACR0_ENB bit(0)
/* SACR1 bits - see Table 14-6 in [1], Table 14-6 in [2] */
/* SACR1 bits - see Table 14-6 in [1], Table 14-6 in [2], Table 14-6 in [3] */
#define SACR1_ENLBF bit(5)
#define SACR1_DRPL bit(4)
#define SACR1_DREC bit(3)
#define SACR1_AMSL bit(0)
/* SASR0 bits - see Table 14-7 in [1], Table 14-7 in [2] */
/* SASR0 bits - see Table 14-7 in [1], Table 14-7 in [2], Table 14-7 in [3] */
#define SASR0_RFL_MASK bits(15,12)
#define SASR0_RFL(x) bits_val(15,12,x)
@ -124,25 +134,25 @@ typedef volatile struct I2S_registers {
#define SASR0_RNE bit(1)
#define SASR0_TNF bit(0)
/* SAIMR bits - see Table 14-10 in [1], Table 14-10 in [2] */
/* SAIMR bits - see Table 14-10 in [1], Table 14-10 in [2], Table 14-10 in [3] */
#define SAIMR_ROR bit(6)
#define SAIMR_TUR bit(5)
#define SAIMR_RFS bit(4)
#define SAIMR_TFS bit(3)
/* SAICR bits - see Table 14-9 in [1], Table 14-9 in [2] */
/* SAICR bits - see Table 14-9 in [1], Table 14-9 in [2], Table 14-9 in [3] */
#define SAICR_ROR bit(6)
#define SAICR_TUR bit(5)
/* SADIV bits - see Table 14-8 in [1], Table 14-8 in [2] */
/* SADIV bits - see Table 14-8 in [1], Table 14-8 in [2], Table 14-8 in [3] */
#define SADIV_SADIV_MASK bits(6,0)
#define SADIV_SADIV(x) bits_val(6,0,x)
#define get_SADIV_SADIV(x) bits_get(6,0,x)
/* SADR bits - see Table 14-11 in [1], Table 14-11 in [2] */
/* SADR bits - see Table 14-11 in [1], Table 14-11 in [2], Table 14-11 in [3] */
#define SADR_DTH_MASK bits(31,16)
#define SADR_DTH(x) bits_val(31,16,x)

42
include/arm/pxa2x0/ic.h
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@ -1,8 +1,8 @@
/*
* $Id$
*
* XScale PXA26x/PXA250/PXA210 Interrupt Control Registers
* Copyright (C) 2002 ETC s.r.o.
* XScale PXA26x/PXA255/PXA250/PXA210 Interrupt Control Registers
* Copyright (C) 2002, 2003 ETC s.r.o.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -28,13 +28,15 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
*
* Documentation:
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
* Developer's Manual", February 2002, Order Number: 278522-001
* [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
* October 2002, Order Number: 278638-001
* March 2003, Order Number: 278638-002
* [3] Intel Corporation, "Intel PXA255 Processor Developer's Manual"
* March 2003, Order Number: 278693-001
*
*/
@ -47,8 +49,12 @@
#include <stdint.h>
#endif
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA26X)
#define PXA2X0_NOPXA26X
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255)
#define PXA2X0_NOPXA255
#endif
#if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260)
#define PXA2X0_NOPXA260
#endif
/* Interrupt Control Registers */
@ -101,10 +107,12 @@ typedef volatile struct IC_registers {
#define IC_IRQ19 bit(19)
#define IC_IRQ18 bit(18)
#define IC_IRQ17 bit(17)
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define IC_IRQ16 bit(16)
#endif /* PXA255 and above only */
#if !defined(PXA2X0_NOPXA260)
#define IC_IRQ15 bit(15)
#endif /* PXA26x only */
#endif /* PXA260 and above only */
#define IC_IRQ14 bit(14)
#define IC_IRQ13 bit(13)
#define IC_IRQ12 bit(12)
@ -112,11 +120,11 @@ typedef volatile struct IC_registers {
#define IC_IRQ10 bit(10)
#define IC_IRQ9 bit(9)
#define IC_IRQ8 bit(8)
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define IC_IRQ7 bit(7)
#endif /* PXA26x only */
#endif /* PXA255 and above only */
/* symbolic names for IRQs - see Table 4-36 in [1], Table 4-36 in [2] */
/* symbolic names for IRQs - see Table 4-36 in [1], Table 4-36 in [2], Table 4-36 in [3] */
#define IC_IRQ_RTC_ALARM IC_IRQ31
#define IC_IRQ_RTC_HZ IC_IRQ30
@ -133,10 +141,12 @@ typedef volatile struct IC_registers {
#define IC_IRQ_ICP IC_IRQ19
#define IC_IRQ_I2C IC_IRQ18
#define IC_IRQ_LCD IC_IRQ17
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define IC_IRQ_NSSP IC_IRQ16
#endif /* PXA255 and above only */
#if !defined(PXA2X0_NOPXA260)
#define IC_IRQ_ASSP IC_IRQ15
#endif /* PXA26x only */
#endif /* PXA260 and above only */
#define IC_IRQ_AC97 IC_IRQ14
#define IC_IRQ_I2S IC_IRQ13
#define IC_IRQ_PMU IC_IRQ12
@ -144,11 +154,11 @@ typedef volatile struct IC_registers {
#define IC_IRQ_GPIO IC_IRQ10
#define IC_IRQ_GPIO1 IC_IRQ9
#define IC_IRQ_GPIO0 IC_IRQ8
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define IC_IRQ_HWUART IC_IRQ7
#endif /* PXA26x only */
#endif /* PXA255 and above only */
/* ICCR bits - see Table 4-33 in [1], Table in [2] */
/* ICCR bits - see Table 4-33 in [1], Table 4-33 in [2], Table 4-32 in [3] */
#define ICCR_DIM bit(0)

30
include/arm/pxa2x0/icp.h
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@ -1,8 +1,8 @@
/*
* $Id$
*
* XScale PXA26x/PXA250/PXA210 ICP Registers
* Copyright (C) 2002 ETC s.r.o.
* XScale PXA26x/PXA255/PXA250/PXA210 ICP Registers
* Copyright (C) 2002, 2003 ETC s.r.o.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -28,13 +28,15 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
*
* Documentation:
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
* Developer's Manual", February 2002, Order Number: 278522-001
* [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
* October 2002, Order Number: 278638-001
* March 2003, Order Number: 278638-002
* [3] Intel Corporation, "Intel PXA255 Processor Developer's Manual"
* March 2003, Order Number: 278693-001
*
*/
@ -47,6 +49,14 @@
#include <stdint.h>
#endif
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255)
#define PXA2X0_NOPXA255
#endif
#if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260)
#define PXA2X0_NOPXA260
#endif
/* ICP Registers */
#define ICP_BASE 0x40800000
@ -81,7 +91,7 @@ typedef volatile struct ICP_registers {
#define ICSR0_OFFSET 0x14
#define ICSR1_OFFSET 0x18
/* ICCR0 bits - see Table 11-2 in [1], Table 11-2 in [2] */
/* ICCR0 bits - see Table 11-2 in [1], Table 11-2 in [2], Table 11-2 in [3] */
#define ICCR0_AME bit(7)
#define ICCR0_TIE bit(6)
@ -92,13 +102,13 @@ typedef volatile struct ICP_registers {
#define ICCR0_LBM bit(1)
#define ICCR0_ITR bit(0)
/* ICCR1 bits - see Table 11-3 in [1], Table 11-3 in [2] */
/* ICCR1 bits - see Table 11-3 in [1], Table 11-3 in [2], Table 11-3 in [3] */
#define ICCR1_AMV_MASK bits(7,0)
#define ICCR1_AMV(x) bits_val(7,0,x)
#define get_ICCR1_AMV(x) bits_get(7,0,x)
/* ICCR2 bits - see Table 11-4 in [1], Table 11-4 in [2] */
/* ICCR2 bits - see Table 11-4 in [1], Table 11-4 in [2], Table 11-4 in [3] */
#define ICCR2_RXP bit(3)
#define ICCR2_TXP bit(2)
@ -106,13 +116,13 @@ typedef volatile struct ICP_registers {
#define ICCR2_TRIG(x) bits_val(1,0,x)
#define get_ICCR2_TRIG(x) bits_get(1,0,x)
/* ICDR bits - see Table 11-5 in [1], Table 11-5 in [2] */
/* ICDR bits - see Table 11-5 in [1], Table 11-5 in [2], Table 11-5 in [3] */
#define ICDR_DATA_MASK bits(7,0)
#define ICDR_DATA(x) bits_val(7,0,x)
#define get_ICDR_DATA(x) bits_get(7,0,x)
/* ICSR0 bits - see Table 11-6 in [1], Table 11-6 in [2] */
/* ICSR0 bits - see Table 11-6 in [1], Table 11-6 in [2], Table 11-6 in [3] */
#define ICSR0_FRE bit(5)
#define ICSR0_RFS bit(4)
@ -121,7 +131,7 @@ typedef volatile struct ICP_registers {
#define ICSR0_TUR bit(1)
#define ICSR0_EIF bit(0)
/* ICSR1 bits - see Table 11-7 in [1], Table 11-7 in [2] */
/* ICSR1 bits - see Table 11-7 in [1], Table 11-7 in [2], Table 11-7 in [3] */
#define ICSR1_ROR bit(6)
#define ICSR1_CRE bit(5)

42
include/arm/pxa2x0/lcd.h
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@ -1,8 +1,8 @@
/*
* $Id$
*
* XScale PXA26x/PXA250/PXA210 LCD Controller Registers
* Copyright (C) 2002 ETC s.r.o.
* XScale PXA26x/PXA255/PXA250/PXA210 LCD Controller Registers
* Copyright (C) 2002, 2003 ETC s.r.o.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -28,13 +28,15 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
*
* Documentation:
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
* Developer's Manual", February 2002, Order Number: 278522-001
* [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
* October 2002, Order Number: 278638-001
* March 2003, Order Number: 278638-002
* [3] Intel Corporation, "Intel PXA255 Processor Developer's Manual"
* March 2003, Order Number: 278693-001
*
*/
@ -47,6 +49,14 @@
#include <stdint.h>
#endif
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255)
#define PXA2X0_NOPXA255
#endif
#if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260)
#define PXA2X0_NOPXA260
#endif
/* LCD Controller Registers */
#define LCD_BASE 0x44000000
@ -117,7 +127,7 @@ typedef volatile struct LCD_registers {
#define FIDR1_OFFSET 0x218
#define LDCMD1_OFFSET 0x21C
/* LCCR0 bits - see Table 7-2 in [1], Table 7-2 in [2] */
/* LCCR0 bits - see Table 7-2 in [1], Table 7-2 in [2], Table 7-3 in [3] */
#define LCCR0_OUM bit(21)
#define LCCR0_BM bit(20)
@ -136,7 +146,7 @@ typedef volatile struct LCD_registers {
#define LCCR0_CMS bit(1)
#define LCCR0_ENB bit(0)
/* LCCR1 bits - see Table 7-5 in [1], Table 7-4 in [2] */
/* LCCR1 bits - see Table 7-5 in [1], Table 7-4 in [2], Table 7-4 in [3] */
#define LCCR1_BLW_MASK bits(31,24)
#define LCCR1_BLW(x) bits_val(31,24,x)
@ -151,7 +161,7 @@ typedef volatile struct LCD_registers {
#define LCCR1_PPL(x) bits_val(9,0,x)
#define get_LCCR1_PPL(x) bits_get(9,0,x)
/* LCCR2 bits - see Table 7-6 in [1], Table 7-5 in [2] */
/* LCCR2 bits - see Table 7-6 in [1], Table 7-5 in [2], Table 7-5 in [3] */
#define LCCR2_BFW_MASK bits(31,24)
#define LCCR2_BFW(x) bits_val(31,24,x)
@ -166,7 +176,7 @@ typedef volatile struct LCD_registers {
#define LCCR2_LPP(x) bits_val(9,0,x)
#define get_LCCR2_LPP(x) bits_get(9,0,x)
/* LCCR3 bits - see Table 7-7 in [1], Table 7-6 in [2] */
/* LCCR3 bits - see Table 7-7 in [1], Table 7-6 in [2], Table 7-6 in [3] */
#define LCCR3_DPC bit(27)
#define LCCR3_BPP_MASK bits(26,24)
@ -186,17 +196,17 @@ typedef volatile struct LCD_registers {
#define LCCR3_PCD(x) bits_val(7,0,x)
#define get_LCCR3_PCD(x) bits_get(7,0,x)
/* FBR0 bits - see Table 7-12 in [1], Table 7-11 in [2] */
/* FBR0 bits - see Table 7-12 in [1], Table 7-11 in [2], Table 7-11 in [3] */
#define FBR0_BINT bit(1)
#define FBR0_BRA bit(0)
/* FBR1 bits - see Table 7-12 in [1], Table 7-11 in [2] */
/* FBR1 bits - see Table 7-12 in [1], Table 7-11 in [2], Table 7-11 in [3] */
#define FBR1_BINT bit(1)
#define FBR1_BRA bit(0)
/* LCSR bits - see Table 7-13 in [1], Table 7-12 in [2] */
/* LCSR bits - see Table 7-13 in [1], Table 7-12 in [2], Table 7-12 in [3] */
#define LCSR_SINT bit(10)
#define LCSR_BS bit(9)
@ -210,13 +220,13 @@ typedef volatile struct LCD_registers {
#define LCSR_SOF bit(1)
#define LCSR_LDD bit(0)
/* LIIDR bits - see Table 7-14 in [1], Table 7-13 in [2] */
/* LIIDR bits - see Table 7-14 in [1], Table 7-13 in [2], Table 7-13 in [3] */
#define LIIDR_IFRAMEID_MASK bits(31,3)
#define LIIDR_IFRAMEID(x) bits_val(31,3,x)
#define get_LIIDR_IFRAMEID(x) bits_get(31,3,x)
/* TRGBR bits - see Table 7-15 in [1], Table 7-14 in [2] */
/* TRGBR bits - see Table 7-15 in [1], Table 7-14 in [2], Table 7-14 in [3] */
#define TRGBR_TBS_MASK bits(23,16)
#define TRGBR_TBS(x) bits_val(23,16,x)
@ -228,7 +238,7 @@ typedef volatile struct LCD_registers {
#define TRGBR_TRS(x) bits_val(7,0,x)
#define get_TRGBR_TRS(x) bits_vat(7,0,x)
/* TCR bits - see Table 7-16 in [1], Table 7-15 in [2] */
/* TCR bits - see Table 7-16 in [1], Table 7-15 in [2], Table 7-15 in [3] */
#define TCR_TED bit(14)
#define TCR_THBS_MASK bits(11,8)
@ -242,7 +252,7 @@ typedef volatile struct LCD_registers {
#define TCR_FNAM bit(1)
#define TCR_COAM bit(0)
/* LDCMD0 bits - see Table 7-11 in [1], Table 7-10 in [2] */
/* LDCMD0 bits - see Table 7-11 in [1], Table 7-10 in [2], Table 7-10 in [3] */
#define LDCMD0_PAL bit(26)
#define LDCMD0_SOFINT bit(22)
@ -251,7 +261,7 @@ typedef volatile struct LCD_registers {
#define LDCMD0_LEN(x) bits_val(20,0,x)
#define get_LDCMD0_LEN(x) bits_get(20,0,x)
/* LDCMD1 bits - see Table 7-11 in [1], Table 7-10 in [2] */
/* LDCMD1 bits - see Table 7-11 in [1], Table 7-10 in [2], Table 7-10 in [3] */
#define LDCMD1_PAL bit(26)
#define LDCMD1_SOFINT bit(22)

72
include/arm/pxa2x0/mc.h
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@ -1,8 +1,8 @@
/*
* $Id$
*
* XScale PXA26x/PXA250/PXA210 Memory Controller Registers
* Copyright (C) 2002 ETC s.r.o.
* XScale PXA26x/PXA255/PXA250/PXA210 Memory Controller Registers
* Copyright (C) 2002, 2003 ETC s.r.o.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -28,15 +28,17 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
*
* Documentation:
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
* Developer's Manual", February 2002, Order Number: 278522-001
* [2] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
* Specification Update", January 2003, Order Number: 278534-0011
* Specification Update", February 2003, Order Number: 278534-012
* [3] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
* October 2002, Order Number: 278638-001
* March 2003, Order Number: 278638-002
* [4] Intel Corporation, "Intel PXA255 Processor Developer's Manual"
* March 2003, Order Number: 278693-001
*
*/
@ -49,8 +51,12 @@
#include <stdint.h>
#endif
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA26X)
#define PXA2X0_NOPXA26X
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255)
#define PXA2X0_NOPXA255
#endif
#if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260)
#define PXA2X0_NOPXA260
#endif
/* Memory Controller Registers */
@ -77,12 +83,14 @@ typedef volatile struct MC_registers {
uint32_t mcio1;
uint32_t mdmrs;
uint32_t boot_def;
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
uint32_t __reserved3[4];
uint32_t mdmrslp;
#endif /* PXA255 and above only */
#if !defined(PXA2X0_NOPXA260)
uint32_t __reserved4[2];
uint32_t sa1111cr;
#endif /* PXA26x only */
#endif /* PXA260 and above only */
} MC_registers_t;
#ifdef PXA2X0_UNMAPPED
@ -105,10 +113,12 @@ typedef volatile struct MC_registers {
#define MCIO1 MC_pointer->mcio1
#define MDMRS MC_pointer->mdmrs
#define BOOT_DEF MC_pointer->boot_def
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define MDMRSLP MC_pointer->mdmrslp
#endif /* PXA255 and above only */
#if !defined(PXA2X0_NOPXA260)
#define SA1111CR MC_pointer->sa1111cr
#endif /* PXA26x only */
#endif /* PXA260 and above only */
#endif /* LANGUAGE == C */
#define MDCNFG_OFFSET 0x00
@ -127,12 +137,14 @@ typedef volatile struct MC_registers {
#define MCIO1_OFFSET 0x3C
#define MDMRS_OFFSET 0x40
#define BOOT_DEF_OFFSET 0x44
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define MDMRSLP_OFFSET 0x58
#endif /* PXA255 and above only */
#if !defined(PXA2X0_NOPXA260)
#define SA1111CR_OFFSET 0x64
#endif /* PXA26x only */
#endif /* PXA260 and above only */
/* MDCNFG bits - see Table 6-3 in [1] and D25 in [2], Table 6-3 in [3] */
/* MDCNFG bits - see Table 6-3 in [1] and D25 in [2], Table 6-3 in [3], Table 6-2 in [4] */
#define MDCNFG_DSA1111_2 bit(28)
#define MDCNFG_DLATCH2 bit(27)
@ -165,7 +177,7 @@ typedef volatile struct MC_registers {
#define MDCNFG_DE1 bit(1)
#define MDCNFG_DE0 bit(0)
/* MDREFR bits - see Table 6-5 in [1], Table 6-6 in [3] */
/* MDREFR bits - see Table 6-5 in [1], Table 6-6 in [3], Table 6-5 in [4] */
#define MDREFR_K2FREE bit(25)
#define MDREFR_K1FREE bit(24)
@ -184,7 +196,7 @@ typedef volatile struct MC_registers {
#define MDREFR_DRI(x) bits_val(11,0,x)
#define get_MDREFR_DRI(x) bits_get(11,0,x)
/* MSC0 bits - see Table 6-21 in [1], Table 6-25 in [3] */
/* MSC0 bits - see Table 6-21 in [1], Table 6-25 in [3], Table 6-21 in [4] */
#define MSC0_RBUFF1 bit(31)
#define MSC0_RRR1_MASK bits(30,28)
@ -215,7 +227,7 @@ typedef volatile struct MC_registers {
#define MSC0_RT0(x) bits_val(2,0,x)
#define get_MSC0_RT0(x) bits_get(2,0,x)
/* MSC1 bits - see Table 6-21 in [1], Table 6-25 in [3] */
/* MSC1 bits - see Table 6-21 in [1], Table 6-25 in [3], Table 6-21 in [4] */
#define MSC1_RBUFF3 bit(31)
#define MSC1_RRR3_MASK bits(30,28)
@ -246,7 +258,7 @@ typedef volatile struct MC_registers {
#define MSC1_RT2(x) bits_val(2,0,x)
#define get_MSC1_RT2(x) bits_get(2,0,x)
/* MSC2 bits - see Table 6-21 in [1], Table 6-25 in [3] */
/* MSC2 bits - see Table 6-21 in [1], Table 6-25 in [3], Table 6-21 in [4] */
#define MSC2_RBUFF5 bit(31)
#define MSC2_RRR5_MASK bits(30,28)
@ -277,12 +289,12 @@ typedef volatile struct MC_registers {
#define MSC2_RT4(x) bits_val(2,0,x)
#define get_MSC2_RT4(x) bits_get(2,0,x)
/* MECR bits - see Table 6-27 in [1], Table 6-31 in [3] */
/* MECR bits - see Table 6-27 in [1], Table 6-31 in [3], Table 6-27 in [4] */
#define MECR_CIT bit(1)
#define MECR_NOS bit(0)
/* SXCNFG bits - see Table 6-13 in [1], Table 6-14 in [3] */
/* SXCNFG bits - see Table 6-13 in [1], Table 6-14 in [3], Table 6-13 in [4] */
#define SXCNFG_SXLATCH2 bit(30)
#define SXCNFG_SXTP2_MASK bits(29,28)
@ -321,7 +333,7 @@ typedef volatile struct MC_registers {
#define SXCNFG_SXEN0(x) bits_val(1,0,x)
#define get_SXCNFG_SXEN0(x) bits_get(1,0,x)
/* SXMRS bits - see Table 6-16 in [1], Table 6-17 in [3] */
/* SXMRS bits - see Table 6-16 in [1], Table 6-17 in [3], Table 6-16 in [4] */
#define SXMRS_SXMRS2_MASK bits(30,16)
#define SXMRS_SXMRS2(x) bits_val(30,16,x)
@ -330,7 +342,7 @@ typedef volatile struct MC_registers {
#define SXMRS_SXMRS0(x) bits_val(14,0,x)
#define get_SXMRS_SXMRS0(x) bits_get(14,0,x)
/* MCMEMx bits - see Table 6-23 in [1], Table 6-27 in [3] */
/* MCMEMx bits - see Table 6-23 in [1], Table 6-27 in [3], Table 6-23 in [4] */
#define MCMEM_HOLD_MASK bits(19,14)
#define MCMEM_HOLD(x) bits_val(19,14,x)
@ -342,7 +354,7 @@ typedef volatile struct MC_registers {
#define MCMEM_SET(x) bits_val(6,0,x)
#define get_MCMEM_SET(x) bits_get(6,0,x)
/* MCATTx bits - see Table 6-24 in [1], Table 6-28 in [3] */
/* MCATTx bits - see Table 6-24 in [1], Table 6-28 in [3], Table 6-24 in [4] */
#define MCATT_HOLD_MASK bits(19,14)
#define MCATT_HOLD(x) bits_val(19,14,x)
@ -354,7 +366,7 @@ typedef volatile struct MC_registers {
#define MCATT_SET(x) bits_val(6,0,x)
#define get_MCATT_SET(x) bits_get(6,0,x)
/* MCIOx bits - see Table 6-25 in [1], Table 6-29 in [3] */
/* MCIOx bits - see Table 6-25 in [1], Table 6-29 in [3], Table 6-25 in [4] */
#define MCIO_HOLD_MASK bits(19,14)
#define MCIO_HOLD(x) bits_val(19,14,x)
@ -366,7 +378,7 @@ typedef volatile struct MC_registers {
#define MCIO_SET(x) bits_val(6,0,x)
#define get_MCIO_SET(x) bits_get(6,0,x)
/* MDMRS bits - see Table 6-4 in [1], Table 6-4 in [3] */
/* MDMRS bits - see Table 6-4 in [1], Table 6-4 in [3], Table 6-3 in [4] */
#define MDMRS_MDMRS2_MASK bits(30,23)
#define MDMRS_MDMRS2(x) bits_val(30,23,x)
@ -389,15 +401,15 @@ typedef volatile struct MC_registers {
#define MDMRS_MDBL0(x) bits_val(2,0,x)
#define get_MDMRS_MDBL0(x) bits_get(2,0,x)
/* BOOT_DEF bits - see Table 6-37 in [1], Table 6-40 in [3] */
/* BOOT_DEF bits - see Table 6-37 in [1], Table 6-40 in [3], Table 6-37 in [4] */
#define BOOT_DEF_PKG_TYPE bit(3)
#define BOOT_DEF_BOOT_SEL_MASK bits(2,0)
#define BOOT_DEF_BOOT_SEL(x) bits_val(2,0,x)
#define get_BOOT_DEF_BOOT_SEL(x) bits_get(2,0,x)
#if !defined(PXA2X0_NOPXA26X)
/* MDMRSLP bits - see Table 6-5 in [3] */
#if !defined(PXA2X0_NOPXA255)
/* MDMRSLP bits - see Table 6-5 in [3], Table 6-4 in [4] */
#define MDMRSLP_MDLPEN2 bit(31)
#define MDMRSLP_MDMRSLP2_MASK bits(30,16)
@ -407,7 +419,9 @@ typedef volatile struct MC_registers {
#define MDMRSLP_MDMRSLP0_MASK bits(14,0)
#define MDMRSLP_MDMRSLP0(x) bits_val(14,0,x)
#define get_MDMRSLP_MDMRSLP0(x) bits_get(14,0,x)
#endif /* PXA255 and above only */
#if !defined(PXA2X0_NOPXA260)
/* SA1111CR bits - see Table 6-24 in [3] */
#define SA1111CR_SA1111_5 bit(5)
@ -416,6 +430,6 @@ typedef volatile struct MC_registers {
#define SA1111CR_SA1111_2 bit(2)
#define SA1111CR_SA1111_1 bit(1)
#define SA1111CR_SA1111_0 bit(0)
#endif /* PXA26x only */
#endif /* PXA260 and above only */
#endif /* PXA2X0_MC_H */

56
include/arm/pxa2x0/mmc.h
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@ -1,8 +1,8 @@
/*
* $Id$
*
* XScale PXA26x/PXA250/PXA210 MMC Controller Registers
* Copyright (C) 2002 ETC s.r.o.
* XScale PXA26x/PXA255/PXA250/PXA210 MMC Controller Registers
* Copyright (C) 2002, 2003 ETC s.r.o.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -28,13 +28,15 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
*
* Documentation:
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
* Developer's Manual", February 2002, Order Number: 278522-001
* [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
* October 2002, Order Number: 278638-001
* March 2003, Order Number: 278638-002
* [3] Intel Corporation, "Intel PXA255 Processor Developer's Manual"
* March 2003, Order Number: 278693-001
*
*/
@ -47,6 +49,14 @@
#include <stdint.h>
#endif
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255)
#define PXA2X0_NOPXA255
#endif
#if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260)
#define PXA2X0_NOPXA260
#endif
/* MMC Controller Registers */
#define MMC_BASE 0x41100000
@ -116,13 +126,13 @@ typedef volatile struct MMC_registers {
#define MMC_RXFIFO_OFFSET 0x40
#define MMC_TXFIFO_OFFSET 0x44
/* MMC_STRPCL bits - see Table 15-6 in [1], Table 15-6 in [2] */
/* MMC_STRPCL bits - see Table 15-6 in [1], Table 15-6 in [2], Table 15-5 in [3] */
#define MMC_STRPCL_STRPCL_MASK bits(1,0)
#define MMC_STRPCL_STRPCL(x) bits_val(1,0,x)
#define get_MMC_STRPCL_STRPCL(x) bits_get(1,0,x)
/* MMC_STAT bits - see Table 15-7 in [1], Table 15-7 in [2] */
/* MMC_STAT bits - see Table 15-7 in [1], Table 15-7 in [2], Table 15-6 in [3] */
#define MMC_STAT_END_CMD_RES bit(13)
#define MMC_STAT_PRG_DONE bit(12)
@ -137,20 +147,20 @@ typedef volatile struct MMC_registers {
#define MMC_STAT_TIME_OUT_RESPONSE bit(1)
#define MMC_STAT_READ_TIME_OUT bit(0)
/* MMC_CLKRT bits - see Table 15-8 in [1], Table 15-8 in [2] */
/* MMC_CLKRT bits - see Table 15-8 in [1], Table 15-8 in [2], Table 15-7 in [3] */
#define MMC_CLKRT_CLK_RATE_MASK bits(2,0)
#define MMC_CLKRT_CLK_RATE(x) bits_val(2,0,x)
#define get_MMC_CLKRT_CLK_RATE(x) bits_get(2,0,x)
/* MMC_SPI bits - see Table 15-9 in [1], Table 15-9 in [2] */
/* MMC_SPI bits - see Table 15-9 in [1], Table 15-9 in [2], Table 15-8 in [3] */
#define MMC_SPI_SPI_CS_ADDRESS bit(3)
#define MMC_SPI_SPI_CS_EN bit(2)
#define MMC_SPI_CRC_ON bit(1)
#define MMC_SPI_SPI_EN bit(0)
/* MMC_CMDAT bits - see Table 15-10 in [1], Table 15-10 in [2] */
/* MMC_CMDAT bits - see Table 15-10 in [1], Table 15-10 in [2], Table 15-9 in [3] */
#define MMC_CMDAT_MMC_DMA_EN bit(7)
#define MMC_CMDAT_INIT bit(6)
@ -162,35 +172,35 @@ typedef volatile struct MMC_registers {
#define MMC_CMDAT_RESPONSE_FORMAT(x) bits_val(1,0,x)
#define get_MMC_CMDAT_RESPONSE_FORMAT(x) bits_get(1,0,x)
/* MMC_RESTO bits - see Table 15-11 in [1], Table 15-11 in [2] */
/* MMC_RESTO bits - see Table 15-11 in [1], Table 15-11 in [2], Table 15-10 in [3] */
#define MMC_RESTO_RES_TO_MASK bits(6,0)
#define MMC_RESTO_RES_TO(x) bits_val(6,0,x)
#define get_MMC_RESTO_RES_TO(x) bits_get(6,0,x)
/* MMC_RDTO bits - see Table 15-12 in [1], Table 15-12 in [2] */
/* MMC_RDTO bits - see Table 15-12 in [1], Table 15-12 in [2], Table 15-11 in [3] */
#define MMC_RDTO_READ_TO_MASK bits(15,0)
#define MMC_RDTO_READ_TO(x) bits_val(15,0,x)
#define get_MMC_RDTO_READ_TO(x) bits_get(15,0,x)
/* MMC_BLKLEN bits - see Table 15-13 in [1], Table 15-13 in [2] */
/* MMC_BLKLEN bits - see Table 15-13 in [1], Table 15-13 in [2], Table 15-12 in [3] */
#define MMC_BLKLEN_BLK_LEN_MASK bits(9,0)
#define MMC_BLKLEN_BLK_LEN(x) bits_val(9,0,x)
#define get_MMC_BLKLEN_BLK_LEN(x) bits_get(9,0,x)
/* MMC_NOB bits - see Table 15-14 in [1], Table 15-14 in [2] */
/* MMC_NOB bits - see Table 15-14 in [1], Table 15-14 in [2], Table 15-13 in [3] */
#define MMC_NOB_MMC_NOB_MASK bits(15,0)
#define MMC_NOB_MMC_NOB(x) bits_val(15,0,x)
#define get_MMC_NOB_MMC_NOB(x) bits_get(15,0,x)
/* MMC_PRTBUF bits - see Table 15-15 in [1], Table 15-15 in [2] */
/* MMC_PRTBUF bits - see Table 15-15 in [1], Table 15-15 in [2], Table 15-14 in [3] */
#define MMC_PRTBUF_BUF_PART_FULL bit(0)
/* MMC_I_MASK bits - see Table 15-16 in [1], Table 15-16 in [2] */
/* MMC_I_MASK bits - see Table 15-16 in [1], Table 15-16 in [2], Table 15-15 in [3] */
#define MMC_I_MASK_TXFIFO_WR_REQ bit(6)
#define MMC_I_MASK_RXFIFO_RD_REQ bit(5)
@ -200,7 +210,7 @@ typedef volatile struct MMC_registers {
#define MMC_I_MASK_PRG_DONE bit(1)
#define MMC_I_MASK_DATA_TRAN_DONE bit(0)
/* MMC_I_REG bits - see Table 15-17 in [1], Table 15-17 in [2] */
/* MMC_I_REG bits - see Table 15-17 in [1], Table 15-17 in [2], Table 15-16 in [3] */
#define MMC_I_REG_TXFIFO_WR_REQ bit(6)
#define MMC_I_REG_RXFIFO_RD_REQ bit(5)
@ -210,13 +220,13 @@ typedef volatile struct MMC_registers {
#define MMC_I_REG_PRG_DONE bit(1)
#define MMC_I_REG_DATA_TRAN_DONE bit(0)
/* MMC_CMD bits - see Table 15-18 in [1], Table 15-18 in [2] */
/* MMC_CMD bits - see Table 15-18 in [1], Table 15-18 in [2], Table 15-17 in [3] */
#define MMC_CMD_CMD_INDEX_MASK bits(5,0)
#define MMC_CMD_CMD_INDEX(x) bits_val(5,0,x)
#define get_MMC_CMD_CMD_INDEX(x) bits_get(5,0,x)
/* MMC commands (for MMC_CMD) - see Table 15-19 in [1], Table 15-19 in [2] */
/* MMC commands (for MMC_CMD) - see Table 15-19 in [1], Table 15-19 in [2], Table 15-18 in [3] */
#define MMC_CMD_GO_IDLE_STATE MMC_CMD_CMD_INDEX(0)
#define MMC_CMD_SEND_OP_COND MMC_CMD_CMD_INDEX(1)
@ -256,31 +266,31 @@ typedef volatile struct MMC_registers {
#define MMC_CMD_READ_OCR MMC_CMD_CMD_INDEX(58)
#define MMC_CMD_CRC_ON_OFF MMC_CMD_CMD_INDEX(59)
/* MMC_ARGH bits - see Table 15-20 in [1], Table 15-20 in [2] */
/* MMC_ARGH bits - see Table 15-20 in [1], Table 15-20 in [2], Table 15-19 in [3] */
#define MMC_ARGH_ARG_H_MASK bits(15,0)
#define MMC_ARGH_ARG_H(x) bits_val(15,0,x)
#define get_MMC_ARGH_ARG_H(x) bits_get(15,0,x)
/* MMC_ARGL bits - see Table 15-21 in [1], Table 15-21 in [2] */
/* MMC_ARGL bits - see Table 15-21 in [1], Table 15-21 in [2], Table 15-20 in [3] */
#define MMC_ARGL_ARG_L_MASK bits(15,0)
#define MMC_ARGL_ARG_L(x) bits_val(15,0,x)
#define get_MMC_ARGL_ARG_L(x) bits_get(15,0,x)
/* MMC_RES bits - see Table 15-22 in [1], Table 15-22 in [2] */
/* MMC_RES bits - see Table 15-22 in [1], Table 15-22 in [2], Table 15-21 in [3] */
#define MMC_RES_RESPONSE_DATA_MASK bits(15,0)
#define MMC_RES_RESPONSE_DATA(x) bits_val(15,0,x)
#define get_MMC_RES_RESPONSE_DATA(x) bits_get(15,0,x)
/* MMC_RXFIFO bits - see Table 15-23 in [1], Table 15-23 in [2] */
/* MMC_RXFIFO bits - see Table 15-23 in [1], Table 15-23 in [2], Table 15-22 in [3] */
#define MMC_RXFIFO_READ_DATA_MASK bits(7,0)
#define MMC_RXFIFO_READ_DATA(x) bits_val(7,0,x)
#define get_MMC_RXFIFO_READ_DATA(x) bits_get(7,0,x)
/* MMC_TXFIFO bits - see Table 15-24 in [1], Table 15-24 in [2] */
/* MMC_TXFIFO bits - see Table 15-24 in [1], Table 15-24 in [2], Table 15-23 in [3] */
#define MMC_TXFIFO_WRITE_DATA_MASK bits(7,0)
#define MMC_TXFIFO_WRITE_DATA(x) bits_val(7,0,x)

24
include/arm/pxa2x0/ost.h
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@ -1,8 +1,8 @@
/*
* $Id$
*
* XScale PXA26x/PXA250/PXA210 OS Timer Registers
* Copyright (C) 2002 ETC s.r.o.
* XScale PXA26x/PXA255/PXA250/PXA210 OS Timer Registers
* Copyright (C) 2002, 2003 ETC s.r.o.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -28,13 +28,15 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
*
* Documentation:
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
* Developer's Manual", February 2002, Order Number: 278522-001
* [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
* October 2002, Order Number: 278638-001
* March 2003, Order Number: 278638-002
* [3] Intel Corporation, "Intel PXA255 Processor Developer's Manual"
* March 2003, Order Number: 278693-001
*
*/
@ -47,6 +49,14 @@
#include <stdint.h>
#endif
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255)
#define PXA2X0_NOPXA255
#endif
#if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260)
#define PXA2X0_NOPXA260
#endif
/* OS Timer Registers */
#define OST_BASE 0x40A00000
@ -84,18 +94,18 @@ typedef volatile struct OST_registers {
#define OWER_OFFSET 0x18
#define OIER_OFFSET 0x1C
/* OSSR bits - see 4.4.2.5 in [1], Table 4-48 in [2] */
/* OSSR bits - see 4.4.2.5 in [1], Table 4-48 in [2], Table 4-45 in [3] */
#define OSSR_M3 bit(3)
#define OSSR_M2 bit(2)
#define OSSR_M1 bit(1)
#define OSSR_M0 bit(0)
/* OWER bits - see Table 4-46 in [1], Table 4-46 in [2] */
/* OWER bits - see Table 4-46 in [1], Table 4-46 in [2], Table 4-43 in [3] */
#define OWER_WME bit(0)
/* OIER bits - see Table 4-45 in [1], Table 4-45 in [2] */
/* OIER bits - see Table 4-45 in [1], Table 4-45 in [2], Table 4-42 in [3] */
#define OIER_E3 bit(3)
#define OIER_E2 bit(2)

28
include/arm/pxa2x0/pmrc.h
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@ -1,8 +1,8 @@
/*
* $Id$
*
* XScale PXA26x/PXA250/PXA210 Power Manager and Reset Control Registers
* Copyright (C) 2002 ETC s.r.o.
* XScale PXA26x/PXA255/PXA250/PXA210 Power Manager and Reset Control Registers
* Copyright (C) 2002, 2003 ETC s.r.o.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -28,13 +28,15 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
*
* Documentation:
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
* Developer's Manual", February 2002, Order Number: 278522-001
* [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
* October 2002, Order Number: 278638-001
* March 2003, Order Number: 278638-002
* [3] Intel Corporation, "Intel PXA255 Processor Developer's Manual"
* March 2003, Order Number: 278693-001
*
*/
@ -47,6 +49,14 @@
#include <stdint.h>
#endif
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255)
#define PXA2X0_NOPXA255
#endif
#if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260)
#define PXA2X0_NOPXA260
#endif
/* Power Manager and Reset Control Registers */
#define PMRC_BASE 0x40F00000
@ -99,11 +109,11 @@ typedef volatile struct PMRC_registers {
#define PGSR2_OFFSET 0x28
#define RCSR_OFFSET 0x30
/* PMCR bits - see Table 3-7 in [1], Table 3-7 in [2] */
/* PMCR bits - see Table 3-7 in [1], Table 3-7 in [2], Table 3-7 in [3] */
#define PMCR_IDAE bit(0)
/* PSSR bits - see Table 3-13 in [1], Table 3-13 in [2] */
/* PSSR bits - see Table 3-13 in [1], Table 3-13 in [2], Table 3-13 in [3] */
#define PSSR_RDH bit(5)
#define PSSR_PH bit(4)
@ -111,7 +121,7 @@ typedef volatile struct PMRC_registers {
#define PSSR_BFS bit(1)
#define PSSR_SSS bit(0)
/* PWER bits - see Table 3-9 in [1], Table 3-9 in [2] */
/* PWER bits - see Table 3-9 in [1], Table 3-9 in [2], Table 3-9 in [3] */
#define PWER_WERTC bit(31)
#define PWER_WE15 bit(15)
@ -131,13 +141,13 @@ typedef volatile struct PMRC_registers {
#define PWER_WE1 bit(1)
#define PWER_WE0 bit(0)
/* PCFR bits - see Table 3-8 in [1], Table 3-8 in [2] */
/* PCFR bits - see Table 3-8 in [1], Table 3-8 in [2], Table 3-8 in [3] */
#define PCFR_FS bit(2)
#define PCFR_FP bit(1)
#define PCFR_OPDE bit(0)
/* RCSR bits - see Table 3-18 in [1], Table 3-18 in [2] */
/* RCSR bits - see Table 3-18 in [1], Table 3-18 in [2], Table 3-19 in [3] */
#define RCSR_GPR bit(3)
#define RCSR_SMR bit(2)

24
include/arm/pxa2x0/pwm.h
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@ -1,8 +1,8 @@
/*
* $Id$
*
* XScale PXA26x/PXA250/PXA210 PWM0 and PWM1 Registers
* Copyright (C) 2002 ETC s.r.o.
* XScale PXA26x/PXA255/PXA250/PXA210 PWM0 and PWM1 Registers
* Copyright (C) 2002, 2003 ETC s.r.o.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -28,13 +28,15 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
*
* Documentation:
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
* Developer's Manual", February 2002, Order Number: 278522-001
* [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
* October 2002, Order Number: 278638-001
* March 2003, Order Number: 278638-002
* [3] Intel Corporation, "Intel PXA255 Processor Developer's Manual"
* March 2003, Order Number: 278693-001
*
*/
@ -47,6 +49,14 @@
#include <stdint.h>
#endif
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255)
#define PXA2X0_NOPXA255
#endif
#if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260)
#define PXA2X0_NOPXA260
#endif
/* PWM0 and PWM1 Registers */
#define PWM0_BASE 0x40B00000
@ -81,21 +91,21 @@ typedef volatile struct PWM_registers {
#define PWM_PWDUTY_OFFSET 0x04
#define PWM_PERVAL_OFFSET 0x08
/* PWM_CTRL bits - see Table 4-49 in [1], Table 4-50 in [2] */
/* PWM_CTRL bits - see Table 4-49 in [1], Table 4-50 in [2], Table 4-46 in [3] */
#define PWM_CTRL_PWM_SD bit(6)
#define PWM_CTRL_PRESCALE_MASK bits(5,0)
#define PWM_CTRL_PRESCALE(x) bits_val(5,0,x)
#define get_PWM_CTRL_PRESCALE(x) bits_get(5,0,x)
/* PWM_PWDUTY bits - see Table 4-50 in [1], Table 4-51 in [2] */
/* PWM_PWDUTY bits - see Table 4-50 in [1], Table 4-51 in [2], Table 4-47 in [3] */
#define PWM_PWDUTY_FDCYCLE bit(10)
#define PWM_PWDUTY_DCYCLE_MASK bits(9,0)
#define PWM_PWDUTY_DCYCLE(x) bits_val(9,0,x)
#define get_PWM_PWDUTY_DCYCLE(x) bits_get(9,0,x)
/* PWM_PERVAL bits - see Table 4-51 in [1], Table 4-52 in [2] */
/* PWM_PERVAL bits - see Table 4-51 in [1], Table 4-52 in [2], Table 4-48 in [3] */
#define PWM_PERVAL_PV_MASK bits(9,0)
#define PWM_PERVAL_PV(x) bits_val(9,0,x)

22
include/arm/pxa2x0/rtc.h
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@ -1,8 +1,8 @@
/*
* $Id$
*
* XScale PXA26x/PXA250/PXA210 RTC Registers
* Copyright (C) 2002 ETC s.r.o.
* XScale PXA26x/PXA255/PXA250/PXA210 RTC Registers
* Copyright (C) 2002, 2003 ETC s.r.o.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -28,13 +28,15 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
*
* Documentation:
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
* Developer's Manual", February 2002, Order Number: 278522-001
* [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
* October 2002, Order Number: 278638-001
* March 2003, Order Number: 278638-002
* [3] Intel Corporation, "Intel PXA255 Processor Developer's Manual"
* March 2003, Order Number: 278693-001
*
*/
@ -47,6 +49,14 @@
#include <stdint.h>
#endif
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255)
#define PXA2X0_NOPXA255
#endif
#if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260)
#define PXA2X0_NOPXA260
#endif
/* RTC Registers */
#define RTC_BASE 0x40900000
@ -74,14 +84,14 @@ typedef volatile struct RTC_registers {
#define RTSR_OFFSET 0x08
#define RTTR_OFFSET 0x0C
/* RTSR bits - see Table 4-42 in [1], Table 4-42 in [2] */
/* RTSR bits - see Table 4-42 in [1], Table 4-42 in [2], Table 4-40 in [3] */
#define RTSR_HZE bit(3)
#define RTSR_ALE bit(2)
#define RTSR_HZ bit(1)
#define RTSR_AL bit(0)
/* RTTR bits - see Table 4-39 in [1], Table 4-39 in [2] */
/* RTTR bits - see Table 4-39 in [1], Table 4-39 in [2], Table 4-37 in [3] */
#define RTTR_LCK bit(31)
#define RTTR_DEL_MASK bits(25,16)

128
include/arm/pxa2x0/ssp.h
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@ -1,8 +1,8 @@
/*
* $Id$
*
* XScale PXA26x/PXA250/PXA210 SSP/NSSP/ASSP Registers
* Copyright (C) 2002 ETC s.r.o.
* XScale PXA26x/PXA255/PXA250/PXA210 SSP/NSSP/ASSP Registers
* Copyright (C) 2002, 2003 ETC s.r.o.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -28,13 +28,15 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
*
* Documentation:
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
* Developer's Manual", February 2002, Order Number: 278522-001
* [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
* October 2002, Order Number: 278638-001
* March 2003, Order Number: 278638-002
* [3] Intel Corporation, "Intel PXA255 Processor Developer's Manual"
* March 2003, Order Number: 278693-001
*
*/
@ -47,43 +49,51 @@
#include <stdint.h>
#endif
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA26X)
#define PXA2X0_NOPXA26X
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255)
#define PXA2X0_NOPXA255
#endif
#if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260)
#define PXA2X0_NOPXA260
#endif
/* SSP Registers */
#define SSP_BASE 0x41000000
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define NSSP_BASE 0x41400000
#endif /* PXA255 and above only */
#if !defined(PXA2X0_NOPXA260)
#define ASSP_BASE 0x41500000
#endif /* PXA26x only */
#endif /* PXA260 and above only */
#if LANGUAGE == C
/* see Table 8-7 in [1], Table 8-7 in [2], Table 16-10 in [2], Table 16-11 in [2] */
/* see Table 8-7 in [1], Table 8-7 in [2], Table 16-10 in [2], Table 16-11 in [2], Table 8-7 in [3], Table 16-10 in [3] */
typedef volatile struct SSP_registers {
uint32_t sscr0;
uint32_t sscr1;
uint32_t sssr;
#if defined(PXA2X0_NOPXA26X)
#if defined(PXA2X0_NOPXA255)
uint32_t __reserved;
#else /* PXA26x only */
#else /* PXA255 and above only */
uint32_t xssitr; /* only for NSSP/ASSP */
#endif /* PXA26x only */
#endif /* PXA255 and above only */
uint32_t ssdr;
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
uint32_t __reserved[5];
uint32_t xssto; /* only for NSSP/ASSP */
uint32_t xsspsp; /* only for NSSP/ASSP */
#endif /* PXA26x only */
#endif /* PXA255 and above only */
} SSP_registers_t;
#ifdef PXA2X0_UNMAPPED
#define SSP_pointer ((SSP_registers_t*) SSP_BASE)
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define NSSP_pointer ((SSP_registers_t*) NSSP_BASE)
#endif /* PXA255 and above only */
#if !defined(PXA2X0_NOPXA260)
#define ASSP_pointer ((SSP_registers_t*) ASSP_BASE)
#endif /* PXA26x only */
#endif /* PXA260 and above only */
#endif
#define SSCR0 SSP_pointer->sscr0
@ -91,7 +101,7 @@ typedef volatile struct SSP_registers {
#define SSSR SSP_pointer->sssr
#define SSDR SSP_pointer->ssdr
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define NSSCR0 NSSP_pointer->sscr0
#define NSSCR1 NSSP_pointer->sscr1
#define NSSSR NSSP_pointer->sssr
@ -99,7 +109,9 @@ typedef volatile struct SSP_registers {
#define NSSDR NSSP_pointer->ssdr
#define NSSPTO NSSP_pointer->xsspto
#define NSSPSP NSSP_pointer->xsspsp
#endif /* PXA255 and above only */
#if !defined(PXA2X0_NOPXA260)
#define ASSCR0 ASSP_pointer->sscr0
#define ASSCR1 ASSP_pointer->sscr1
#define ASSSR ASSP_pointer->sssr
@ -107,7 +119,9 @@ typedef volatile struct SSP_registers {
#define ASSDR ASSP_pointer->ssdr
#define ASSPTO ASSP_pointer->xsspto
#define ASSPSP ASSP_pointer->xsspsp
#endif /* PXA260 and above only */
#if !defined(PXA2X0_NOPXA255)
/* common for NSSP/ASSP */
#define XSSCR0 XSSP_pointer->sscr0
@ -117,7 +131,7 @@ typedef volatile struct SSP_registers {
#define XSSDR XSSP_pointer->ssdr
#define XSSPTO XSSP_pointer->xsspto
#define XSSPSP XSSP_pointer->xsspsp
#endif /* PXA26x only */
#endif /* PXA255 and above only */
#endif /* LANGUAGE == C */
#define SSCR0_OFFSET 0x00
@ -125,7 +139,7 @@ typedef volatile struct SSP_registers {
#define SSSR_OFFSET 0x08
#define SSDR_OFFSET 0x10
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define NSSCR0_OFFSET 0x00
#define NSSCR1_OFFSET 0x04
#define NSSSR_OFFSET 0x08
@ -133,7 +147,9 @@ typedef volatile struct SSP_registers {
#define NSSDR_OFFSET 0x10
#define NSSTO_OFFSET 0x28
#define NSSPSP_OFFSET 0x2C
#endif /* PXA255 and above only */
#if !defined(PXA2X0_NOPXA260)
#define ASSCR0_OFFSET 0x00
#define ASSCR1_OFFSET 0x04
#define ASSSR_OFFSET 0x08
@ -141,7 +157,9 @@ typedef volatile struct SSP_registers {
#define ASSDR_OFFSET 0x10
#define ASSTO_OFFSET 0x28
#define ASSPSP_OFFSET 0x2C
#endif /* PXA260 and above only */
#if !defined(PXA2X0_NOPXA255)
/* common for NSSP/ASSP */
#define XSSCR0_OFFSET 0x00
@ -151,9 +169,9 @@ typedef volatile struct SSP_registers {
#define XSSDR_OFFSET 0x10
#define XSSTO_OFFSET 0x28
#define XSSPSP_OFFSET 0x2C
#endif /* PXA26x only */
#endif /* PXA255 and above only */
/* SSCR0 bits - see Table 8-2 in [1], Table 8-2 in [2] */
/* SSCR0 bits - see Table 8-2 in [1], Table 8-2 in [2], Table 8-2 in [3] */
#define SSCR0_SCR_MASK bits(15,8)
#define SSCR0_SCR(x) bits_val(15,8,x)
@ -167,7 +185,7 @@ typedef volatile struct SSP_registers {
#define SSCR0_DSS(x) bits_val(3,0,x)
#define get_SSCR0_DSS(x) bits_get(3,0,x)
/* SSCR1 bits - see Table 8-3 in [1], Table 8-3 in [2] */
/* SSCR1 bits - see Table 8-3 in [1], Table 8-3 in [2], Table 8-3 in [3] */
#define SSCR1_RFT_MASK bits(13,10)
#define SSCR1_RFT(x) bits_val(13,10,x)
@ -182,7 +200,7 @@ typedef volatile struct SSP_registers {
#define SSCR1_TIE bit(1)
#define SSCR1_RIE bit(0)
/* SSSR bits - see Table 8-6 in [1], Table 8-6 in [2] */
/* SSSR bits - see Table 8-6 in [1], Table 8-6 in [2], Table 8-6 in [3] */
#define SSSR_RFL_MASK bits(15,12)
#define SSSR_RFL(x) bits_val(15,12,x)
@ -197,8 +215,8 @@ typedef volatile struct SSP_registers {
#define SSSR_RNE bit(3)
#define SSSR_TNF bit(2)
#if !defined(PXA2X0_NOPXA26X)
/* NSSCR0/ASSCR0 bits - see Table 16-3 in [2] */
#if !defined(PXA2X0_NOPXA255)
/* NSSCR0 bits - see Table 16-3 in [2], Table 16-3 in [3] */
#define NSSCR0_EDSS bit(20)
#define NSSCR0_SCR_MASK bits(19,8)
@ -211,6 +229,10 @@ typedef volatile struct SSP_registers {
#define NSSCR0_DSS_MASK bits(3,0)
#define NSSCR0_DSS(x) bits_val(3,0,x)
#define get_NSSCR0_DSS(x) bits_get(3,0,x)
#endif /* PXA255 and above only */
#if !defined(PXA2X0_NOPXA260)
/* ASSCR0 bits - see Table 16-3 in [2] */
#define ASSCR0_EDSS bit(20)
#define ASSCR0_SCR_MASK bits(19,8)
@ -223,6 +245,10 @@ typedef volatile struct SSP_registers {
#define ASSCR0_DSS_MASK bits(3,0)
#define ASSCR0_DSS(x) bits_val(3,0,x)
#define get_ASSCR0_DSS(x) bits_get(3,0,x)
#endif /* PXA260 and above only */
#if !defined(PXA2X0_NOPXA255)
/* NSSCR0/ASSCR0 bits - see Table 16-3 in [2], Table 16-3 in [3] */
#define XSSCR0_EDSS bit(20)
#define XSSCR0_SCR_MASK bits(19,8)
@ -236,7 +262,7 @@ typedef volatile struct SSP_registers {
#define XSSCR0_DSS(x) bits_val(3,0,x)
#define get_XSSCR0_DSS(x) bits_get(3,0,x)
/* NSSCR1/ASSCR1 bits - see Table 16-4 in [2] */
/* NSSCR1 bits - see Table 16-4 in [2], Table 16-4 in [3] */
#define NSSCR1_TTELP bit(31)
#define NSSCR1_TTE bit(30)
@ -262,6 +288,10 @@ typedef volatile struct SSP_registers {
#define NSSCR1_LBM bit(2)
#define NSSCR1_TIE bit(1)
#define NSSCR1_RIE bit(0)
#endif /* PXA255 and above only */
#if !defined(PXA2X0_NOPXA260)
/* ASSCR1 bits - see Table 16-4 in [2] */
#define ASSCR1_TTELP bit(31)
#define ASSCR1_TTE bit(30)
@ -287,6 +317,10 @@ typedef volatile struct SSP_registers {
#define ASSCR1_LBM bit(2)
#define ASSCR1_TIE bit(1)
#define ASSCR1_RIE bit(0)
#endif /* PXA260 and above only */
#if !defined(PXA2X0_NOPXA255)
/* NSSCR1/ASSCR1 bits - see Table 16-4 in [2], Table 16-4 in [3] */
#define XSSCR1_TTELP bit(31)
#define XSSCR1_TTE bit(30)
@ -313,21 +347,29 @@ typedef volatile struct SSP_registers {
#define XSSCR1_TIE bit(1)
#define XSSCR1_RIE bit(0)
/* NSSITR/ASSITR bits - see Table 16-7 in [2] */
/* NSSITR bits - see Table 16-7 in [2], Table 16-7 in [3] */
#define NSSITR_TROR bit(7)
#define NSSITR_TRFS bit(6)
#define NSSITR_TTFS bit(5)
#endif /* PXA255 and above only */
#if !defined(PXA2X0_NOPXA260)
/* ASSITR bits - see Table 16-7 in [2] */
#define ASSITR_TROR bit(7)
#define ASSITR_TRFS bit(6)
#define ASSITR_TTFS bit(5)
#endif /* PXA260 and above only */
#if !defined(PXA2X0_NOPXA255)
/* NSSITR/ASSITR bits - see Table 16-7 in [2], Table 16-7 in [3] */
#define XSSITR_TROR bit(7)
#define XSSITR_TRFS bit(6)
#define XSSITR_TTFS bit(5)
/* NSSSR/ASSSR bits - see Table 16-8 in [2] */
/* NSSSR bits - see Table 16-8 in [2], Table 16-8 in [3] */
#define NSSSR_BCE bit(23)
#define NSSSR_CSS bit(22)
@ -345,6 +387,10 @@ typedef volatile struct SSP_registers {
#define NSSSR_BSY bit(4)
#define NSSSR_RNE bit(3)
#define NSSSR_TNF bit(2)
#endif /* PXA255 and above only */
#if !defined(PXA2X0_NOPXA260)
/* ASSSR bits - see Table 16-8 in [2] */
#define ASSSR_BCE bit(23)
#define ASSSR_CSS bit(22)
@ -362,6 +408,10 @@ typedef volatile struct SSP_registers {
#define ASSSR_BSY bit(4)
#define ASSSR_RNE bit(3)
#define ASSSR_TNF bit(2)
#endif /* PXA260 and above only */
#if !defined(PXA2X0_NOPXA255)
/* NSSSR/ASSSR bits - see Table 16-8 in [2], Table 16-8 in [3] */
#define XSSSR_BCE bit(23)
#define XSSSR_CSS bit(22)
@ -380,21 +430,29 @@ typedef volatile struct SSP_registers {
#define XSSSR_RNE bit(3)
#define XSSSR_TNF bit(2)
/* NSSTO/ASSTO bits - see Table 16-6 in [2] */
/* NSSTO bits - see Table 16-6 in [2], Table 16-6 in [3] */
#define NSSTO_TIMEOUT_MASK bits(23,0)
#define NSSTO_TIMEOUT(x) bits_val(23,0,x)
#define get_NSSTO_TIMEOUT(x) bits_get(23,0,x)
#endif /* PXA255 and above only */
#if !defined(PXA2X0_NOPXA260)
/* ASSTO bits - see Table 16-6 in [2] */
#define ASSTO_TIMEOUT_MASK bits(23,0)
#define ASSTO_TIMEOUT(x) bits_val(23,0,x)
#define get_ASSTO_TIMEOUT(x) bits_get(23,0,x)
#endif /* PXA260 and above only */
#if !defined(PXA2X0_NOPXA255)
/* NSSTO/ASSTO bits - see Table 16-6 in [2], Table 16-6 in [3] */
#define XSSTO_TIMEOUT_MASK bits(23,0)
#define XSSTO_TIMEOUT(x) bits_val(23,0,x)
#define get_XSSTO_TIMEOUT(x) bits_get(23,0,x)
/* NSSPSP/ASSPSP bits - see Table 16-5 in [2] */
/* NSSPSP bits - see Table 16-5 in [2], Table 16-5 in [3] */
#define NSSPSP_DMYSTOP_MASK bits(24,23)
#define NSSPSP_DMYSTOP(x) bits_val(24,23,x)
@ -416,6 +474,10 @@ typedef volatile struct SSP_registers {
#define NSSPSP_SCMODE_MASK bits(1,0)
#define NSSPSP_SCMODE(x) bits_val(1,0,x)
#define get_NSSPSP_SCMODE(x) bits_get(1,0,x)
#endif /* PXA255 and above only */
#if !defined(PXA2X0_NOPXA260)
/* ASSPSP bits - see Table 16-5 in [2] */
#define ASSPSP_DMYSTOP_MASK bits(24,23)
#define ASSPSP_DMYSTOP(x) bits_val(24,23,x)
@ -437,6 +499,10 @@ typedef volatile struct SSP_registers {
#define ASSPSP_SCMODE_MASK bits(1,0)
#define ASSPSP_SCMODE(x) bits_val(1,0,x)
#define get_ASSPSP_SCMODE(x) bits_get(1,0,x)
#endif /* PXA260 and above only */
#if !defined(PXA2X0_NOPXA255)
/* NSSPSP/ASSPSP bits - see Table 16-5 in [2], Table 16-5 in [3] */
#define XSSPSP_DMYSTOP_MASK bits(24,23)
#define XSSPSP_DMYSTOP(x) bits_val(24,23,x)
@ -458,6 +524,6 @@ typedef volatile struct SSP_registers {
#define XSSPSP_SCMODE_MASK bits(1,0)
#define XSSPSP_SCMODE(x) bits_val(1,0,x)
#define get_XSSPSP_SCMODE(x) bits_get(1,0,x)
#endif /* PXA26x only */
#endif /* PXA255 and above only */
#endif /* PXA2X0_SSP_H */

88
include/arm/pxa2x0/uart.h
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@ -1,8 +1,8 @@
/*
* $Id$
*
* XScale PXA26x/PXA250/PXA210 UART (FFUART/BTUART/STUART/HWUART) Declarations
* Copyright (C) 2002 ETC s.r.o.
* XScale PXA26x/PXA255/PXA250/PXA210 UART (FFUART/BTUART/STUART/HWUART) Declarations
* Copyright (C) 2002, 2003 ETC s.r.o.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -28,13 +28,15 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
*
* Documentation:
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
* Developer's Manual", February 2002, Order Number: 278522-001
* [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
* October 2002, Order Number: 278638-001
* March 2003, Order Number: 278638-002
* [3] Intel Corporation, "Intel PXA255 Processor Developer's Manual"
* March 2003, Order Number: 278693-001
*
*/
@ -47,8 +49,12 @@
#include <stdint.h>
#endif
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA26X)
#define PXA2X0_NOPXA26X
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255)
#define PXA2X0_NOPXA255
#endif
#if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260)
#define PXA2X0_NOPXA260
#endif
/* Common UART (FFUART/BTUART/STUART/HWUART) Declarations */
@ -56,9 +62,9 @@
#define FFUART_BASE 0x40100000
#define BTUART_BASE 0x40200000
#define STUART_BASE 0x40700000
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define HWUART_BASE 0x41600000
#endif /* PXA26x only */
#endif /* PXA255 and above only */
#if LANGUAGE == C
typedef volatile struct UART_registers {
@ -81,20 +87,20 @@ typedef volatile struct UART_registers {
uint32_t msr; /* only for FFUART, BTUART, HWUART */
uint32_t spr;
uint32_t isr;
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
uint32_t hwfor; /* only for HWUART */
uint32_t hwabr; /* only for HWUART */
uint32_t hwacr; /* only for HWUART */
#endif /* PXA26x only */
#endif /* PXA255 and above only */
} UART_registers_t;
#ifdef PXA2X0_UNMAPPED
#define FFUART_pointer ((UART_registers_t*) FFUART_BASE)
#define BTUART_pointer ((UART_registers_t*) BTUART_BASE)
#define STUART_pointer ((UART_registers_t*) STUART_BASE)
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define HWUART_pointer ((UART_registers_t*) HWUART_BASE)
#endif /* PXA26x only */
#endif /* PXA255 and above only */
#endif
#define RBR UART_pointer->rbr
@ -158,7 +164,7 @@ typedef volatile struct UART_registers {
#define STDLL STUART_pointer->dll
#define STDLH STUART_pointer->dlh
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
/* HWUART */
#define HWRBR HWUART_pointer->rbr
@ -177,7 +183,7 @@ typedef volatile struct UART_registers {
#define HWACR HWUART_pointer->hwacr
#define HWDLL HWUART_pointer->dll
#define HWDLH HWUART_pointer->dlh
#endif /* PXA26x only */
#endif /* PXA255 and above only */
#endif /* LANGUAGE == C */
#define RBR_OFFSET 0x00
@ -191,15 +197,15 @@ typedef volatile struct UART_registers {
#define MSR_OFFSET 0x18
#define SPR_OFFSET 0x1C
#define ISR_OFFSET 0x20
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define HWFOR_OFFSET 0x24 /* only for HWUART */
#define HWABR_OFFSET 0x28 /* only for HWUART */
#define HWACR_OFFSET 0x2C /* only for HWUART */
#endif /* PXA26x only */
#endif /* PXA255 and above only */
#define DLL_OFFSET 0x00
#define DLH_OFFSET 0x04
/* IER bits - see Table 10-7 in [1], Table 10-7 in [2], Table 17-6 in [2] */
/* IER bits - see Table 10-7 in [1], Table 10-7 in [2], Table 17-6 in [2], Table 10-7 in [3], Table 17-6 in [3] */
#define IER_DMAE bit(7)
#define IER_UUE bit(6)
@ -210,33 +216,33 @@ typedef volatile struct UART_registers {
#define IER_TIE bit(1)
#define IER_RAVIE bit(0)
/* IIR bits - see Table 10-9 in [1], Table 10-9 in [2], Table 17-8 in [2] */
/* IIR bits - see Table 10-9 in [1], Table 10-9 in [2], Table 17-8 in [2], Table 10-9 in [3], Table 17-8 in [3] */
#define IIR_FIFOES_MASK bits(7,6)
#define IIR_FIFOES(x) bits_val(7,6,x)
#define get_IIR_FIFOES(x) bits_get(7,6,x)
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define IIR_ABL bit(4) /* only for HWUART */
#endif /* PXA26x only */
#endif /* PXA255 and above only */
#define IIR_TOD bit(3)
#define IIR_IID_MASK bits(2,1)
#define IIR_IID(x) bits_val(2,1,x)
#define get_IIR_IID(x) bits_get(2,1,x)
#define IIR_IP bit(0)
/* FCR bits - see Table 10-11 in [1], Table 10-11 in [2], Table 17-10 in [2] */
/* FCR bits - see Table 10-11 in [1], Table 10-11 in [2], Table 17-10 in [2], Table 10-11 in [3], Table 17-10 in [3] */
#define FCR_ITL_MASK bits(7,6)
#define FCR_ITL(x) bits_val(7,6,x)
#define get_FCR_ITL(x) bits_get(7,6,x)
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define FCR_TIL bit(3) /* only for HWUART */
#endif /* PXA26x only */
#endif /* PXA255 and above only */
#define FCR_RESETTF bit(2)
#define FCR_RESETRF bit(1)
#define FCR_TRFIFOE bit(0)
/* LCR bits - see Table 10-12 in [1], Table 10-12 in [2], Table 17-14 in [2] */
/* LCR bits - see Table 10-12 in [1], Table 10-12 in [2], Table 17-14 in [2], Table 10-12 in [3], Table 17-14 in [3] */
#define LCR_DLAB bit(7)
#define LCR_SB bit(6)
@ -248,7 +254,7 @@ typedef volatile struct UART_registers {
#define LCR_WLS(x) bits_val(1,0,x)
#define get_LCR_WLS(x) bits_get(1,0,x)
/* LSR bits - see Table 10-13 in [1], Table 10-13 in [2], Table 17-15 in [2] */
/* LSR bits - see Table 10-13 in [1], Table 10-13 in [2], Table 17-15 in [2], Table 10-13 in [3], Table 17-15 in [3] */
#define LSR_FIFOE bit(7)
#define LSR_TEMT bit(6)
@ -259,35 +265,35 @@ typedef volatile struct UART_registers {
#define LSR_OE bit(1)
#define LSR_DR bit(0)
/* MCR bits - see Table 10-14 in [1], Table 10-14 in [2], Table 17-16 in [2] */
/* MCR bits - see Table 10-14 in [1], Table 10-14 in [2], Table 17-16 in [2], Table 10-14 in [3], Table 17-16 in [3] */
#if !defined(PXA2X0_NOPXA26X)
#if !defined(PXA2X0_NOPXA255)
#define MCR_AFE bit(5) /* only for HWUART */
#endif /* PXA26x only */
#endif /* PXA255 and above only */
#define MCR_LOOP bit(4)
#define MCR_OUT2 bit(3)
#define MCR_OUT1 bit(2) /* only for FFUART - see Table 10-21 in [1], Table 10-21 in [2] */
#define MCR_RTS bit(1) /* only for FFUART, BTUART, HWUART - see Table 10-21 in [1], Table 10-21 in [2] */
#define MCR_DTR bit(0) /* only for FFUART - see Table 10-21 in [1], Table 10-21 in [2] */
#define MCR_OUT1 bit(2) /* only for FFUART - see Table 10-21 in [1], Table 10-21 in [2], Table 10-21 in [3] */
#define MCR_RTS bit(1) /* only for FFUART, BTUART, HWUART - see Table 10-21 in [1], Table 10-21 in [2], Table 10-21 in [3] */
#define MCR_DTR bit(0) /* only for FFUART - see Table 10-21 in [1], Table 10-21 in [2], Table 10-21 in [3] */
/* MSR bits - see Table 10-15 in [1], Table 10-15 in [2], Table 17-17 in [2] */
/* MSR bits - see Table 10-15 in [1], Table 10-15 in [2], Table 17-17 in [2], Table 10-15 in [3], Table 17-17 in [3] */
#define MSR_DCD bit(7) /* only for FFUART */
#define MSR_RI bit(6) /* only for FFUART */
#define MSR_DSR bit(5) /* only for FFUART */
#define MSR_CTS bit(4) /* only for FFUART, BTUART, HWUART - see Table 10-21 in [1], Table 10-21 in [2] */
#define MSR_CTS bit(4) /* only for FFUART, BTUART, HWUART - see Table 10-21 in [1], Table 10-21 in [2], Table 10-21 in [3] */
#define MSR_DDCD bit(3) /* only for FFUART */
#define MSR_TERI bit(2) /* only for FFUART */
#define MSR_DDSR bit(1) /* only for FFUART */
#define MSR_DCTS bit(0) /* only for FFUART, BTUART, HWUART - see Table 10-21 in [1], Table 10-21 in [2] */
#define MSR_DCTS bit(0) /* only for FFUART, BTUART, HWUART - see Table 10-21 in [1], Table 10-21 in [2], Table 10-21 in [3] */
/* SPR bits - see Table 10-16 in [1], Table 10-16 in [2], Table 17-18 in [2] */
/* SPR bits - see Table 10-16 in [1], Table 10-16 in [2], Table 17-18 in [2], Table 10-16 in [3], Table 17-18 in [3] */
#define SPR_SP_MASK bits(7,0)
#define SPR_SP(x) bits_val(7,0,x)
#define get_SPR_SP(x) bits_get(7,0,x)
/* ISR bits - see Table 10-17 in [1], Table 10-17 in [2], Table 17-19 in [2] */
/* ISR bits - see Table 10-17 in [1], Table 10-17 in [2], Table 17-19 in [2], Table 10-17 in [3], Table 17-19 in [3] */
#define ISR_RXPL bit(4)
#define ISR_TXPL bit(3)
@ -295,25 +301,25 @@ typedef volatile struct UART_registers {
#define ISR_RCVEIR bit(1)
#define ISR_XMITIR bit(0)
#if !defined(PXA2X0_NOPXA26X)
/* HWFOR bits - see Table 17-11 in [2] */
#if !defined(PXA2X0_NOPXA255)
/* HWFOR bits - see Table 17-11 in [2], Table 17-11 in [3] */
#define HWFOR_BC_MASK bits(6,0)
#define HWFOR_BC(x) bits_val(6,0,x)
#define get_HWFOR_BC(x) bits_get(6,0,x)
/* HWABR bits - see Table 17-12 in [2] */
/* HWABR bits - see Table 17-12 in [2], Table 17-12 in [3] */
#define HWABR_ABT bit(3)
#define HWABR_ABUP bit(2)
#define HWABR_ABLIE bit(1)
#define HWABR_ABE bit(0)
/* HWACR bits - see Table 17-13 in [2] */
/* HWACR bits - see Table 17-13 in [2], Table 17-13 in [3] */
#define HWACR_ACR_MASK bits(15,0)
#define HWACR_ACR(x) bits_val(15,0,x)
#define get_HWACR_ACR(x) bits_get(15,0,x)
#endif /* PXA26x only */
#endif /* PXA255 and above only */
#endif /* PXA2X0_UART_H */

118
include/arm/pxa2x0/udc.h
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@ -1,8 +1,8 @@
/*
* $Id$
*
* XScale PXA26x/PXA250/PXA210 UDC Registers
* Copyright (C) 2002 ETC s.r.o.
* XScale PXA26x/PXA255/PXA250/PXA210 UDC Registers
* Copyright (C) 2002, 2003 ETC s.r.o.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -28,13 +28,15 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
* Written by Marcel Telka <marcel@telka.sk>, 2002, 2003.
*
* Documentation:
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
* Developer's Manual", February 2002, Order Number: 278522-001
* [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual",
* October 2002, Order Number: 278638-001
* March 2003, Order Number: 278638-002
* [3] Intel Corporation, "Intel PXA255 Processor Developer's Manual"
* March 2003, Order Number: 278693-001
*
*/
@ -47,6 +49,14 @@
#include <stdint.h>
#endif
#if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255)
#define PXA2X0_NOPXA255
#endif
#if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260)
#define PXA2X0_NOPXA260
#endif
/* UDC Registers */
#define UDC_BASE 0x40600000
@ -54,7 +64,13 @@
#if LANGUAGE == C
typedef volatile struct UDC_registers {
uint32_t udccr;
uint32_t __reserved1[3];
uint32_t __reserved1;
#if !defined(PXA2X0_NOPXA255)
uint32_t udccfr;
#else /* PXA255 and above only */
uint32_t __reserved2;
#endif
uint32_t __reserved3;
uint32_t udccs[16];
uint32_t uicr0;
uint32_t uicr1;
@ -69,35 +85,35 @@ typedef volatile struct UDC_registers {
uint32_t ubcr12;
uint32_t ubcr14;
uint32_t uddr0;
uint32_t __reserved2[7];
uint32_t __reserved4[7];
uint32_t uddr5;
uint32_t __reserved3[7];
uint32_t __reserved5[7];
uint32_t uddr10;
uint32_t __reserved4[7];
uint32_t __reserved6[7];
uint32_t uddr15;
uint32_t __reserved5[7];
uint32_t __reserved7[7];
uint32_t uddr1;
uint32_t __reserved6[31];
uint32_t __reserved8[31];
uint32_t uddr2;
uint32_t __reserved7[31];
uint32_t __reserved9[31];
uint32_t uddr3;
uint32_t __reserved8[127];
uint32_t __reserved10[127];
uint32_t uddr4;
uint32_t __reserved9[127];
uint32_t __reserved11[127];
uint32_t uddr6;
uint32_t __reserved10[31];
uint32_t __reserved12[31];
uint32_t uddr7;
uint32_t __reserved11[31];
uint32_t __reserved13[31];
uint32_t uddr8;
uint32_t __reserved12[127];
uint32_t __reserved14[127];
uint32_t uddr9;
uint32_t __reserved13[127];
uint32_t __reserved15[127];
uint32_t uddr11;
uint32_t __reserved14[31];
uint32_t __reserved16[31];
uint32_t uddr12;
uint32_t __reserved15[31];
uint32_t __reserved17[31];
uint32_t uddr13;
uint32_t __reserved16[127];
uint32_t __reserved18[127];
uint32_t uddr14;
} UDC_registers_t;
@ -106,6 +122,9 @@ typedef volatile struct UDC_registers {
#endif
#define UDCCR UDC_pointer->udccr
#if !defined(PXA2X0_NOPXA255)
#define UDCCFR UDC_pointer->udccfr
#endif /* PXA255 and above only */
#define UDCCS(i) UDC_pointer->udccs[i]
#define UDCCS0 UDCCS(0)
#define UDCCS1 UDCCS(1)
@ -154,6 +173,9 @@ typedef volatile struct UDC_registers {
#endif /* LANGUAGE == C */
#define UDCCR_OFFSET 0x000
#if !defined(PXA2X0_NOPXA255)
#define UDCCFR_OFFSET 0x008
#endif /* PXA255 and above only */
#define UDCCS_OFFSET(i) (0x010 + ((i) << 2))
#define UDCCS0_OFFSET UDCCS_OFFSET(0)
#define UDCCS1_OFFSET UDCCS_OFFSET(1)
@ -200,7 +222,7 @@ typedef volatile struct UDC_registers {
#define USIR0_OFFSET 0x058
#define USIR1_OFFSET 0x05C
/* UDCCR bits - see Table 12-20 in [1], Table 12-12 in [2] */
/* UDCCR bits - see Table 12-20 in [1], Table 12-12 in [2], Table 12-12 in [3] */
#define UDCCR_REM bit(7)
#define UDCCR_RSTIR bit(6)
@ -211,7 +233,13 @@ typedef volatile struct UDC_registers {
#define UDCCR_UDA bit(1)
#define UDCCR_UDE bit(0)
/* UDCCS0 bits - see Table 12-21 in [1], Table 12-13 in [2] */
#if !defined(PXA2X0_NOPXA255)
/* UDCCFR bits - see Table 12-13 in [3] */
#define UDCCFR_AREN bit(7)
#define UDCCFR_ACM bit(2)
#endif /* PXA255 and above only */
/* UDCCS0 bits - see Table 12-21 in [1], Table 12-13 in [2], Table 12-14 in [3] */
#define UDCCS0_SA bit(7)
#define UDCCS0_RNE bit(6)
@ -222,7 +250,7 @@ typedef volatile struct UDC_registers {
#define UDCCS0_IPR bit(1)
#define UDCCS0_OPR bit(0)
/* UDCCS1 bits - see Table 12-22 in [1], Table 12-14 in [2] */
/* UDCCS1 bits - see Table 12-22 in [1], Table 12-14 in [2], Table 12-15 in [3] */
#define UDCCS1_TSP bit(7)
#define UDCCS1_FST bit(5)
@ -232,7 +260,7 @@ typedef volatile struct UDC_registers {
#define UDCCS1_TPC bit(1)
#define UDCCS1_TFS bit(0)
/* UDCCS2 bits - see Table 12-23 in [1], Table 12-15 in [2] */
/* UDCCS2 bits - see Table 12-23 in [1], Table 12-15 in [2], Table 12-16 in [3] */
#define UDCCS2_RSP bit(7)
#define UDCCS2_RNE bit(6)
@ -242,7 +270,7 @@ typedef volatile struct UDC_registers {
#define UDCCS2_RPC bit(1)
#define UDCCS2_RFS bit(0)
/* UDCCS3 bits - see Table 12-24 in [1], Table 12-16 in [2] */
/* UDCCS3 bits - see Table 12-24 in [1], Table 12-16 in [2], Table 12-17 in [3] */
#define UDCCS3_TSP bit(7)
#define UDCCS3_TUR bit(3)
@ -250,7 +278,7 @@ typedef volatile struct UDC_registers {
#define UDCCS3_TPC bit(1)
#define UDCCS3_TFS bit(0)
/* UDCCS4 bits - see Table 12-25 in [1], Table 12-17 in [2] */
/* UDCCS4 bits - see Table 12-25 in [1], Table 12-17 in [2], Table 12-18 in [3] */
#define UDCCS4_RSP bit(7)
#define UDCCS4_RNE bit(6)
@ -259,7 +287,7 @@ typedef volatile struct UDC_registers {
#define UDCCS4_RPC bit(1)
#define UDCCS4_RFS bit(0)
/* UDCCS5 bits - see Table 12-26 in [1], Table 12-18 in [2] */
/* UDCCS5 bits - see Table 12-26 in [1], Table 12-18 in [2], Table 12-19 in [3] */
#define UDCCS5_TSP bit(7)
#define UDCCS5_FST bit(5)
@ -269,7 +297,7 @@ typedef volatile struct UDC_registers {
#define UDCCS5_TPC bit(1)
#define UDCCS5_TFS bit(0)
/* UDCCS6 bits - see Table 12-22 in [1], Table 12-14 in [2] */
/* UDCCS6 bits - see Table 12-22 in [1], Table 12-14 in [2], Table 12-15 in [3] */
#define UDCCS6_TSP bit(7)
#define UDCCS6_FST bit(5)
@ -279,7 +307,7 @@ typedef volatile struct UDC_registers {
#define UDCCS6_TPC bit(1)
#define UDCCS6_TFS bit(0)
/* UDCCS7 bits - see Table 12-23 in [1], Table 12-15 in [2] */
/* UDCCS7 bits - see Table 12-23 in [1], Table 12-15 in [2], Table 12-16 in [3] */
#define UDCCS7_RSP bit(7)
#define UDCCS7_RNE bit(6)
@ -289,7 +317,7 @@ typedef volatile struct UDC_registers {
#define UDCCS7_RPC bit(1)
#define UDCCS7_RFS bit(0)
/* UDCCS8 bits - see Table 12-24 in [1], Table 12-16 in [2] */
/* UDCCS8 bits - see Table 12-24 in [1], Table 12-16 in [2], Table 12-17 in [3] */
#define UDCCS8_TSP bit(7)
#define UDCCS8_TUR bit(3)
@ -297,7 +325,7 @@ typedef volatile struct UDC_registers {
#define UDCCS8_TPC bit(1)
#define UDCCS8_TFS bit(0)
/* UDCCS9 bits - see Table 12-25 in [1], Table 12-17 in [2] */
/* UDCCS9 bits - see Table 12-25 in [1], Table 12-17 in [2], Table 12-18 in [3] */
#define UDCCS9_RSP bit(7)
#define UDCCS9_RNE bit(6)
@ -306,7 +334,7 @@ typedef volatile struct UDC_registers {
#define UDCCS9_RPC bit(1)
#define UDCCS9_RFS bit(0)
/* UDCCS10 bits - see Table 12-26 in [1], Table 12-18 in [2] */
/* UDCCS10 bits - see Table 12-26 in [1], Table 12-18 in [2], Table 12-19 in [3] */
#define UDCCS10_TSP bit(7)
#define UDCCS10_FST bit(5)
@ -316,7 +344,7 @@ typedef volatile struct UDC_registers {
#define UDCCS10_TPC bit(1)
#define UDCCS10_TFS bit(0)
/* UDCCS11 bits - see Table 12-22 in [1], Table 12-14 in [2] */
/* UDCCS11 bits - see Table 12-22 in [1], Table 12-14 in [2], Table 12-15 in [3] */
#define UDCCS11_TSP bit(7)
#define UDCCS11_FST bit(5)
@ -326,7 +354,7 @@ typedef volatile struct UDC_registers {
#define UDCCS11_TPC bit(1)
#define UDCCS11_TFS bit(0)
/* UDCCS12 bits - see Table 12-23 in [1], Table 12-15 in [2] */
/* UDCCS12 bits - see Table 12-23 in [1], Table 12-15 in [2], Table 12-16 in [3] */
#define UDCCS12_RSP bit(7)
#define UDCCS12_RNE bit(6)
@ -336,7 +364,7 @@ typedef volatile struct UDC_registers {
#define UDCCS12_RPC bit(1)
#define UDCCS12_RFS bit(0)
/* UDCCS13 bits - see Table 12-24 in [1], Table 12-16 in [2] */
/* UDCCS13 bits - see Table 12-24 in [1], Table 12-16 in [2], Table 12-17 in [3] */
#define UDCCS13_TSP bit(7)
#define UDCCS13_TUR bit(3)
@ -344,7 +372,7 @@ typedef volatile struct UDC_registers {
#define UDCCS13_TPC bit(1)
#define UDCCS13_TFS bit(0)
/* UDCCS14 bits - see Table 12-25 in [1], Table 12-17 in [2] */
/* UDCCS14 bits - see Table 12-25 in [1], Table 12-17 in [2], Table 12-18 in [3] */
#define UDCCS14_RSP bit(7)
#define UDCCS14_RNE bit(6)
@ -353,7 +381,7 @@ typedef volatile struct UDC_registers {
#define UDCCS14_RPC bit(1)
#define UDCCS14_RFS bit(0)
/* UDCCS15 bits - see Table 12-26 in [1], Table 12-18 in [2] */
/* UDCCS15 bits - see Table 12-26 in [1], Table 12-18 in [2], Table 12-19 in [3] */
#define UDCCS15_TSP bit(7)
#define UDCCS15_FST bit(5)
@ -363,7 +391,7 @@ typedef volatile struct UDC_registers {
#define UDCCS15_TPC bit(1)
#define UDCCS15_TFS bit(0)
/* UICR0 bits - see Table 12-27 in [1], Table 12-19 in [2] */
/* UICR0 bits - see Table 12-27 in [1], Table 12-19 in [2], Table 12-20 in [3] */
#define UICR0_IM7 bit(7)
#define UICR0_IM6 bit(6)
@ -374,7 +402,7 @@ typedef volatile struct UDC_registers {
#define UICR0_IM1 bit(1)
#define UICR0_IM0 bit(0)
/* UICR1 bits - see Table 12-28 in [1], Table 12-20 in [2] */
/* UICR1 bits - see Table 12-28 in [1], Table 12-20 in [2], Table 12-21 in [3] */
#define UICR1_IM15 bit(7)
#define UICR1_IM14 bit(6)
@ -385,7 +413,7 @@ typedef volatile struct UDC_registers {
#define UICR1_IM9 bit(1)
#define UICR1_IM8 bit(0)
/* USIR0 bits - see Table 12-29 in [1], Table 12-21 in [2] */
/* USIR0 bits - see Table 12-29 in [1], Table 12-21 in [2], Table 12-22 in [3] */
#define USIR0_IR7 bit(7)
#define USIR0_IR6 bit(6)
@ -396,7 +424,7 @@ typedef volatile struct UDC_registers {
#define USIR0_IR1 bit(1)
#define USIR0_IR0 bit(0)
/* USIR1 bits - see Table 12-30 in [1], Table 12-22 in [2] */
/* USIR1 bits - see Table 12-30 in [1], Table 12-22 in [2], Table 12-23 in [3] */
#define USIR1_IR15 bit(7)
#define USIR1_IR14 bit(6)
@ -407,7 +435,7 @@ typedef volatile struct UDC_registers {
#define USIR1_IR9 bit(1)
#define USIR1_IR8 bit(0)
/* UFNHR bits - see Table 12-31 in [1], Table 12-23 in [2] */
/* UFNHR bits - see Table 12-31 in [1], Table 12-23 in [2], Table 12-24 in [3] */
#define UFNHR_SIR bit(7)
#define UFNHR_SIM bit(6)
@ -418,19 +446,19 @@ typedef volatile struct UDC_registers {
#define UFNHR_FNMSB(x) bits_val(2,0,x)
#define get_UFNHR_FNMSB(x) bits_get(2,0,x)
/* UFNLR bits - see Table 12-32 in [1], Table 12-24 in [2] */
/* UFNLR bits - see Table 12-32 in [1], Table 12-24 in [2], Table 12-25 in [3] */
#define UNFLR_FNLSB_MASK bits(7,0)
#define UFNLR_FNLSB(x) bits_val(7,0,x)
#define get_UFNLR_FNLSB(x) bits_get(7,0,x)
/* UBCRx bits - see Table 12-33 in [1], Table 12-25 in [2] */
/* UBCRx bits - see Table 12-33 in [1], Table 12-25 in [2], Table 12-26 in [3] */
#define UBCR_BC_MASK bits(7,0)
#define UBCR_BC(x) bits_val(7,0,x)
#define get_UBCR_BC(x) bits_get(7,0,x)
/* UDDRx bits - see 12.6.15 - 12.6.20 in [1], 12.6.15 - 12.6.20 in [2] */
/* UDDRx bits - see 12.6.15 - 12.6.20 in [1], 12.6.15 - 12.6.20 in [2], 12.6.16 - 12.6.21 in [3] */
#define UDDR_DATA_MASK bits(7,0)
#define UDDR_DATA(x) bits_val(7,0,x)

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